1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.backend.fu.FuConfig.StaCfg 28import xiangshan.backend.rob.DebugLsInfoBundle 29import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 30import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 31 32 33// Store Pipeline Stage 0 34// Generate addr, use addr to query DCache and DTLB 35class StoreUnit_S0(implicit p: Parameters) extends XSModule { 36 val io = IO(new Bundle() { 37 val in = Flipped(Decoupled(new MemExuInput)) 38 val out = Decoupled(new LsPipelineBundle) 39 val dtlbReq = DecoupledIO(new TlbReq) 40 }) 41 42 // send req to dtlb 43 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 44 val imm12 = WireInit(io.in.bits.uop.imm(11,0)) 45 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 46 val saddr_hi = Mux(saddr_lo(12), 47 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 48 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 49 ) 50 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 51 52 io.dtlbReq.bits.vaddr := saddr 53 io.dtlbReq.valid := io.in.valid 54 io.dtlbReq.bits.cmd := TlbCmd.write 55 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.fuOpType) 56 io.dtlbReq.bits.kill := DontCare 57 io.dtlbReq.bits.memidx.is_ld := false.B 58 io.dtlbReq.bits.memidx.is_st := true.B 59 io.dtlbReq.bits.memidx.idx := io.in.bits.uop.sqIdx.value 60 io.dtlbReq.bits.debug.robIdx := io.in.bits.uop.robIdx 61 io.dtlbReq.bits.no_translate := false.B 62 io.dtlbReq.bits.debug.pc := io.in.bits.uop.pc 63 io.dtlbReq.bits.debug.isFirstIssue := io.in.bits.isFirstIssue 64 65 io.out.bits := DontCare 66 io.out.bits.vaddr := saddr 67 68 // Now data use its own io 69 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 70 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 71 io.out.bits.uop := io.in.bits.uop 72 io.out.bits.miss := DontCare 73 io.out.bits.rsIdx := io.in.bits.iqIdx // guarded by io.in.valid 74 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.fuOpType(1,0)) 75 io.out.bits.isFirstIssue := io.in.bits.isFirstIssue // guarded by io.in.valid 76 io.out.bits.wlineflag := io.in.bits.uop.fuOpType === LSUOpType.cbo_zero 77 io.out.valid := io.in.valid 78 io.in.ready := io.out.ready 79 when(io.in.valid && io.in.bits.isFirstIssue) { 80 io.out.bits.uop.debugInfo.tlbFirstReqTime := GTimer() 81 } 82 83 // exception check 84 val addrAligned = LookupTree(io.in.bits.uop.fuOpType(1,0), List( 85 "b00".U -> true.B, //b 86 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 87 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 88 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 89 )) 90 91 io.out.bits.uop.exceptionVec(storeAddrMisaligned) := !addrAligned 92 93 XSPerfAccumulate("in_valid", io.in.valid) 94 XSPerfAccumulate("in_fire", io.in.fire) 95 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 96 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 97 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 98 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.in.bits.isFirstIssue) 99 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.in.bits.isFirstIssue) 100} 101 102// Store Pipeline Stage 1 103// TLB resp (send paddr to dcache) 104class StoreUnit_S1(implicit p: Parameters) extends XSModule { 105 val io = IO(new Bundle() { 106 val in = Flipped(Decoupled(new LsPipelineBundle)) 107 val out = Decoupled(new LsPipelineBundle) 108 val lsq = ValidIO(new LsPipelineBundle()) 109 val dtlbResp = Flipped(DecoupledIO(new TlbResp())) 110 val rsFeedback = ValidIO(new RSFeedback) 111 val reExecuteQuery = Valid(new LoadReExecuteQueryIO) 112 }) 113 114 // mmio cbo decoder 115 val is_mmio_cbo = io.in.bits.uop.fuOpType === LSUOpType.cbo_clean || 116 io.in.bits.uop.fuOpType === LSUOpType.cbo_flush || 117 io.in.bits.uop.fuOpType === LSUOpType.cbo_inval 118 119 val s1_paddr = io.dtlbResp.bits.paddr(0) 120 val s1_tlb_miss = io.dtlbResp.bits.miss 121 122 val s1_mmio = is_mmio_cbo 123 val s1_exception = ExceptionNO.selectByFu(io.out.bits.uop.exceptionVec, StaCfg).asUInt.orR 124 125 io.in.ready := true.B 126 127 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 128 129 // st-ld violation dectect request. 130 io.reExecuteQuery.valid := io.in.valid && !s1_tlb_miss 131 io.reExecuteQuery.bits.robIdx := io.in.bits.uop.robIdx 132 io.reExecuteQuery.bits.paddr := s1_paddr 133 io.reExecuteQuery.bits.mask := io.in.bits.mask 134 135 // Send TLB feedback to store issue queue 136 // Store feedback is generated in store_s1, sent to RS in store_s2 137 io.rsFeedback.valid := io.in.valid 138 io.rsFeedback.bits.hit := !s1_tlb_miss 139 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 140 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 141 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 142 XSDebug(io.rsFeedback.valid, 143 "S1 Store: tlbHit: %d robIdx: %d\n", 144 io.rsFeedback.bits.hit, 145 io.rsFeedback.bits.rsIdx 146 ) 147 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 148 149 // get paddr from dtlb, check if rollback is needed 150 // writeback store inst to lsq 151 io.out.valid := io.in.valid && !s1_tlb_miss 152 io.out.bits := io.in.bits 153 io.out.bits.paddr := s1_paddr 154 io.out.bits.miss := false.B 155 io.out.bits.mmio := s1_mmio 156 io.out.bits.atomic := s1_mmio 157 io.out.bits.uop.exceptionVec(storePageFault) := io.dtlbResp.bits.excp(0).pf.st 158 io.out.bits.uop.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp(0).af.st 159 160 io.lsq.valid := io.in.valid 161 io.lsq.bits := io.out.bits 162 io.lsq.bits.miss := s1_tlb_miss 163 164 // mmio inst with exception will be writebacked immediately 165 // io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 166 167 // write below io.out.bits assign sentence to prevent overwriting values 168 val s1_tlb_memidx = io.dtlbResp.bits.memidx 169 when(s1_tlb_memidx.is_st && io.dtlbResp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === io.out.bits.uop.sqIdx.value) { 170 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 171 io.out.bits.uop.debugInfo.tlbRespTime := GTimer() 172 } 173 174 XSPerfAccumulate("in_valid", io.in.valid) 175 XSPerfAccumulate("in_fire", io.in.fire) 176 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 177 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 178 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 179} 180 181class StoreUnit_S2(implicit p: Parameters) extends XSModule { 182 val io = IO(new Bundle() { 183 val in = Flipped(Decoupled(new LsPipelineBundle)) 184 val pmpResp = Flipped(new PMPRespBundle) 185 val static_pm = Input(Valid(Bool())) 186 val out = Decoupled(new LsPipelineBundle) 187 }) 188 val pmp = WireInit(io.pmpResp) 189 when (io.static_pm.valid) { 190 pmp.ld := false.B 191 pmp.st := false.B 192 pmp.instr := false.B 193 pmp.mmio := io.static_pm.bits 194 } 195 196 val s2_exception = ExceptionNO.selectByFu(io.out.bits.uop.exceptionVec, StaCfg).asUInt.orR 197 val is_mmio = io.in.bits.mmio || pmp.mmio 198 199 io.in.ready := true.B 200 io.out.bits := io.in.bits 201 io.out.bits.mmio := is_mmio && !s2_exception 202 io.out.bits.atomic := io.in.bits.atomic || pmp.atomic 203 io.out.bits.uop.exceptionVec(storeAccessFault) := io.in.bits.uop.exceptionVec(storeAccessFault) || pmp.st 204 io.out.valid := io.in.valid && (!is_mmio || s2_exception) 205} 206 207class StoreUnit_S3(implicit p: Parameters) extends XSModule { 208 val io = IO(new Bundle() { 209 val in = Flipped(Decoupled(new LsPipelineBundle)) 210 val stout = DecoupledIO(new MemExuOutput) // writeback store 211 }) 212 213 io.in.ready := true.B 214 215 io.stout.valid := io.in.valid 216 io.stout.bits.uop := io.in.bits.uop 217 io.stout.bits.data := DontCare 218 io.stout.bits.debug.isMMIO := io.in.bits.mmio 219 io.stout.bits.debug.paddr := io.in.bits.paddr 220 io.stout.bits.debug.vaddr := io.in.bits.vaddr 221 io.stout.bits.debug.isPerfCnt := false.B 222} 223 224class StoreUnit(implicit p: Parameters) extends XSModule { 225 val io = IO(new Bundle() { 226 val stin = Flipped(Decoupled(new MemExuInput)) 227 val redirect = Flipped(ValidIO(new Redirect)) 228 val feedbackSlow = ValidIO(new RSFeedback) 229 val tlb = new TlbRequestIO() 230 val pmp = Flipped(new PMPRespBundle()) 231 val lsq = ValidIO(new LsPipelineBundle) 232 val lsq_replenish = Output(new LsPipelineBundle()) 233 val stout = DecoupledIO(new MemExuOutput) // writeback store 234 // store mask, send to sq in store_s0 235 val storeMaskOut = Valid(new StoreMaskBundle) 236 val reExecuteQuery = Valid(new LoadReExecuteQueryIO) 237 val issue = Valid(new MemExuInput) 238 val debug_ls = Output(new DebugLsInfoBundle) 239 }) 240 241 val store_s0 = Module(new StoreUnit_S0) 242 val store_s1 = Module(new StoreUnit_S1) 243 val store_s2 = Module(new StoreUnit_S2) 244 val store_s3 = Module(new StoreUnit_S3) 245 246 store_s0.io.in <> io.stin 247 store_s0.io.dtlbReq <> io.tlb.req 248 io.tlb.req_kill := false.B 249 250 io.storeMaskOut.valid := store_s0.io.in.valid 251 io.storeMaskOut.bits.mask := store_s0.io.out.bits.mask 252 io.storeMaskOut.bits.sqIdx := store_s0.io.out.bits.uop.sqIdx 253 254 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 255 io.issue.valid := store_s1.io.in.valid && !store_s1.io.dtlbResp.bits.miss 256 io.issue.bits := RegEnable(store_s0.io.in.bits, store_s0.io.in.valid) 257 258 store_s1.io.dtlbResp <> io.tlb.resp 259 io.lsq <> store_s1.io.lsq 260 io.reExecuteQuery := store_s1.io.reExecuteQuery 261 262 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 263 264 // feedback tlb miss to RS in store_s2 265 io.feedbackSlow.bits := RegNext(store_s1.io.rsFeedback.bits) 266 io.feedbackSlow.valid := RegNext(store_s1.io.rsFeedback.valid && !store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 267 268 store_s2.io.pmpResp <> io.pmp 269 store_s2.io.static_pm := RegNext(io.tlb.resp.bits.static_pm) 270 io.lsq_replenish := store_s2.io.out.bits // mmio and exception 271 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 272 273 store_s3.io.stout <> io.stout 274 275 io.debug_ls := DontCare 276 io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue 277 io.debug_ls.s1_robIdx := store_s1.io.in.bits.uop.robIdx.value 278 279 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 280 XSDebug(cond, 281 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 282 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 283 p"op ${Binary(pipeline.uop.fuOpType)} " + 284 p"data ${Hexadecimal(pipeline.data)} " + 285 p"mask ${Hexadecimal(pipeline.mask)}\n" 286 ) 287 } 288 289 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 290 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 291} 292