1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.DebugLsInfoBundle 30import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 31import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 32 33class StoreUnit(implicit p: Parameters) extends XSModule with HasDCacheParameters { 34 val io = IO(new Bundle() { 35 val redirect = Flipped(ValidIO(new Redirect)) 36 val stin = Flipped(Decoupled(new MemExuInput)) 37 val issue = Valid(new MemExuInput) 38 val tlb = new TlbRequestIO() 39 val dcache = new DCacheStoreIO 40 val pmp = Flipped(new PMPRespBundle()) 41 val lsq = ValidIO(new LsPipelineBundle) 42 val lsq_replenish = Output(new LsPipelineBundle()) 43 val feedback_slow = ValidIO(new RSFeedback) 44 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 45 // provide prefetch info to sms 46 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 47 val stld_nuke_query = Valid(new StoreNukeQueryIO) 48 val stout = DecoupledIO(new MemExuOutput) // writeback store 49 // store mask, send to sq in store_s0 50 val st_mask_out = Valid(new StoreMaskBundle) 51 val debug_ls = Output(new DebugLsInfoBundle) 52 }) 53 54 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 55 56 // Pipeline 57 // -------------------------------------------------------------------------------- 58 // stage 0 59 // -------------------------------------------------------------------------------- 60 // generate addr, use addr to query DCache and DTLB 61 val s0_iss_valid = io.stin.valid 62 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 63 val s0_valid = s0_iss_valid || s0_prf_valid 64 val s0_use_flow_rs = s0_iss_valid 65 val s0_use_flow_prf = !s0_iss_valid && s0_prf_valid 66 val s0_in = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 67 val s0_isFirstIssue = Mux(s0_use_flow_rs, io.stin.bits.isFirstIssue, false.B) 68 val s0_rsIdx = Mux(s0_use_flow_rs, io.stin.bits.iqIdx, 0.U) 69 val s0_size = Mux(s0_use_flow_rs, LSUOpType.size(s0_in.uop.fuOpType), 3.U) 70 val s0_mem_idx = Mux(s0_use_flow_rs, s0_in.uop.sqIdx.value, 0.U) 71 val s0_rob_idx = Mux(s0_use_flow_rs, s0_in.uop.robIdx, 0.U.asTypeOf(s0_in.uop.robIdx)) 72 val s0_pc = Mux(s0_use_flow_rs, s0_in.uop.pc, 0.U) 73 val s0_instr_type = Mux(s0_use_flow_rs, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 74 val s0_wlineflag = Mux(s0_use_flow_rs, s0_in.uop.fuOpType === LSUOpType.cbo_zero, false.B) 75 val s0_out = Wire(new LsPipelineBundle) 76 val s0_kill = s0_in.uop.robIdx.needFlush(io.redirect) 77 val s0_can_go = s1_ready 78 val s0_fire = s0_valid && !s0_kill && s0_can_go 79 80 // generate addr 81 // val saddr = s0_in.bits.src(0) + SignExt(s0_in.bits.uop.imm(11,0), VAddrBits) 82 val imm12 = WireInit(s0_in.uop.imm(11,0)) 83 val saddr_lo = s0_in.src(0)(11,0) + Cat(0.U(1.W), imm12) 84 val saddr_hi = Mux(saddr_lo(12), 85 Mux(imm12(11), s0_in.src(0)(VAddrBits-1, 12), s0_in.src(0)(VAddrBits-1, 12)+1.U), 86 Mux(imm12(11), s0_in.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), s0_in.src(0)(VAddrBits-1, 12)), 87 ) 88 val s0_saddr = Cat(saddr_hi, saddr_lo(11,0)) 89 val s0_vaddr = Mux(s0_use_flow_rs, s0_saddr, io.prefetch_req.bits.vaddr) 90 val s0_mask = Mux(s0_use_flow_rs, genVWmask(s0_saddr, s0_in.uop.fuOpType(1,0)), 3.U) 91 92 io.tlb.req.valid := s0_valid 93 io.tlb.req.bits.vaddr := s0_vaddr 94 io.tlb.req.bits.cmd := TlbCmd.write 95 io.tlb.req.bits.size := s0_size 96 io.tlb.req.bits.kill := false.B 97 io.tlb.req.bits.memidx.is_ld := false.B 98 io.tlb.req.bits.memidx.is_st := true.B 99 io.tlb.req.bits.memidx.idx := s0_mem_idx 100 io.tlb.req.bits.debug.robIdx := s0_rob_idx 101 io.tlb.req.bits.no_translate := false.B 102 io.tlb.req.bits.debug.pc := s0_pc 103 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 104 io.tlb.req_kill := false.B 105 106 // Dcache access here: not **real** dcache write 107 // just read meta and tag in dcache, to find out the store will hit or miss 108 109 // NOTE: The store request does not wait for the dcache to be ready. 110 // If the dcache is not ready at this time, the dcache is not queried. 111 // But, store prefetch request will always wait for dcache to be ready to make progress. 112 io.dcache.req.valid := s0_fire 113 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 114 io.dcache.req.bits.vaddr := s0_vaddr 115 io.dcache.req.bits.instrtype := s0_instr_type 116 117 s0_out := DontCare 118 s0_out.vaddr := s0_vaddr 119 // Now data use its own io 120 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.fuOpType(1,0)) 121 s0_out.data := s0_in.src(1) // FIXME: remove data from pipeline 122 s0_out.uop := s0_in.uop 123 s0_out.miss := false.B 124 s0_out.rsIdx := s0_rsIdx 125 s0_out.mask := s0_mask 126 s0_out.isFirstIssue := s0_isFirstIssue 127 s0_out.isHWPrefetch := s0_use_flow_prf 128 s0_out.wlineflag := s0_wlineflag 129 when(s0_valid && s0_isFirstIssue) { 130 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 131 } 132 133 // exception check 134 val s0_addr_aligned = LookupTree(s0_in.uop.fuOpType(1,0), List( 135 "b00".U -> true.B, //b 136 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 137 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 138 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 139 )) 140 s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_flow_rs, !s0_addr_aligned, false.B) 141 142 io.st_mask_out.valid := s0_use_flow_rs 143 io.st_mask_out.bits.mask := s0_out.mask 144 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 145 146 io.stin.ready := s1_ready 147 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid 148 149 // Pipeline 150 // -------------------------------------------------------------------------------- 151 // stage 1 152 // -------------------------------------------------------------------------------- 153 // TLB resp (send paddr to dcache) 154 val s1_valid = RegInit(false.B) 155 val s1_in = RegEnable(s0_out, s0_fire) 156 val s1_out = Wire(new LsPipelineBundle) 157 val s1_kill = Wire(Bool()) 158 val s1_can_go = s2_ready 159 val s1_fire = s1_valid && !s1_kill && s1_can_go 160 161 // mmio cbo decoder 162 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 163 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 164 s1_in.uop.fuOpType === LSUOpType.cbo_inval 165 val s1_paddr = io.tlb.resp.bits.paddr(0) 166 val s1_tlb_miss = io.tlb.resp.bits.miss 167 val s1_mmio = s1_mmio_cbo 168 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 169 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || s1_tlb_miss 170 171 s1_ready := !s1_valid || s1_kill || s2_ready 172 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 173 when (s0_fire) { s1_valid := true.B } 174 .elsewhen (s1_fire) { s1_valid := false.B } 175 .elsewhen (s1_kill) { s1_valid := false.B } 176 177 // st-ld violation dectect request. 178 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 179 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 180 io.stld_nuke_query.bits.paddr := s1_paddr 181 io.stld_nuke_query.bits.mask := s1_in.mask 182 183 // issue 184 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 185 io.issue.bits := RegEnable(s0_in, s0_valid) 186 187 188 // Send TLB feedback to store issue queue 189 // Store feedback is generated in store_s1, sent to RS in store_s2 190 val s1_feedback = Wire(Valid(new RSFeedback)) 191 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 192 s1_feedback.bits.hit := !s1_tlb_miss 193 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 194 s1_feedback.bits.robIdx := s1_out.uop.robIdx 195 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 196 s1_feedback.bits.dataInvalidSqIdx := DontCare 197 198 XSDebug(s1_feedback.valid, 199 "S1 Store: tlbHit: %d robIdx: %d\n", 200 s1_feedback.bits.hit, 201 s1_feedback.bits.robIdx.value 202 ) 203 204 io.feedback_slow := s1_feedback 205 206 // get paddr from dtlb, check if rollback is needed 207 // writeback store inst to lsq 208 s1_out := s1_in 209 s1_out.paddr := s1_paddr 210 s1_out.miss := false.B 211 s1_out.mmio := s1_mmio 212 s1_out.tlbMiss := s1_tlb_miss 213 s1_out.atomic := s1_mmio 214 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 215 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 216 217 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch 218 io.lsq.bits := s1_out 219 io.lsq.bits.miss := s1_tlb_miss 220 221 // kill dcache write intent request when tlb miss or exception 222 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 223 io.dcache.s1_paddr := s1_paddr 224 225 // write below io.out.bits assign sentence to prevent overwriting values 226 val s1_tlb_memidx = io.tlb.resp.bits.memidx 227 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 228 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 229 s1_out.uop.debugInfo.tlbRespTime := GTimer() 230 } 231 232 // Pipeline 233 // -------------------------------------------------------------------------------- 234 // stage 2 235 // -------------------------------------------------------------------------------- 236 // mmio check 237 val s2_valid = RegInit(false.B) 238 val s2_in = RegEnable(s1_out, s1_fire) 239 val s2_out = Wire(new LsPipelineBundle) 240 val s2_kill = Wire(Bool()) 241 val s2_can_go = s3_ready 242 val s2_fire = s2_valid && !s2_kill && s2_can_go 243 244 s2_ready := !s2_valid || s2_kill || s3_ready 245 when (s1_fire) { s2_valid := true.B } 246 .elsewhen (s2_fire) { s2_valid := false.B } 247 .elsewhen (s2_kill) { s2_valid := false.B } 248 249 val s2_pmp = WireInit(io.pmp) 250 251 val s2_exception = ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR 252 val s2_mmio = s2_in.mmio || s2_pmp.mmio 253 s2_kill := (s2_mmio && !s2_exception) || s2_in.uop.robIdx.needFlush(io.redirect) 254 255 s2_out := s2_in 256 s2_out.mmio := s2_mmio && !s2_exception 257 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 258 s2_out.uop.exceptionVec(storeAccessFault) := s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st 259 260 // kill dcache write intent request when mmio or exception 261 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 262 io.dcache.s2_pc := s2_out.uop.pc 263 // TODO: dcache resp 264 io.dcache.resp.ready := true.B 265 266 // feedback tlb miss to RS in store_s2 267 io.feedback_slow.valid := RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) 268 io.feedback_slow.bits := RegNext(s1_feedback.bits) 269 270 // mmio and exception 271 io.lsq_replenish := s2_out 272 273 // prefetch related 274 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 275 276 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 277 // override miss bit 278 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss 279 // TODO: add prefetch and access bit 280 io.prefetch_train.bits.meta_prefetch := false.B 281 io.prefetch_train.bits.meta_access := false.B 282 if(EnableStorePrefetchSMS) { 283 io.prefetch_train.valid := s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch 284 }else { 285 io.prefetch_train.valid := false.B 286 } 287 288 // Pipeline 289 // -------------------------------------------------------------------------------- 290 // stage 3 291 // -------------------------------------------------------------------------------- 292 // store write back 293 val s3_valid = RegInit(false.B) 294 val s3_in = RegEnable(s2_out, s2_fire) 295 val s3_out = Wire(new MemExuOutput) 296 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 297 val s3_can_go = s3_ready 298 val s3_fire = s3_valid && !s3_kill && s3_can_go 299 300 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch } 301 .elsewhen (s3_fire) { s3_valid := false.B } 302 .elsewhen (s3_kill) { s3_valid := false.B } 303 304 // wb: writeback 305 val SelectGroupSize = RollbackGroupSize 306 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 307 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 308 309 s3_out := DontCare 310 s3_out.uop := s3_in.uop 311 s3_out.data := DontCare 312 s3_out.debug.isMMIO := s3_in.mmio 313 s3_out.debug.paddr := s3_in.paddr 314 s3_out.debug.vaddr := s3_in.vaddr 315 s3_out.debug.isPerfCnt := false.B 316 317 // Pipeline 318 // -------------------------------------------------------------------------------- 319 // stage x 320 // -------------------------------------------------------------------------------- 321 // delay TotalSelectCycles - 2 cycle(s) 322 val TotalDelayCycles = TotalSelectCycles - 2 323 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 324 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 325 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 326 327 // backward ready signal 328 s3_ready := sx_ready.head 329 for (i <- 0 until TotalDelayCycles + 1) { 330 if (i == 0) { 331 sx_valid(i) := s3_valid 332 sx_in(i) := s3_out 333 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 334 } else { 335 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 336 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 337 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 338 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 339 340 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 341 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 342 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 343 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 344 } 345 } 346 val sx_last_valid = sx_valid.takeRight(1).head 347 val sx_last_ready = sx_ready.takeRight(1).head 348 val sx_last_in = sx_in.takeRight(1).head 349 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 350 351 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) 352 io.stout.bits := sx_last_in 353 354 io.debug_ls := DontCare 355 io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 356 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 357 358 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 359 XSDebug(cond, 360 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 361 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 362 p"op ${Binary(pipeline.uop.fuOpType)} " + 363 p"data ${Hexadecimal(pipeline.data)} " + 364 p"mask ${Hexadecimal(pipeline.mask)}\n" 365 ) 366 } 367 368 printPipeLine(s0_out, s0_valid, "S0") 369 printPipeLine(s1_out, s1_valid, "S1") 370 371 // perf cnt 372 XSPerfAccumulate("s0_in_valid", s0_valid) 373 XSPerfAccumulate("s0_in_fire", s0_fire) 374 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 375 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_saddr(VAddrBits-1, 12) === s0_in.src(0)(VAddrBits-1, 12)) 376 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_saddr(VAddrBits-1, 12) =/= s0_in.src(0)(VAddrBits-1, 12)) 377 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_saddr(VAddrBits-1, 12) === s0_in.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 378 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_saddr(VAddrBits-1, 12) =/= s0_in.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 379 380 XSPerfAccumulate("s1_in_valid", s1_valid) 381 XSPerfAccumulate("s1_in_fire", s1_fire) 382 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 383 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 384 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 385 // end 386}