1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.cache._ 26import xiangshan.cache.mmu.{TlbPtwIO, TlbRequestIO, TlbReq, TlbResp, TlbCmd, TLB} 27 28// Store Pipeline Stage 0 29// Generate addr, use addr to query DCache and DTLB 30class StoreUnit_S0(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val in = Flipped(Decoupled(new ExuInput)) 33 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 34 val isFirstIssue = Input(Bool()) 35 val out = Decoupled(new LsPipelineBundle) 36 val dtlbReq = DecoupledIO(new TlbReq) 37 }) 38 39 // send req to dtlb 40 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 41 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 42 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 43 val saddr_hi = Mux(saddr_lo(12), 44 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 45 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 46 ) 47 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 48 49 io.dtlbReq.bits.vaddr := saddr 50 io.dtlbReq.valid := io.in.valid 51 io.dtlbReq.bits.cmd := TlbCmd.write 52 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 53 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 54 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 55 56 io.out.bits := DontCare 57 io.out.bits.vaddr := saddr 58 59 // Now data use its own io 60 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 61 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 62 io.out.bits.uop := io.in.bits.uop 63 io.out.bits.miss := DontCare 64 io.out.bits.rsIdx := io.rsIdx 65 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 66 io.out.bits.isFirstIssue := io.isFirstIssue 67 io.out.valid := io.in.valid 68 io.in.ready := io.out.ready 69 70 // exception check 71 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 72 "b00".U -> true.B, //b 73 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 74 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 75 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 76 )) 77 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 78 79 XSPerfAccumulate("in_valid", io.in.valid) 80 XSPerfAccumulate("in_fire", io.in.fire) 81 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.isFirstIssue) 82 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 83 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 84 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 85 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 86} 87 88// Store Pipeline Stage 1 89// TLB resp (send paddr to dcache) 90class StoreUnit_S1(implicit p: Parameters) extends XSModule { 91 val io = IO(new Bundle() { 92 val in = Flipped(Decoupled(new LsPipelineBundle)) 93 val out = Decoupled(new LsPipelineBundle) 94 val lsq = ValidIO(new LsPipelineBundle) 95 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 96 val rsFeedback = ValidIO(new RSFeedback) 97 }) 98 99 val s1_paddr = io.dtlbResp.bits.paddr 100 val s1_tlb_miss = io.dtlbResp.bits.miss 101 val s1_mmio = io.dtlbResp.bits.mmio 102 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 103 104 io.in.ready := true.B 105 106 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 107 108 // Send TLB feedback to store issue queue 109 io.rsFeedback.valid := io.in.valid 110 io.rsFeedback.bits.hit := !s1_tlb_miss 111 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 112 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 113 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 114 XSDebug(io.rsFeedback.valid, 115 "S1 Store: tlbHit: %d roqIdx: %d\n", 116 io.rsFeedback.bits.hit, 117 io.rsFeedback.bits.rsIdx 118 ) 119 120 121 // get paddr from dtlb, check if rollback is needed 122 // writeback store inst to lsq 123 io.lsq.valid := io.in.valid && !s1_tlb_miss 124 io.lsq.bits := io.in.bits 125 io.lsq.bits.paddr := s1_paddr 126 io.lsq.bits.miss := false.B 127 io.lsq.bits.mmio := s1_mmio && !s1_exception 128 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 129 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 130 131 // mmio inst with exception will be writebacked immediately 132 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 133 io.out.bits := io.lsq.bits 134 135 XSPerfAccumulate("in_valid", io.in.valid) 136 XSPerfAccumulate("in_fire", io.in.fire) 137 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 138 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 139 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 140} 141 142class StoreUnit_S2(implicit p: Parameters) extends XSModule { 143 val io = IO(new Bundle() { 144 val in = Flipped(Decoupled(new LsPipelineBundle)) 145 val out = Decoupled(new LsPipelineBundle) 146 }) 147 148 io.in.ready := true.B 149 io.out.bits := io.in.bits 150 io.out.valid := io.in.valid 151 152} 153 154class StoreUnit_S3(implicit p: Parameters) extends XSModule { 155 val io = IO(new Bundle() { 156 val in = Flipped(Decoupled(new LsPipelineBundle)) 157 val stout = DecoupledIO(new ExuOutput) // writeback store 158 }) 159 160 io.in.ready := true.B 161 162 io.stout.valid := io.in.valid 163 io.stout.bits.uop := io.in.bits.uop 164 io.stout.bits.data := DontCare 165 io.stout.bits.redirectValid := false.B 166 io.stout.bits.redirect := DontCare 167 io.stout.bits.debug.isMMIO := io.in.bits.mmio 168 io.stout.bits.debug.paddr := DontCare 169 io.stout.bits.debug.isPerfCnt := false.B 170 io.stout.bits.fflags := DontCare 171 172} 173 174class StoreUnit(implicit p: Parameters) extends XSModule { 175 val io = IO(new Bundle() { 176 val stin = Flipped(Decoupled(new ExuInput)) 177 val redirect = Flipped(ValidIO(new Redirect)) 178 val flush = Input(Bool()) 179 val rsFeedback = ValidIO(new RSFeedback) 180 val tlb = new TlbRequestIO() 181 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 182 val isFirstIssue = Input(Bool()) 183 val lsq = ValidIO(new LsPipelineBundle) 184 val stout = DecoupledIO(new ExuOutput) // writeback store 185 }) 186 187 val store_s0 = Module(new StoreUnit_S0) 188 val store_s1 = Module(new StoreUnit_S1) 189 val store_s2 = Module(new StoreUnit_S2) 190 val store_s3 = Module(new StoreUnit_S3) 191 192 store_s0.io.in <> io.stin 193 store_s0.io.dtlbReq <> io.tlb.req 194 store_s0.io.rsIdx := io.rsIdx 195 store_s0.io.isFirstIssue := io.isFirstIssue 196 197 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 198 199 store_s1.io.lsq <> io.lsq // send result to sq 200 store_s1.io.dtlbResp <> io.tlb.resp 201 store_s1.io.rsFeedback <> io.rsFeedback 202 203 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 204 205 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 206 207 store_s3.io.stout <> io.stout 208 209 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 210 XSDebug(cond, 211 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 212 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 213 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 214 p"data ${Hexadecimal(pipeline.data)} " + 215 p"mask ${Hexadecimal(pipeline.mask)}\n" 216 ) 217 } 218 219 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 220 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 221 222} 223