1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 28 29// Store Pipeline Stage 0 30// Generate addr, use addr to query DCache and DTLB 31class StoreUnit_S0(implicit p: Parameters) extends XSModule { 32 val io = IO(new Bundle() { 33 val in = Flipped(Decoupled(new ExuInput)) 34 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 35 val isFirstIssue = Input(Bool()) 36 val out = Decoupled(new LsPipelineBundle) 37 val dtlbReq = DecoupledIO(new TlbReq) 38 }) 39 40 // send req to dtlb 41 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 42 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 43 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 44 val saddr_hi = Mux(saddr_lo(12), 45 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 46 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 47 ) 48 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 49 50 io.dtlbReq.bits.vaddr := saddr 51 io.dtlbReq.valid := io.in.valid 52 io.dtlbReq.bits.cmd := TlbCmd.write 53 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 54 io.dtlbReq.bits.kill := DontCare 55 io.dtlbReq.bits.debug.robIdx := io.in.bits.uop.robIdx 56 io.dtlbReq.bits.no_translate := false.B 57 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 58 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 59 60 io.out.bits := DontCare 61 io.out.bits.vaddr := saddr 62 63 // Now data use its own io 64 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 65 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 66 io.out.bits.uop := io.in.bits.uop 67 io.out.bits.miss := DontCare 68 io.out.bits.rsIdx := io.rsIdx 69 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 70 io.out.bits.isFirstIssue := io.isFirstIssue 71 io.out.bits.wlineflag := io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_zero 72 io.out.valid := io.in.valid 73 io.in.ready := io.out.ready 74 75 // exception check 76 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 77 "b00".U -> true.B, //b 78 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 79 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 80 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 81 )) 82 83 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 84 85 XSPerfAccumulate("in_valid", io.in.valid) 86 XSPerfAccumulate("in_fire", io.in.fire) 87 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.isFirstIssue) 88 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 89 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 90 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 91 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 92} 93 94// Store Pipeline Stage 1 95// TLB resp (send paddr to dcache) 96class StoreUnit_S1(implicit p: Parameters) extends XSModule { 97 val io = IO(new Bundle() { 98 val in = Flipped(Decoupled(new LsPipelineBundle)) 99 val out = Decoupled(new LsPipelineBundle) 100 val lsq = ValidIO(new LsPipelineBundle()) 101 val dtlbResp = Flipped(DecoupledIO(new TlbResp())) 102 val rsFeedback = ValidIO(new RSFeedback) 103 val reExecuteQuery = Valid(new LoadReExecuteQueryIO) 104 }) 105 106 // mmio cbo decoder 107 val is_mmio_cbo = io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_clean || 108 io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_flush || 109 io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_inval 110 111 val s1_paddr = io.dtlbResp.bits.paddr(0) 112 val s1_tlb_miss = io.dtlbResp.bits.miss 113 val s1_mmio = is_mmio_cbo 114 val s1_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, staCfg).asUInt.orR 115 116 io.in.ready := true.B 117 118 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 119 120 // st-ld violation dectect request. 121 io.reExecuteQuery.valid := io.in.valid && !s1_tlb_miss 122 io.reExecuteQuery.bits.robIdx := io.in.bits.uop.robIdx 123 io.reExecuteQuery.bits.paddr := s1_paddr 124 io.reExecuteQuery.bits.mask := io.in.bits.mask 125 126 // Send TLB feedback to store issue queue 127 // Store feedback is generated in store_s1, sent to RS in store_s2 128 io.rsFeedback.valid := io.in.valid 129 io.rsFeedback.bits.hit := !s1_tlb_miss 130 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 131 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 132 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 133 XSDebug(io.rsFeedback.valid, 134 "S1 Store: tlbHit: %d robIdx: %d\n", 135 io.rsFeedback.bits.hit, 136 io.rsFeedback.bits.rsIdx 137 ) 138 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 139 140 // get paddr from dtlb, check if rollback is needed 141 // writeback store inst to lsq 142 io.out.valid := io.in.valid && !s1_tlb_miss 143 io.out.bits := io.in.bits 144 io.out.bits.paddr := s1_paddr 145 io.out.bits.miss := false.B 146 io.out.bits.mmio := s1_mmio 147 io.out.bits.atomic := s1_mmio 148 io.out.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp(0).pf.st 149 io.out.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp(0).af.st 150 151 io.lsq.valid := io.in.valid 152 io.lsq.bits := io.out.bits 153 io.lsq.bits.miss := s1_tlb_miss 154 155 // mmio inst with exception will be writebacked immediately 156 // io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 157 158 XSPerfAccumulate("in_valid", io.in.valid) 159 XSPerfAccumulate("in_fire", io.in.fire) 160 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 161 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 162 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 163} 164 165class StoreUnit_S2(implicit p: Parameters) extends XSModule { 166 val io = IO(new Bundle() { 167 val in = Flipped(Decoupled(new LsPipelineBundle)) 168 val pmpResp = Flipped(new PMPRespBundle) 169 val static_pm = Input(Valid(Bool())) 170 val out = Decoupled(new LsPipelineBundle) 171 }) 172 val pmp = WireInit(io.pmpResp) 173 when (io.static_pm.valid) { 174 pmp.ld := false.B 175 pmp.st := false.B 176 pmp.instr := false.B 177 pmp.mmio := io.static_pm.bits 178 } 179 180 val s2_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, staCfg).asUInt.orR 181 val is_mmio = io.in.bits.mmio || pmp.mmio 182 183 io.in.ready := true.B 184 io.out.bits := io.in.bits 185 io.out.bits.mmio := is_mmio && !s2_exception 186 io.out.bits.atomic := io.in.bits.atomic || pmp.atomic 187 io.out.bits.uop.cf.exceptionVec(storeAccessFault) := io.in.bits.uop.cf.exceptionVec(storeAccessFault) || pmp.st 188 io.out.valid := io.in.valid && (!is_mmio || s2_exception) 189} 190 191class StoreUnit_S3(implicit p: Parameters) extends XSModule { 192 val io = IO(new Bundle() { 193 val in = Flipped(Decoupled(new LsPipelineBundle)) 194 val stout = DecoupledIO(new ExuOutput) // writeback store 195 }) 196 197 io.in.ready := true.B 198 199 io.stout.valid := io.in.valid 200 io.stout.bits.uop := io.in.bits.uop 201 io.stout.bits.data := DontCare 202 io.stout.bits.redirectValid := false.B 203 io.stout.bits.redirect := DontCare 204 io.stout.bits.debug.isMMIO := io.in.bits.mmio 205 io.stout.bits.debug.paddr := io.in.bits.paddr 206 io.stout.bits.debug.vaddr := io.in.bits.vaddr 207 io.stout.bits.debug.isPerfCnt := false.B 208 io.stout.bits.fflags := DontCare 209 210} 211 212class StoreUnit(implicit p: Parameters) extends XSModule { 213 val io = IO(new Bundle() { 214 val stin = Flipped(Decoupled(new ExuInput)) 215 val redirect = Flipped(ValidIO(new Redirect)) 216 val feedbackSlow = ValidIO(new RSFeedback) 217 val tlb = new TlbRequestIO() 218 val pmp = Flipped(new PMPRespBundle()) 219 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 220 val isFirstIssue = Input(Bool()) 221 val lsq = ValidIO(new LsPipelineBundle) 222 val lsq_replenish = Output(new LsPipelineBundle()) 223 val stout = DecoupledIO(new ExuOutput) // writeback store 224 // store mask, send to sq in store_s0 225 val storeMaskOut = Valid(new StoreMaskBundle) 226 val reExecuteQuery = Valid(new LoadReExecuteQueryIO) 227 val issue = Valid(new ExuInput) 228 }) 229 230 val store_s0 = Module(new StoreUnit_S0) 231 val store_s1 = Module(new StoreUnit_S1) 232 val store_s2 = Module(new StoreUnit_S2) 233 val store_s3 = Module(new StoreUnit_S3) 234 235 store_s0.io.in <> io.stin 236 store_s0.io.dtlbReq <> io.tlb.req 237 io.tlb.req_kill := false.B 238 store_s0.io.rsIdx := io.rsIdx 239 store_s0.io.isFirstIssue := io.isFirstIssue 240 241 io.storeMaskOut.valid := store_s0.io.in.valid 242 io.storeMaskOut.bits.mask := store_s0.io.out.bits.mask 243 io.storeMaskOut.bits.sqIdx := store_s0.io.out.bits.uop.sqIdx 244 245 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 246 io.issue.valid := store_s1.io.in.valid && !store_s1.io.dtlbResp.bits.miss 247 io.issue.bits := RegEnable(store_s0.io.in.bits, store_s0.io.in.valid) 248 249 store_s1.io.dtlbResp <> io.tlb.resp 250 io.lsq <> store_s1.io.lsq 251 io.reExecuteQuery := store_s1.io.reExecuteQuery 252 253 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 254 255 // feedback tlb miss to RS in store_s2 256 io.feedbackSlow.bits := RegNext(store_s1.io.rsFeedback.bits) 257 io.feedbackSlow.valid := RegNext(store_s1.io.rsFeedback.valid && !store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 258 259 store_s2.io.pmpResp <> io.pmp 260 store_s2.io.static_pm := RegNext(io.tlb.resp.bits.static_pm) 261 io.lsq_replenish := store_s2.io.out.bits // mmio and exception 262 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 263 264 store_s3.io.stout <> io.stout 265 266 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 267 XSDebug(cond, 268 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 269 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 270 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 271 p"data ${Hexadecimal(pipeline.data)} " + 272 p"mask ${Hexadecimal(pipeline.mask)}\n" 273 ) 274 } 275 276 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 277 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 278} 279