1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9 10// Store Pipeline Stage 0 11// Generate addr, use addr to query DCache and DTLB 12class StoreUnit_S0 extends XSModule { 13 val io = IO(new Bundle() { 14 val in = Flipped(Decoupled(new ExuInput)) 15 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 16 val out = Decoupled(new LsPipelineBundle) 17 val dtlbReq = DecoupledIO(new TlbReq) 18 }) 19 20 // send req to dtlb 21 val saddr_old = io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN) 22 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 23 val saddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 24 val saddr_hi = Mux(imm12(11), 25 Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)), 26 Mux((saddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12)) 27 ) 28 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 29 when(io.in.fire() && saddr(VAddrBits-1,0) =/= (io.in.bits.src1 + SignExt(ImmUnion.S.toImm32(io.in.bits.uop.ctrl.imm), XLEN))(VAddrBits-1,0)){ 30 printf("saddr %x saddr_old %x\n", saddr, saddr_old(VAddrBits-1,0)) 31 } 32 33 io.dtlbReq.bits.vaddr := saddr 34 io.dtlbReq.valid := io.in.valid 35 io.dtlbReq.bits.cmd := TlbCmd.write 36 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 37 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 38 39 io.out.bits := DontCare 40 io.out.bits.vaddr := saddr 41 42 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 43 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 44 io.out.bits.data := io.in.bits.src2 45 } // not not touch fp store raw data 46 io.out.bits.uop := io.in.bits.uop 47 io.out.bits.miss := DontCare 48 io.out.bits.rsIdx := io.rsIdx 49 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 50 io.out.valid := io.in.valid 51 io.in.ready := io.out.ready 52 53 // exception check 54 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 55 "b00".U -> true.B, //b 56 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 57 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 58 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 59 )) 60 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 61 62} 63 64// Load Pipeline Stage 1 65// TLB resp (send paddr to dcache) 66class StoreUnit_S1 extends XSModule { 67 val io = IO(new Bundle() { 68 val in = Flipped(Decoupled(new LsPipelineBundle)) 69 val out = Decoupled(new LsPipelineBundle) 70 // val fp_out = Decoupled(new LsPipelineBundle) 71 val lsq = ValidIO(new LsPipelineBundle) 72 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 73 val tlbFeedback = ValidIO(new TlbFeedback) 74 }) 75 76 val s1_paddr = io.dtlbResp.bits.paddr 77 val s1_tlb_miss = io.dtlbResp.bits.miss 78 79 io.in.ready := true.B 80 81 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 82 83 // Send TLB feedback to store issue queue 84 io.tlbFeedback.valid := io.in.valid 85 io.tlbFeedback.bits.hit := !s1_tlb_miss 86 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 87 XSDebug(io.tlbFeedback.valid, 88 "S1 Store: tlbHit: %d roqIdx: %d\n", 89 io.tlbFeedback.bits.hit, 90 io.tlbFeedback.bits.rsIdx 91 ) 92 93 94 // get paddr from dtlb, check if rollback is needed 95 // writeback store inst to lsq 96 io.lsq.valid := io.in.valid && !s1_tlb_miss// TODO: && ! FP 97 io.lsq.bits := io.in.bits 98 io.lsq.bits.paddr := s1_paddr 99 io.lsq.bits.miss := false.B 100 io.lsq.bits.mmio := io.dtlbResp.bits.mmio 101 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 102 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 103 104 // mmio inst with exception will be writebacked immediately 105 val hasException = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 106 io.out.valid := io.in.valid && (!io.out.bits.mmio || hasException) && !s1_tlb_miss 107 io.out.bits := io.lsq.bits 108 109 // encode data for fp store 110 when(io.in.bits.uop.ctrl.src2Type === SrcType.fp){ 111 io.lsq.bits.data := genWdata(ieee(io.in.bits.data), io.in.bits.uop.ctrl.fuOpType(1,0)) 112 } 113 114} 115 116class StoreUnit_S2 extends XSModule { 117 val io = IO(new Bundle() { 118 val in = Flipped(Decoupled(new LsPipelineBundle)) 119 val out = Decoupled(new LsPipelineBundle) 120 }) 121 122 io.in.ready := true.B 123 io.out.bits := io.in.bits 124 io.out.valid := io.in.valid 125 126} 127 128class StoreUnit_S3 extends XSModule { 129 val io = IO(new Bundle() { 130 val in = Flipped(Decoupled(new LsPipelineBundle)) 131 val stout = DecoupledIO(new ExuOutput) // writeback store 132 }) 133 134 io.in.ready := true.B 135 136 io.stout.valid := io.in.valid 137 io.stout.bits.uop := io.in.bits.uop 138 io.stout.bits.data := DontCare 139 io.stout.bits.redirectValid := false.B 140 io.stout.bits.redirect := DontCare 141 io.stout.bits.debug.isMMIO := io.in.bits.mmio 142 io.stout.bits.debug.isPerfCnt := false.B 143 io.stout.bits.fflags := DontCare 144 145} 146 147class StoreUnit extends XSModule { 148 val io = IO(new Bundle() { 149 val stin = Flipped(Decoupled(new ExuInput)) 150 val redirect = Flipped(ValidIO(new Redirect)) 151 val flush = Input(Bool()) 152 val tlbFeedback = ValidIO(new TlbFeedback) 153 val dtlb = new TlbRequestIO() 154 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 155 val lsq = ValidIO(new LsPipelineBundle) 156 val stout = DecoupledIO(new ExuOutput) // writeback store 157 }) 158 159 val store_s0 = Module(new StoreUnit_S0) 160 val store_s1 = Module(new StoreUnit_S1) 161 val store_s2 = Module(new StoreUnit_S2) 162 val store_s3 = Module(new StoreUnit_S3) 163 164 store_s0.io.in <> io.stin 165 store_s0.io.dtlbReq <> io.dtlb.req 166 store_s0.io.rsIdx := io.rsIdx 167 168 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 169 170 store_s1.io.lsq <> io.lsq // send result to sq 171 store_s1.io.dtlbResp <> io.dtlb.resp 172 store_s1.io.tlbFeedback <> io.tlbFeedback 173 174 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 175 176 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 177 178 store_s3.io.stout <> io.stout 179 180 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 181 XSDebug(cond, 182 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 183 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 184 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 185 p"data ${Hexadecimal(pipeline.data)} " + 186 p"mask ${Hexadecimal(pipeline.mask)}\n" 187 ) 188 } 189 190 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 191 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 192 193} 194