1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.DebugLsInfoBundle 30import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 31import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 32 33class StoreUnit(implicit p: Parameters) extends XSModule with HasDCacheParameters { 34 val io = IO(new Bundle() { 35 val redirect = Flipped(ValidIO(new Redirect)) 36 val stin = Flipped(Decoupled(new MemExuInput)) 37 val issue = Valid(new MemExuInput) 38 val tlb = new TlbRequestIO() 39 val dcache = new DCacheStoreIO 40 val pmp = Flipped(new PMPRespBundle()) 41 val lsq = ValidIO(new LsPipelineBundle) 42 val lsq_replenish = Output(new LsPipelineBundle()) 43 val feedback_slow = ValidIO(new RSFeedback) 44 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 45 // provide prefetch info to sms 46 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 47 val stld_nuke_query = Valid(new StoreNukeQueryIO) 48 val stout = DecoupledIO(new MemExuOutput) // writeback store 49 // store mask, send to sq in store_s0 50 val st_mask_out = Valid(new StoreMaskBundle) 51 val debug_ls = Output(new DebugLsInfoBundle) 52 // vector 53 val vecstin = Flipped(Decoupled(new VecStorePipeBundle())) 54 val vec_isFirstIssue = Input(Bool()) 55 val lsq_vec = ValidIO(new LsPipelineBundle) // nuke check between vector stores and scalar loads 56 val vec_feedback_slow = ValidIO(new VSFQFeedback) 57 }) 58 59 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 60 61 // Pipeline 62 // -------------------------------------------------------------------------------- 63 // stage 0 64 // -------------------------------------------------------------------------------- 65 // generate addr, use addr to query DCache and DTLB 66 val s0_iss_valid = io.stin.valid 67 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 68 val s0_vec_valid = io.vecstin.valid 69 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid 70 val s0_use_flow_rs = s0_iss_valid 71 val s0_use_flow_vec = s0_vec_valid 72 val s0_use_flow_prf = !s0_iss_valid && !s0_vec_valid && s0_prf_valid 73 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 74 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 75 val s0_uop = Mux(s0_use_flow_rs, s0_stin.uop, s0_vecstin.uop) 76 val s0_isFirstIssue = s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 77 val s0_rsIdx = Mux(s0_use_flow_rs, io.stin.bits.iqIdx, 0.U) 78 val s0_size = Mux( 79 s0_use_flow_rs, 80 LSUOpType.size(s0_uop.fuOpType), 81 Mux( 82 s0_use_flow_vec, 83 io.vecstin.bits.alignedType, 84 3.U 85 ) 86 ) 87 val s0_mem_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.sqIdx.value, 0.U) 88 val s0_rob_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 89 val s0_pc = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.pc, 0.U) 90 val s0_instr_type = Mux(s0_use_flow_rs || s0_use_flow_vec, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 91 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 92 val s0_out = Wire(new LsPipelineBundle) 93 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 94 val s0_can_go = s1_ready 95 val s0_fire = s0_valid && !s0_kill && s0_can_go 96 // vector 97 val s0_exp = !s0_use_flow_vec || s0_vecstin.exp 98 val s0_flowPtr = s0_vecstin.flowPtr 99 assert(!(s0_iss_valid && s0_vec_valid)) 100 101 // generate addr 102 // val saddr = s0_in.bits.src(0) + SignExt(s0_in.bits.uop.imm(11,0), VAddrBits) 103 val imm12 = WireInit(s0_uop.imm(11,0)) 104 val saddr_lo = s0_stin.src(0)(11,0) + Cat(0.U(1.W), imm12) 105 val saddr_hi = Mux(saddr_lo(12), 106 Mux(imm12(11), s0_stin.src(0)(VAddrBits-1, 12), s0_stin.src(0)(VAddrBits-1, 12)+1.U), 107 Mux(imm12(11), s0_stin.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), s0_stin.src(0)(VAddrBits-1, 12)), 108 ) 109 val s0_saddr = Cat(saddr_hi, saddr_lo(11,0)) 110 val s0_vaddr = Mux( 111 s0_use_flow_rs, 112 s0_saddr, 113 Mux( 114 s0_use_flow_vec, 115 s0_vecstin.vaddr, 116 io.prefetch_req.bits.vaddr 117 ) 118 ) 119 val s0_mask = Mux( 120 s0_use_flow_rs, 121 genVWmask(s0_saddr, s0_uop.fuOpType(1,0)), 122 Mux( 123 s0_use_flow_vec, 124 s0_vecstin.mask, 125 // -1.asSInt.asUInt 126 Fill(VLEN/8, 1.U(1.W)) 127 ) 128 ) 129 130 io.tlb.req.valid := s0_valid 131 io.tlb.req.bits.vaddr := s0_vaddr 132 io.tlb.req.bits.cmd := TlbCmd.write 133 io.tlb.req.bits.size := s0_size 134 io.tlb.req.bits.kill := false.B 135 io.tlb.req.bits.memidx.is_ld := false.B 136 io.tlb.req.bits.memidx.is_st := true.B 137 io.tlb.req.bits.memidx.idx := s0_mem_idx 138 io.tlb.req.bits.debug.robIdx := s0_rob_idx 139 io.tlb.req.bits.no_translate := false.B 140 io.tlb.req.bits.debug.pc := s0_pc 141 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 142 io.tlb.req_kill := false.B 143 144 // Dcache access here: not **real** dcache write 145 // just read meta and tag in dcache, to find out the store will hit or miss 146 147 // NOTE: The store request does not wait for the dcache to be ready. 148 // If the dcache is not ready at this time, the dcache is not queried. 149 // But, store prefetch request will always wait for dcache to be ready to make progress. 150 io.dcache.req.valid := s0_fire 151 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 152 io.dcache.req.bits.vaddr := s0_vaddr 153 io.dcache.req.bits.instrtype := s0_instr_type 154 155 s0_out := DontCare 156 s0_out.vaddr := s0_vaddr 157 // Now data use its own io 158 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.fuOpType(1,0)) 159 s0_out.data := Mux(s0_use_flow_rs, s0_stin.src(1), s0_vecstin.src_vs3) // FIXME: remove data from pipeline 160 s0_out.uop := s0_uop 161 s0_out.miss := false.B 162 s0_out.rsIdx := s0_rsIdx 163 s0_out.mask := s0_mask 164 s0_out.isFirstIssue := s0_isFirstIssue 165 s0_out.isHWPrefetch := s0_use_flow_prf 166 s0_out.wlineflag := s0_wlineflag 167 s0_out.isvec := s0_use_flow_vec 168 s0_out.is128bit := false.B 169 s0_out.exp := s0_exp 170 // s0_out.fqIdx := s0_fqidx 171 s0_out.flowPtr := s0_flowPtr 172 when(s0_valid && s0_isFirstIssue) { 173 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 174 } 175 176 // exception check 177 val s0_addr_aligned = LookupTree(Mux(s0_use_flow_vec, s0_vecstin.alignedType, s0_uop.fuOpType(1, 0)), List( 178 "b00".U -> true.B, //b 179 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 180 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 181 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 182 )) 183 s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_flow_rs || s0_use_flow_vec, !s0_addr_aligned, false.B) 184 185 io.st_mask_out.valid := s0_use_flow_rs 186 io.st_mask_out.bits.mask := s0_out.mask 187 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 188 189 io.stin.ready := s1_ready 190 io.vecstin.ready := s1_ready 191 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid 192 193 // Pipeline 194 // -------------------------------------------------------------------------------- 195 // stage 1 196 // -------------------------------------------------------------------------------- 197 // TLB resp (send paddr to dcache) 198 val s1_valid = RegInit(false.B) 199 val s1_in = RegEnable(s0_out, s0_fire) 200 val s1_out = Wire(new LsPipelineBundle) 201 val s1_kill = Wire(Bool()) 202 val s1_can_go = s2_ready 203 val s1_fire = s1_valid && !s1_kill && s1_can_go 204 val s1_exp = RegEnable(s0_out.exp, true.B, s0_fire) 205 206 // mmio cbo decoder 207 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 208 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 209 s1_in.uop.fuOpType === LSUOpType.cbo_inval 210 val s1_paddr = io.tlb.resp.bits.paddr(0) 211 val s1_tlb_miss = io.tlb.resp.bits.miss 212 val s1_mmio = s1_mmio_cbo 213 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 214 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 215 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || s1_tlb_miss 216 217 s1_ready := !s1_valid || s1_kill || s2_ready 218 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 219 when (s0_fire) { s1_valid := true.B } 220 .elsewhen (s1_fire) { s1_valid := false.B } 221 .elsewhen (s1_kill) { s1_valid := false.B } 222 223 // st-ld violation dectect request. 224 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 225 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 226 io.stld_nuke_query.bits.paddr := s1_paddr 227 io.stld_nuke_query.bits.mask := s1_in.mask 228 229 // issue 230 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec 231 io.issue.bits := RegEnable(s0_stin, s0_valid) 232 233 234 // Send TLB feedback to store issue queue 235 // Store feedback is generated in store_s1, sent to RS in store_s2 236 val s1_feedback = Wire(Valid(new RSFeedback)) 237 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch && !s1_isvec 238 s1_feedback.bits.hit := !s1_tlb_miss 239 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 240 s1_feedback.bits.robIdx := s1_out.uop.robIdx 241 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 242 s1_feedback.bits.dataInvalidSqIdx := DontCare 243 244 XSDebug(s1_feedback.valid, 245 "S1 Store: tlbHit: %d robIdx: %d\n", 246 s1_feedback.bits.hit, 247 s1_feedback.bits.robIdx.value 248 ) 249 250 val s1_vec_feedback = Wire(Valid(new VSFQFeedback)) 251 s1_vec_feedback.valid := s1_valid && !s1_in.isHWPrefetch && s1_isvec 252 // s1_vec_feedback.bits.fqIdx := s1_out.fqIdx 253 s1_vec_feedback.bits.flowPtr := s1_out.flowPtr 254 s1_vec_feedback.bits.hit := !s1_tlb_miss 255 s1_vec_feedback.bits.sourceType := RSFeedbackType.tlbMiss 256 s1_vec_feedback.bits.paddr := s1_paddr 257 XSDebug(s1_vec_feedback.valid, 258 "Vector S1 Store: tlbHit: %d fqIdx: %d\n", 259 s1_vec_feedback.bits.hit, 260 s1_vec_feedback.bits.flowPtr.value 261 ) 262 263 // io.feedback_slow := s1_feedback 264 // io.vec_feedback_slow := s1_vec_feedback 265 266 // get paddr from dtlb, check if rollback is needed 267 // writeback store inst to lsq 268 s1_out := s1_in 269 s1_out.paddr := s1_paddr 270 s1_out.miss := false.B 271 s1_out.mmio := s1_mmio 272 s1_out.tlbMiss := s1_tlb_miss 273 s1_out.atomic := s1_mmio 274 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_exp 275 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_exp 276 277 // scalar store and scalar load nuke check, and also other purposes 278 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch && !s1_isvec 279 io.lsq.bits := s1_out 280 io.lsq.bits.miss := s1_tlb_miss 281 // vector store and scalar load nuke check 282 io.lsq_vec.valid := s1_valid && !s1_in.isHWPrefetch && s1_isvec 283 io.lsq_vec.bits := s1_out 284 io.lsq_vec.bits.miss := s1_tlb_miss 285 286 // kill dcache write intent request when tlb miss or exception 287 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 288 io.dcache.s1_paddr := s1_paddr 289 290 // write below io.out.bits assign sentence to prevent overwriting values 291 val s1_tlb_memidx = io.tlb.resp.bits.memidx 292 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 293 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 294 s1_out.uop.debugInfo.tlbRespTime := GTimer() 295 } 296 297 // Pipeline 298 // -------------------------------------------------------------------------------- 299 // stage 2 300 // -------------------------------------------------------------------------------- 301 // mmio check 302 val s2_valid = RegInit(false.B) 303 val s2_in = RegEnable(s1_out, s1_fire) 304 val s2_out = Wire(new LsPipelineBundle) 305 val s2_kill = Wire(Bool()) 306 val s2_can_go = s3_ready 307 val s2_fire = s2_valid && !s2_kill && s2_can_go 308 val s2_exp = RegEnable(s1_out.exp, true.B, s1_fire) 309 310 s2_ready := !s2_valid || s2_kill || s3_ready 311 when (s1_fire) { s2_valid := true.B } 312 .elsewhen (s2_fire) { s2_valid := false.B } 313 .elsewhen (s2_kill) { s2_valid := false.B } 314 315 val s2_pmp = WireInit(io.pmp) 316 317 val s2_exception = ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR 318 val s2_mmio = s2_in.mmio || s2_pmp.mmio 319 s2_kill := (s2_mmio && !s2_exception) || s2_in.uop.robIdx.needFlush(io.redirect) 320 321 s2_out := s2_in 322 s2_out.mmio := s2_mmio && !s2_exception 323 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 324 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st) && s2_exp 325 326 // kill dcache write intent request when mmio or exception 327 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 328 io.dcache.s2_pc := s2_out.uop.pc 329 // TODO: dcache resp 330 io.dcache.resp.ready := true.B 331 332 // feedback tlb miss to RS in store_s2 333 io.feedback_slow.valid := RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) 334 io.feedback_slow.bits := RegNext(s1_feedback.bits) 335 336 // vector feedback 337 io.vec_feedback_slow.valid := RegNext(s1_vec_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) 338 io.vec_feedback_slow.bits := RegNext(s1_vec_feedback.bits) 339 340 // mmio and exception 341 io.lsq_replenish := s2_out 342 343 // prefetch related 344 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 345 346 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 347 // override miss bit 348 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss 349 // TODO: add prefetch and access bit 350 io.prefetch_train.bits.meta_prefetch := false.B 351 io.prefetch_train.bits.meta_access := false.B 352 if(EnableStorePrefetchSMS) { 353 io.prefetch_train.valid := s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch 354 }else { 355 io.prefetch_train.valid := false.B 356 } 357 358 // Pipeline 359 // -------------------------------------------------------------------------------- 360 // stage 3 361 // -------------------------------------------------------------------------------- 362 // store write back 363 val s3_valid = RegInit(false.B) 364 val s3_in = RegEnable(s2_out, s2_fire) 365 val s3_out = Wire(new MemExuOutput) 366 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 367 val s3_can_go = s3_ready 368 val s3_fire = s3_valid && !s3_kill && s3_can_go 369 370 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch } 371 .elsewhen (s3_fire) { s3_valid := false.B } 372 .elsewhen (s3_kill) { s3_valid := false.B } 373 374 // wb: writeback 375 val SelectGroupSize = RollbackGroupSize 376 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 377 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 378 379 s3_out := DontCare 380 s3_out.uop := s3_in.uop 381 s3_out.data := DontCare 382 s3_out.debug.isMMIO := s3_in.mmio 383 s3_out.debug.paddr := s3_in.paddr 384 s3_out.debug.vaddr := s3_in.vaddr 385 s3_out.debug.isPerfCnt := false.B 386 387 // Pipeline 388 // -------------------------------------------------------------------------------- 389 // stage x 390 // -------------------------------------------------------------------------------- 391 // delay TotalSelectCycles - 2 cycle(s) 392 val TotalDelayCycles = TotalSelectCycles - 2 393 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 394 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 395 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 396 397 // backward ready signal 398 s3_ready := sx_ready.head 399 for (i <- 0 until TotalDelayCycles + 1) { 400 if (i == 0) { 401 sx_valid(i) := s3_valid 402 sx_in(i) := s3_out 403 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 404 } else { 405 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 406 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 407 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 408 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 409 410 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 411 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 412 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 413 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 414 } 415 } 416 val sx_last_valid = sx_valid.takeRight(1).head 417 val sx_last_ready = sx_ready.takeRight(1).head 418 val sx_last_in = sx_in.takeRight(1).head 419 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 420 421 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) 422 io.stout.bits := sx_last_in 423 424 io.debug_ls := DontCare 425 io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 426 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 427 428 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 429 XSDebug(cond, 430 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 431 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 432 p"op ${Binary(pipeline.uop.fuOpType)} " + 433 p"data ${Hexadecimal(pipeline.data)} " + 434 p"mask ${Hexadecimal(pipeline.mask)}\n" 435 ) 436 } 437 438 printPipeLine(s0_out, s0_valid, "S0") 439 printPipeLine(s1_out, s1_valid, "S1") 440 441 // perf cnt 442 XSPerfAccumulate("s0_in_valid", s0_valid) 443 XSPerfAccumulate("s0_in_fire", s0_fire) 444 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 445 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 446 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 447 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 448 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 449 450 XSPerfAccumulate("s1_in_valid", s1_valid) 451 XSPerfAccumulate("s1_in_fire", s1_fire) 452 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 453 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 454 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 455 // end 456}