1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.fu.FuType._ 30import xiangshan.backend.ctrlblock.DebugLsInfoBundle 31import xiangshan.backend.fu.NewCSR._ 32import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp, Pbmt} 33import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 34 35class StoreUnit(implicit p: Parameters) extends XSModule 36 with HasDCacheParameters 37 with HasVLSUParameters 38 { 39 val io = IO(new Bundle() { 40 val redirect = Flipped(ValidIO(new Redirect)) 41 val csrCtrl = Flipped(new CustomCSRCtrlIO) 42 val stin = Flipped(Decoupled(new MemExuInput)) 43 val issue = Valid(new MemExuInput) 44 // misalignBuffer issue path 45 val misalign_stin = Flipped(Decoupled(new LsPipelineBundle)) 46 val misalign_stout = Valid(new SqWriteBundle) 47 val tlb = new TlbRequestIO() 48 val dcache = new DCacheStoreIO 49 val pmp = Flipped(new PMPRespBundle()) 50 val lsq = ValidIO(new LsPipelineBundle) 51 val lsq_replenish = Output(new LsPipelineBundle()) 52 val feedback_slow = ValidIO(new RSFeedback) 53 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 54 // provide prefetch info to sms 55 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 56 // speculative for gated control 57 val s1_prefetch_spec = Output(Bool()) 58 val s2_prefetch_spec = Output(Bool()) 59 val stld_nuke_query = Valid(new StoreNukeQueryIO) 60 val stout = DecoupledIO(new MemExuOutput) // writeback store 61 val vecstout = DecoupledIO(new VecPipelineFeedbackIO(isVStore = true)) 62 // store mask, send to sq in store_s0 63 val st_mask_out = Valid(new StoreMaskBundle) 64 val debug_ls = Output(new DebugLsInfoBundle) 65 // vector 66 val vecstin = Flipped(Decoupled(new VecPipeBundle(isVStore = true))) 67 val vec_isFirstIssue = Input(Bool()) 68 // writeback to misalign buffer 69 val misalign_buf = Valid(new LsPipelineBundle) 70 // trigger 71 val fromCsrTrigger = Input(new CsrTriggerBundle) 72 }) 73 74 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 75 76 // Pipeline 77 // -------------------------------------------------------------------------------- 78 // stage 0 79 // -------------------------------------------------------------------------------- 80 // generate addr, use addr to query DCache and DTLB 81 val s0_iss_valid = io.stin.valid 82 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 83 val s0_vec_valid = io.vecstin.valid 84 val s0_ma_st_valid = io.misalign_stin.valid 85 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid || s0_ma_st_valid 86 val s0_use_flow_ma = s0_ma_st_valid 87 val s0_use_flow_vec = s0_vec_valid && !s0_ma_st_valid 88 val s0_use_flow_rs = s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 89 val s0_use_flow_prf = s0_prf_valid && !s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 90 val s0_use_non_prf_flow = s0_use_flow_rs || s0_use_flow_vec || s0_use_flow_ma 91 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 92 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 93 val s0_uop = Mux( 94 s0_use_flow_ma, 95 io.misalign_stin.bits.uop, 96 Mux( 97 s0_use_flow_rs, 98 s0_stin.uop, 99 s0_vecstin.uop 100 ) 101 ) 102 val s0_isFirstIssue = Mux( 103 s0_use_flow_ma, 104 false.B, 105 s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 106 ) 107 val s0_size = Mux(s0_use_non_prf_flow, s0_uop.fuOpType(2,0), 0.U)// may broken if use it in feature 108 val s0_mem_idx = Mux(s0_use_non_prf_flow, s0_uop.sqIdx.value, 0.U) 109 val s0_rob_idx = Mux(s0_use_non_prf_flow, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 110 val s0_pc = Mux(s0_use_non_prf_flow, s0_uop.pc, 0.U) 111 val s0_instr_type = Mux(s0_use_non_prf_flow, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 112 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 113 val s0_out = Wire(new LsPipelineBundle) 114 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 115 val s0_can_go = s1_ready 116 val s0_fire = s0_valid && !s0_kill && s0_can_go 117 val s0_is128bit = Mux(s0_use_flow_ma, io.misalign_stin.bits.is128bit, is128Bit(s0_vecstin.alignedType)) 118 // vector 119 val s0_vecActive = !s0_use_flow_vec || s0_vecstin.vecActive 120 // val s0_flowPtr = s0_vecstin.flowPtr 121 // val s0_isLastElem = s0_vecstin.isLastElem 122 val s0_secondInv = s0_vecstin.usSecondInv 123 val s0_elemIdx = s0_vecstin.elemIdx 124 val s0_alignedType = s0_vecstin.alignedType 125 val s0_mBIndex = s0_vecstin.mBIndex 126 127 // generate addr 128 val s0_saddr = s0_stin.src(0) + SignExt(s0_uop.imm(11,0), VAddrBits) 129 val s0_vaddr = Mux( 130 s0_use_flow_ma, 131 io.misalign_stin.bits.vaddr, 132 Mux( 133 s0_use_flow_rs, 134 s0_saddr, 135 Mux( 136 s0_use_flow_vec, 137 s0_vecstin.vaddr, 138 io.prefetch_req.bits.vaddr 139 ) 140 ) 141 ) 142 val s0_mask = Mux( 143 s0_use_flow_ma, 144 io.misalign_stin.bits.mask, 145 Mux( 146 s0_use_flow_rs, 147 genVWmask128(s0_saddr, s0_uop.fuOpType(2,0)), 148 Mux( 149 s0_use_flow_vec, 150 s0_vecstin.mask, 151 // -1.asSInt.asUInt 152 Fill(VLEN/8, 1.U(1.W)) 153 ) 154 ) 155 ) 156 157 io.tlb.req.valid := s0_valid 158 io.tlb.req.bits.vaddr := s0_vaddr 159 io.tlb.req.bits.cmd := TlbCmd.write 160 io.tlb.req.bits.size := s0_size 161 io.tlb.req.bits.kill := false.B 162 io.tlb.req.bits.memidx.is_ld := false.B 163 io.tlb.req.bits.memidx.is_st := true.B 164 io.tlb.req.bits.memidx.idx := s0_mem_idx 165 io.tlb.req.bits.debug.robIdx := s0_rob_idx 166 io.tlb.req.bits.no_translate := false.B 167 io.tlb.req.bits.debug.pc := s0_pc 168 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 169 io.tlb.req_kill := false.B 170 io.tlb.req.bits.hyperinst := LSUOpType.isHsv(s0_uop.fuOpType) 171 io.tlb.req.bits.hlvx := false.B 172 io.tlb.req.bits.pmp_addr := DontCare 173 174 // Dcache access here: not **real** dcache write 175 // just read meta and tag in dcache, to find out the store will hit or miss 176 177 // NOTE: The store request does not wait for the dcache to be ready. 178 // If the dcache is not ready at this time, the dcache is not queried. 179 // But, store prefetch request will always wait for dcache to be ready to make progress. 180 io.dcache.req.valid := s0_fire 181 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 182 io.dcache.req.bits.vaddr := s0_vaddr 183 io.dcache.req.bits.instrtype := s0_instr_type 184 185 s0_out := DontCare 186 s0_out.vaddr := s0_vaddr 187 // Now data use its own io 188 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.fuOpType(1,0)) 189 s0_out.data := s0_stin.src(1) 190 s0_out.uop := s0_uop 191 s0_out.miss := false.B 192 s0_out.mask := s0_mask 193 s0_out.isFirstIssue := s0_isFirstIssue 194 s0_out.isHWPrefetch := s0_use_flow_prf 195 s0_out.wlineflag := s0_wlineflag 196 s0_out.isvec := s0_use_flow_vec 197 s0_out.is128bit := s0_is128bit 198 s0_out.vecActive := s0_vecActive 199 s0_out.usSecondInv := s0_secondInv 200 s0_out.elemIdx := s0_elemIdx 201 s0_out.alignedType := s0_alignedType 202 s0_out.mbIndex := s0_mBIndex 203 when(s0_valid && s0_isFirstIssue) { 204 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 205 } 206 s0_out.isFrmMisAlignBuf := s0_use_flow_ma 207 208 // exception check 209 val s0_addr_aligned = LookupTree(Mux(s0_use_flow_vec, s0_vecstin.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 210 "b00".U -> true.B, //b 211 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 212 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 213 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 214 )) 215 // if vector store sends 128-bit requests, its address must be 128-aligned 216 XSError(s0_use_flow_vec && s0_out.vaddr(3, 0) =/= 0.U && s0_vecstin.alignedType(2), "unit stride 128 bit element is not aligned!") 217 s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_non_prf_flow, (!s0_addr_aligned || s0_vecstin.uop.exceptionVec(storeAddrMisaligned) && s0_vecActive), false.B) 218 219 io.st_mask_out.valid := s0_use_flow_rs || s0_use_flow_vec 220 io.st_mask_out.bits.mask := s0_out.mask 221 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 222 223 io.stin.ready := s1_ready && s0_use_flow_rs 224 io.vecstin.ready := s1_ready && s0_use_flow_vec 225 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid && !s0_ma_st_valid 226 io.misalign_stin.ready := s1_ready && s0_use_flow_ma 227 228 // Pipeline 229 // -------------------------------------------------------------------------------- 230 // stage 1 231 // -------------------------------------------------------------------------------- 232 // TLB resp (send paddr to dcache) 233 val s1_valid = RegInit(false.B) 234 val s1_in = RegEnable(s0_out, s0_fire) 235 val s1_out = Wire(new LsPipelineBundle) 236 val s1_kill = Wire(Bool()) 237 val s1_can_go = s2_ready 238 val s1_fire = s1_valid && !s1_kill && s1_can_go 239 val s1_vecActive = RegEnable(s0_out.vecActive, true.B, s0_fire) 240 val s1_frm_mabuf = s1_in.isFrmMisAlignBuf 241 242 // mmio cbo decoder 243 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 244 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 245 s1_in.uop.fuOpType === LSUOpType.cbo_inval 246 val s1_paddr = io.tlb.resp.bits.paddr(0) 247 val s1_gpaddr = io.tlb.resp.bits.gpaddr(0) 248 val s1_tlb_miss = io.tlb.resp.bits.miss 249 val s1_mmio = s1_mmio_cbo 250 val s1_pbmt = io.tlb.resp.bits.pbmt(0) 251 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 252 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 253 // val s1_isLastElem = RegEnable(s0_isLastElem, false.B, s0_fire) 254 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || (s1_tlb_miss && !s1_isvec && !s1_frm_mabuf) 255 256 s1_ready := !s1_valid || s1_kill || s2_ready 257 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 258 when (s0_fire) { s1_valid := true.B } 259 .elsewhen (s1_fire) { s1_valid := false.B } 260 .elsewhen (s1_kill) { s1_valid := false.B } 261 262 // st-ld violation dectect request. 263 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_frm_mabuf 264 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 265 io.stld_nuke_query.bits.paddr := s1_paddr 266 io.stld_nuke_query.bits.mask := s1_in.mask 267 io.stld_nuke_query.bits.matchLine := s1_in.isvec && s1_in.is128bit 268 269 // issue 270 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec && !s1_frm_mabuf 271 io.issue.bits := RegEnable(s0_stin, s0_valid) 272 273 274 // Send TLB feedback to store issue queue 275 // Store feedback is generated in store_s1, sent to RS in store_s2 276 val s1_feedback = Wire(Valid(new RSFeedback)) 277 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 278 s1_feedback.bits.hit := !s1_tlb_miss 279 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 280 s1_feedback.bits.robIdx := s1_out.uop.robIdx 281 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 282 s1_feedback.bits.dataInvalidSqIdx := DontCare 283 s1_feedback.bits.sqIdx := s1_out.uop.sqIdx 284 s1_feedback.bits.lqIdx := s1_out.uop.lqIdx 285 286 XSDebug(s1_feedback.valid, 287 "S1 Store: tlbHit: %d robIdx: %d\n", 288 s1_feedback.bits.hit, 289 s1_feedback.bits.robIdx.value 290 ) 291 292 // io.feedback_slow := s1_feedback 293 294 // get paddr from dtlb, check if rollback is needed 295 // writeback store inst to lsq 296 s1_out := s1_in 297 s1_out.paddr := s1_paddr 298 s1_out.gpaddr := s1_gpaddr 299 s1_out.miss := false.B 300 s1_out.mmio := s1_mmio 301 s1_out.tlbMiss := s1_tlb_miss 302 s1_out.atomic := s1_mmio 303 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_vecActive 304 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_vecActive 305 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st && s1_vecActive 306 307 // trigger 308 val storeTrigger = Module(new MemTrigger(MemType.STORE)) 309 storeTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 310 storeTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 311 storeTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 312 storeTrigger.io.fromCsrTrigger.debugMode := io.fromCsrTrigger.debugMode 313 storeTrigger.io.fromLoadStore.vaddr := s1_in.vaddr 314 315 val s1_trigger_action = storeTrigger.io.toLoadStore.triggerAction 316 val s1_trigger_debug_mode = TriggerAction.isDmode(s1_trigger_action) 317 val s1_trigger_breakpoint = TriggerAction.isExp(s1_trigger_action) 318 319 s1_out.uop.flushPipe := false.B 320 s1_out.uop.trigger := s1_trigger_action 321 s1_out.uop.exceptionVec(breakPoint) := s1_trigger_breakpoint 322 323 // scalar store and scalar load nuke check, and also other purposes 324 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch && !s1_frm_mabuf 325 io.lsq.bits := s1_out 326 io.lsq.bits.miss := s1_tlb_miss 327 328 // goto misalignBuffer 329 io.misalign_buf.valid := s1_valid && !s1_in.isHWPrefetch && GatedValidRegNext(io.csrCtrl.hd_misalign_st_enable) && !s1_in.isvec 330 io.misalign_buf.bits := io.lsq.bits 331 332 // kill dcache write intent request when tlb miss or exception 333 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 334 io.dcache.s1_paddr := s1_paddr 335 336 // write below io.out.bits assign sentence to prevent overwriting values 337 val s1_tlb_memidx = io.tlb.resp.bits.memidx 338 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 339 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 340 s1_out.uop.debugInfo.tlbRespTime := GTimer() 341 } 342 343 // Pipeline 344 // -------------------------------------------------------------------------------- 345 // stage 2 346 // -------------------------------------------------------------------------------- 347 // mmio check 348 val s2_valid = RegInit(false.B) 349 val s2_in = RegEnable(s1_out, s1_fire) 350 val s2_out = Wire(new LsPipelineBundle) 351 val s2_kill = Wire(Bool()) 352 val s2_can_go = s3_ready 353 val s2_fire = s2_valid && !s2_kill && s2_can_go 354 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 355 val s2_frm_mabuf = s2_in.isFrmMisAlignBuf 356 val s2_pbmt = RegEnable(s1_pbmt, s1_fire) 357 val s2_trigger_debug_mode = RegEnable(s1_trigger_debug_mode, false.B, s1_fire) 358 val s2_mis_align = GatedValidRegNext(io.csrCtrl.hd_misalign_st_enable) && !s2_in.isvec && 359 s2_in.uop.exceptionVec(storeAddrMisaligned) && !s2_in.uop.exceptionVec(breakPoint) && !s2_trigger_debug_mode 360 361 s2_ready := !s2_valid || s2_kill || s3_ready 362 when (s1_fire) { s2_valid := true.B } 363 .elsewhen (s2_fire) { s2_valid := false.B } 364 .elsewhen (s2_kill) { s2_valid := false.B } 365 366 val s2_pmp = WireInit(io.pmp) 367 368 val s2_exception = RegNext(s1_feedback.bits.hit) && 369 (s2_trigger_debug_mode || ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR) 370 val s2_mmio = (s2_in.mmio || s2_pmp.mmio || Pbmt.isUncache(s2_pbmt)) && RegNext(s1_feedback.bits.hit) 371 s2_kill := ((s2_mmio && !s2_exception) && !s2_in.isvec) || s2_in.uop.robIdx.needFlush(io.redirect) 372 373 s2_out := s2_in 374 s2_out.af := s2_pmp.st && !s2_in.isvec 375 s2_out.mmio := s2_mmio && !s2_exception 376 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 377 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || 378 s2_pmp.st || 379 (s2_in.isvec && s2_pmp.mmio && RegNext(s1_feedback.bits.hit)) 380 ) && s2_vecActive 381 382 // kill dcache write intent request when mmio or exception 383 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 384 io.dcache.s2_pc := s2_out.uop.pc 385 // TODO: dcache resp 386 io.dcache.resp.ready := true.B 387 388 // feedback tlb miss to RS in store_s2 389 val feedback_slow_valid = WireInit(false.B) 390 feedback_slow_valid := s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect) && !s1_out.isvec && !s1_frm_mabuf 391 io.feedback_slow.valid := GatedValidRegNext(feedback_slow_valid) 392 io.feedback_slow.bits := RegEnable(s1_feedback.bits, feedback_slow_valid) 393 394 val s2_vecFeedback = RegNext(!s1_out.uop.robIdx.needFlush(io.redirect) && s1_feedback.bits.hit) && s2_in.isvec 395 396 val s2_misalign_stout = WireInit(0.U.asTypeOf(io.misalign_stout)) 397 s2_misalign_stout.valid := s2_valid && s2_can_go && s2_frm_mabuf 398 s2_misalign_stout.bits.mmio := s2_out.mmio 399 s2_misalign_stout.bits.vaddr := s2_out.vaddr 400 s2_misalign_stout.bits.paddr := s2_out.paddr 401 s2_misalign_stout.bits.gpaddr := s2_out.gpaddr 402 s2_misalign_stout.bits.need_rep := RegEnable(s1_tlb_miss, s1_fire) 403 s2_misalign_stout.bits.uop.exceptionVec := s2_out.uop.exceptionVec 404 io.misalign_stout := s2_misalign_stout 405 406 // mmio and exception 407 io.lsq_replenish := s2_out 408 io.lsq_replenish.af := s2_out.af && s2_valid && !s2_kill 409 410 // prefetch related 411 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 412 413 // RegNext prefetch train for better timing 414 // ** Now, prefetch train is valid at store s3 ** 415 val s2_prefetch_train_valid = WireInit(false.B) 416 s2_prefetch_train_valid := s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch 417 if(EnableStorePrefetchSMS) { 418 io.s1_prefetch_spec := s1_fire 419 io.s2_prefetch_spec := s2_prefetch_train_valid 420 io.prefetch_train.valid := RegNext(s2_prefetch_train_valid) 421 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = s2_prefetch_train_valid) 422 }else { 423 io.s1_prefetch_spec := false.B 424 io.s2_prefetch_spec := false.B 425 io.prefetch_train.valid := false.B 426 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true, enable = false.B) 427 } 428 // override miss bit 429 io.prefetch_train.bits.miss := RegEnable(io.dcache.resp.bits.miss, s2_prefetch_train_valid) 430 // TODO: add prefetch and access bit 431 io.prefetch_train.bits.meta_prefetch := false.B 432 io.prefetch_train.bits.meta_access := false.B 433 434 // Pipeline 435 // -------------------------------------------------------------------------------- 436 // stage 3 437 // -------------------------------------------------------------------------------- 438 // store write back 439 val s3_valid = RegInit(false.B) 440 val s3_in = RegEnable(s2_out, s2_fire) 441 val s3_out = Wire(new MemExuOutput(isVector = true)) 442 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 443 val s3_can_go = s3_ready 444 val s3_fire = s3_valid && !s3_kill && s3_can_go 445 val s3_vecFeedback = RegEnable(s2_vecFeedback, s2_fire) 446 447 // store misalign will not writeback to rob now 448 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch && !s2_mis_align && !s2_frm_mabuf } 449 .elsewhen (s3_fire) { s3_valid := false.B } 450 .elsewhen (s3_kill) { s3_valid := false.B } 451 452 // wb: writeback 453 val SelectGroupSize = RollbackGroupSize 454 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 455 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 456 457 s3_out := DontCare 458 s3_out.uop := s3_in.uop 459 s3_out.data := DontCare 460 s3_out.debug.isMMIO := s3_in.mmio 461 s3_out.debug.paddr := s3_in.paddr 462 s3_out.debug.vaddr := s3_in.vaddr 463 s3_out.debug.isPerfCnt := false.B 464 465 // Pipeline 466 // -------------------------------------------------------------------------------- 467 // stage x 468 // -------------------------------------------------------------------------------- 469 // delay TotalSelectCycles - 2 cycle(s) 470 val TotalDelayCycles = TotalSelectCycles - 2 471 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 472 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 473 val sx_in = Wire(Vec(TotalDelayCycles + 1, new VecMemExuOutput(isVector = true))) 474 475 // backward ready signal 476 s3_ready := sx_ready.head 477 for (i <- 0 until TotalDelayCycles + 1) { 478 if (i == 0) { 479 sx_valid(i) := s3_valid 480 sx_in(i).output := s3_out 481 sx_in(i).vecFeedback := s3_vecFeedback 482 sx_in(i).mmio := s3_in.mmio 483 sx_in(i).usSecondInv := s3_in.usSecondInv 484 sx_in(i).elemIdx := s3_in.elemIdx 485 sx_in(i).alignedType := s3_in.alignedType 486 sx_in(i).mbIndex := s3_in.mbIndex 487 sx_in(i).mask := s3_in.mask 488 sx_in(i).vaddr := s3_in.vaddr 489 sx_in(i).gpaddr := s3_in.gpaddr 490 sx_ready(i) := !s3_valid(i) || sx_in(i).output.uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 491 } else { 492 val cur_kill = sx_in(i).output.uop.robIdx.needFlush(io.redirect) 493 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 494 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 495 val prev_fire = sx_valid(i-1) && !sx_in(i-1).output.uop.robIdx.needFlush(io.redirect) && sx_ready(i) 496 497 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 498 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 499 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 500 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 501 } 502 } 503 val sx_last_valid = sx_valid.takeRight(1).head 504 val sx_last_ready = sx_ready.takeRight(1).head 505 val sx_last_in = sx_in.takeRight(1).head 506 sx_last_ready := !sx_last_valid || sx_last_in.output.uop.robIdx.needFlush(io.redirect) || io.stout.ready 507 508 io.stout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isStore(sx_last_in.output.uop.fuType) 509 io.stout.bits := sx_last_in.output 510 io.stout.bits.uop.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, StaCfg) 511 512 io.vecstout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isVStore(sx_last_in.output.uop.fuType) 513 // TODO: implement it! 514 io.vecstout.bits.mBIndex := sx_last_in.mbIndex 515 io.vecstout.bits.hit := sx_last_in.vecFeedback 516 io.vecstout.bits.isvec := true.B 517 io.vecstout.bits.sourceType := RSFeedbackType.tlbMiss 518 io.vecstout.bits.flushState := DontCare 519 io.vecstout.bits.mmio := sx_last_in.mmio 520 io.vecstout.bits.exceptionVec := ExceptionNO.selectByFu(sx_last_in.output.uop.exceptionVec, VstuCfg) 521 io.vecstout.bits.usSecondInv := sx_last_in.usSecondInv 522 io.vecstout.bits.vecFeedback := sx_last_in.vecFeedback 523 io.vecstout.bits.elemIdx := sx_last_in.elemIdx 524 io.vecstout.bits.alignedType := sx_last_in.alignedType 525 io.vecstout.bits.mask := sx_last_in.mask 526 io.vecstout.bits.vaddr := sx_last_in.vaddr 527 io.vecstout.bits.gpaddr := sx_last_in.gpaddr 528 // io.vecstout.bits.reg_offset.map(_ := DontCare) 529 // io.vecstout.bits.elemIdx.map(_ := sx_last_in.elemIdx) 530 // io.vecstout.bits.elemIdxInsideVd.map(_ := DontCare) 531 // io.vecstout.bits.vecdata.map(_ := DontCare) 532 // io.vecstout.bits.mask.map(_ := DontCare) 533 // io.vecstout.bits.alignedType.map(_ := sx_last_in.alignedType) 534 535 io.debug_ls := DontCare 536 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 537 io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 538 539 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 540 XSDebug(cond, 541 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 542 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 543 p"op ${Binary(pipeline.uop.fuOpType)} " + 544 p"data ${Hexadecimal(pipeline.data)} " + 545 p"mask ${Hexadecimal(pipeline.mask)}\n" 546 ) 547 } 548 549 printPipeLine(s0_out, s0_valid, "S0") 550 printPipeLine(s1_out, s1_valid, "S1") 551 552 // perf cnt 553 XSPerfAccumulate("s0_in_valid", s0_valid) 554 XSPerfAccumulate("s0_in_fire", s0_fire) 555 XSPerfAccumulate("s0_vecin_fire", s0_fire && s0_use_flow_vec) 556 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 557 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 558 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 559 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 560 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 561 562 XSPerfAccumulate("s1_in_valid", s1_valid) 563 XSPerfAccumulate("s1_in_fire", s1_fire) 564 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 565 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 566 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 567 // end 568} 569