1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.backend.rob.DebugLsInfoBundle 28import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 29 30class StoreUnit(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val redirect = Flipped(ValidIO(new Redirect)) 33 val stin = Flipped(Decoupled(new ExuInput)) 34 val issue = Valid(new ExuInput) 35 val tlb = new TlbRequestIO() 36 val pmp = Flipped(new PMPRespBundle()) 37 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 38 val isFirstIssue = Input(Bool()) 39 val lsq = ValidIO(new LsPipelineBundle) 40 val lsq_replenish = Output(new LsPipelineBundle()) 41 val feedback_slow = ValidIO(new RSFeedback) 42 val stld_nuke_query = Valid(new StoreNukeQueryIO) 43 val stout = DecoupledIO(new ExuOutput) // writeback store 44 // store mask, send to sq in store_s0 45 val st_mask_out = Valid(new StoreMaskBundle) 46 val debug_ls = Output(new DebugLsInfoBundle) 47 }) 48 49 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 50 51 // Pipeline 52 // -------------------------------------------------------------------------------- 53 // stage 0 54 // -------------------------------------------------------------------------------- 55 // generate addr, use addr to query DCache and DTLB 56 val s0_valid = io.stin.valid 57 val s0_in = io.stin.bits 58 val s0_isFirstIssue = io.isFirstIssue 59 val s0_rsIdx = io.rsIdx 60 val s0_out = Wire(new LsPipelineBundle) 61 val s0_kill = s0_in.uop.robIdx.needFlush(io.redirect) 62 val s0_can_go = s1_ready 63 val s0_fire = s0_valid && !s0_kill && s0_can_go 64 65 // generate addr 66 // val saddr = s0_in.bits.src(0) + SignExt(s0_in.bits.uop.ctrl.imm(11,0), VAddrBits) 67 val imm12 = WireInit(s0_in.uop.ctrl.imm(11,0)) 68 val saddr_lo = s0_in.src(0)(11,0) + Cat(0.U(1.W), imm12) 69 val saddr_hi = Mux(saddr_lo(12), 70 Mux(imm12(11), s0_in.src(0)(VAddrBits-1, 12), s0_in.src(0)(VAddrBits-1, 12)+1.U), 71 Mux(imm12(11), s0_in.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), s0_in.src(0)(VAddrBits-1, 12)), 72 ) 73 val s0_saddr = Cat(saddr_hi, saddr_lo(11,0)) 74 75 io.tlb.req.valid := s0_valid 76 io.tlb.req.bits.vaddr := s0_saddr 77 io.tlb.req.bits.cmd := TlbCmd.write 78 io.tlb.req.bits.size := LSUOpType.size(s0_in.uop.ctrl.fuOpType) 79 io.tlb.req.bits.kill := DontCare 80 io.tlb.req.bits.memidx.is_ld := false.B 81 io.tlb.req.bits.memidx.is_st := true.B 82 io.tlb.req.bits.memidx.idx := s0_in.uop.sqIdx.value 83 io.tlb.req.bits.debug.robIdx := s0_in.uop.robIdx 84 io.tlb.req.bits.no_translate := false.B 85 io.tlb.req.bits.debug.pc := s0_in.uop.cf.pc 86 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 87 io.tlb.req_kill := false.B 88 89 s0_out := DontCare 90 s0_out.vaddr := s0_saddr 91 // Now data use its own io 92 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.ctrl.fuOpType(1,0)) 93 s0_out.data := s0_in.src(1) // FIXME: remove data from pipeline 94 s0_out.uop := s0_in.uop 95 s0_out.miss := DontCare 96 s0_out.rsIdx := s0_rsIdx 97 s0_out.mask := genWmask(s0_saddr, s0_in.uop.ctrl.fuOpType(1,0)) 98 s0_out.isFirstIssue := s0_isFirstIssue 99 s0_out.wlineflag := s0_in.uop.ctrl.fuOpType === LSUOpType.cbo_zero 100 when(s0_valid && s0_isFirstIssue) { 101 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 102 } 103 104 // exception check 105 val s0_addr_aligned = LookupTree(s0_in.uop.ctrl.fuOpType(1,0), List( 106 "b00".U -> true.B, //b 107 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 108 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 109 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 110 )) 111 s0_out.uop.cf.exceptionVec(storeAddrMisaligned) := !s0_addr_aligned 112 113 io.st_mask_out.valid := s0_valid 114 io.st_mask_out.bits.mask := s0_out.mask 115 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 116 117 io.stin.ready := s1_ready 118 119 // Pipeline 120 // -------------------------------------------------------------------------------- 121 // stage 1 122 // -------------------------------------------------------------------------------- 123 // TLB resp (send paddr to dcache) 124 val s1_valid = RegInit(false.B) 125 val s1_in = RegEnable(s0_out, s0_fire) 126 val s1_out = Wire(new LsPipelineBundle) 127 val s1_kill = Wire(Bool()) 128 val s1_can_go = s2_ready 129 val s1_fire = s1_valid && !s1_kill && s1_can_go 130 131 // mmio cbo decoder 132 val s1_mmio_cbo = s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_clean || 133 s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_flush || 134 s1_in.uop.ctrl.fuOpType === LSUOpType.cbo_inval 135 val s1_paddr = io.tlb.resp.bits.paddr(0) 136 val s1_tlb_miss = io.tlb.resp.bits.miss 137 val s1_mmio = s1_mmio_cbo 138 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.cf.exceptionVec, staCfg).asUInt.orR 139 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || s1_tlb_miss 140 141 s1_ready := !s1_valid || s1_kill || s2_ready 142 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 143 when (s0_fire) { s1_valid := true.B } 144 .elsewhen (s1_fire) { s1_valid := false.B } 145 .elsewhen (s1_kill) { s1_valid := false.B } 146 147 // st-ld violation dectect request. 148 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss 149 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 150 io.stld_nuke_query.bits.paddr := s1_paddr 151 io.stld_nuke_query.bits.mask := s1_in.mask 152 153 // Send TLB feedback to store issue queue 154 // Store feedback is generated in store_s1, sent to RS in store_s2 155 io.feedback_slow.valid := s1_fire 156 io.feedback_slow.bits.hit := !s1_tlb_miss 157 io.feedback_slow.bits.flushState := io.tlb.resp.bits.ptwBack 158 io.feedback_slow.bits.rsIdx := s1_in.rsIdx 159 io.feedback_slow.bits.sourceType := RSFeedbackType.tlbMiss 160 XSDebug(io.feedback_slow.valid, 161 "S1 Store: tlbHit: %d robIdx: %d\n", 162 io.feedback_slow.bits.hit, 163 io.feedback_slow.bits.rsIdx 164 ) 165 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 166 167 // issue 168 io.issue.valid := s1_valid && !s1_tlb_miss 169 io.issue.bits := RegEnable(s0_in, s0_valid) 170 171 // get paddr from dtlb, check if rollback is needed 172 // writeback store inst to lsq 173 s1_out := s1_in 174 s1_out.paddr := s1_paddr 175 s1_out.miss := false.B 176 s1_out.mmio := s1_mmio 177 s1_out.atomic := s1_mmio 178 s1_out.uop.cf.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 179 s1_out.uop.cf.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 180 181 io.lsq.valid := s1_valid 182 io.lsq.bits := s1_out 183 io.lsq.bits.miss := s1_tlb_miss 184 185 // write below io.out.bits assign sentence to prevent overwriting values 186 val s1_tlb_memidx = io.tlb.resp.bits.memidx 187 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 188 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 189 s1_out.uop.debugInfo.tlbRespTime := GTimer() 190 } 191 192 // Pipeline 193 // -------------------------------------------------------------------------------- 194 // stage 2 195 // -------------------------------------------------------------------------------- 196 // mmio check 197 val s2_valid = RegInit(false.B) 198 val s2_in = RegEnable(s1_out, s1_fire) 199 val s2_out = Wire(new LsPipelineBundle) 200 val s2_kill = Wire(Bool()) 201 val s2_can_go = s3_ready 202 val s2_fire = s2_valid && !s2_kill && s2_can_go 203 204 s2_ready := !s2_valid || s2_kill || s3_ready 205 when (s1_fire) { s2_valid := true.B } 206 .elsewhen (s2_fire) { s2_valid := false.B } 207 .elsewhen (s2_kill) { s2_valid := false.B } 208 209 val s2_pmp = WireInit(io.pmp) 210 val s2_static_pm = RegNext(io.tlb.resp.bits.static_pm) 211 when (s2_static_pm.valid) { 212 s2_pmp.ld := false.B 213 s2_pmp.st := false.B 214 s2_pmp.instr := false.B 215 s2_pmp.mmio := s2_static_pm.bits 216 } 217 218 val s2_exception = ExceptionNO.selectByFu(s2_out.uop.cf.exceptionVec, staCfg).asUInt.orR 219 val s2_mmio = s2_in.mmio || s2_pmp.mmio 220 s2_kill := (s2_mmio && !s2_exception) || s2_in.uop.robIdx.needFlush(io.redirect) 221 222 s2_out := s2_in 223 s2_out.mmio := s2_mmio && !s2_exception 224 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 225 s2_out.uop.cf.exceptionVec(storeAccessFault) := s2_in.uop.cf.exceptionVec(storeAccessFault) || s2_pmp.st 226 227 // feedback tlb miss to RS in store_s2 228 val s1_feedback = Wire(Valid(new RSFeedback)) 229 s1_feedback.valid := s1_valid 230 s1_feedback.bits.hit := !s1_tlb_miss 231 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 232 s1_feedback.bits.rsIdx := s1_out.rsIdx 233 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 234 s1_feedback.bits.dataInvalidSqIdx := DontCare 235 XSDebug(s1_feedback.valid, 236 "S1 Store: tlbHit: %d robIdx: %d\n", 237 s1_feedback.bits.hit, 238 s1_feedback.bits.rsIdx 239 ) 240 io.feedback_slow.valid := RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) 241 io.feedback_slow.bits := RegNext(s1_feedback.bits) 242 243 // mmio and exception 244 io.lsq_replenish := s2_out 245 246 // Pipeline 247 // -------------------------------------------------------------------------------- 248 // stage 3 249 // -------------------------------------------------------------------------------- 250 // store write back 251 val s3_valid = RegInit(false.B) 252 val s3_in = RegEnable(s2_out, s2_fire) 253 val s3_out = Wire(new ExuOutput) 254 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 255 val s3_can_go = s3_ready 256 val s3_fire = s3_valid && !s3_kill && s3_can_go 257 258 when (s2_fire) { s3_valid := !s2_mmio || s2_exception } 259 .elsewhen (s3_fire) { s3_valid := false.B } 260 .elsewhen (s3_kill) { s3_valid := false.B } 261 262 // wb: writeback 263 val SelectGroupSize = RollbackGroupSize 264 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 265 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 266 267 s3_out := DontCare 268 s3_out.uop := s3_in.uop 269 s3_out.data := DontCare 270 s3_out.redirectValid := false.B 271 s3_out.redirect := DontCare 272 s3_out.debug.isMMIO := s3_in.mmio 273 s3_out.debug.paddr := s3_in.paddr 274 s3_out.debug.vaddr := s3_in.vaddr 275 s3_out.debug.isPerfCnt := false.B 276 s3_out.fflags := DontCare 277 278 // Pipeline 279 // -------------------------------------------------------------------------------- 280 // stage x 281 // -------------------------------------------------------------------------------- 282 // delay TotalSelectCycles - 2 cycle(s) 283 val TotalDelayCycles = TotalSelectCycles - 2 284 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 285 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 286 val sx_in = Wire(Vec(TotalDelayCycles + 1, new ExuOutput)) 287 288 // backward ready signal 289 s3_ready := sx_ready.head 290 for (i <- 0 until TotalDelayCycles + 1) { 291 if (i == 0) { 292 sx_valid(i) := s3_valid 293 sx_in(i) := s3_out 294 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 295 } else { 296 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 297 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 298 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 299 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 300 301 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 302 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 303 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), sx_valid_can_go) 304 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 305 } 306 } 307 val sx_last_valid = sx_valid.takeRight(1).head 308 val sx_last_ready = sx_ready.takeRight(1).head 309 val sx_last_in = sx_in.takeRight(1).head 310 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 311 312 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) 313 io.stout.bits := sx_last_in 314 315 io.debug_ls := DontCare 316 io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue 317 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 318 319 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 320 XSDebug(cond, 321 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 322 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 323 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 324 p"data ${Hexadecimal(pipeline.data)} " + 325 p"mask ${Hexadecimal(pipeline.mask)}\n" 326 ) 327 } 328 329 printPipeLine(s0_out, s0_valid, "S0") 330 printPipeLine(s1_out, s1_valid, "S1") 331 332 // perf cnt 333 XSPerfAccumulate("in_valid", s0_valid) 334 XSPerfAccumulate("in_fire", s0_fire) 335 XSPerfAccumulate("in_fire_first_issue", s0_fire && s0_isFirstIssue) 336 XSPerfAccumulate("addr_spec_success", s0_fire && s0_saddr(VAddrBits-1, 12) === s0_in.src(0)(VAddrBits-1, 12)) 337 XSPerfAccumulate("addr_spec_failed", s0_fire && s0_saddr(VAddrBits-1, 12) =/= s0_in.src(0)(VAddrBits-1, 12)) 338 XSPerfAccumulate("addr_spec_success_once", s0_fire && s0_saddr(VAddrBits-1, 12) === s0_in.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 339 XSPerfAccumulate("addr_spec_failed_once", s0_fire && s0_saddr(VAddrBits-1, 12) =/= s0_in.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 340 341 XSPerfAccumulate("in_valid", s1_valid) 342 XSPerfAccumulate("in_fire", s1_fire) 343 XSPerfAccumulate("in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 344 XSPerfAccumulate("tlb_miss", s1_fire && s1_tlb_miss) 345 XSPerfAccumulate("tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 346 // end 347}