1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 28import xiangshan.v2backend.Bundles.{MemExuInput, MemExuOutput} 29import xiangshan.v2backend.{StaCfg} 30 31// Store Pipeline Stage 0 32// Generate addr, use addr to query DCache and DTLB 33class StoreUnit_S0(implicit p: Parameters) extends XSModule { 34 val io = IO(new Bundle() { 35 val in = Flipped(Decoupled(new MemExuInput)) 36 val out = Decoupled(new LsPipelineBundle) 37 val dtlbReq = DecoupledIO(new TlbReq) 38 }) 39 40 // send req to dtlb 41 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 42 val imm12 = WireInit(io.in.bits.uop.imm(11,0)) 43 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 44 val saddr_hi = Mux(saddr_lo(12), 45 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 46 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 47 ) 48 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 49 50 io.dtlbReq.bits.vaddr := saddr 51 io.dtlbReq.valid := io.in.valid 52 io.dtlbReq.bits.cmd := TlbCmd.write 53 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.fuOpType) 54 io.dtlbReq.bits.kill := DontCare 55 io.dtlbReq.bits.debug.robIdx := io.in.bits.uop.robIdx 56 io.dtlbReq.bits.debug.pc := io.in.bits.uop.pc 57 io.dtlbReq.bits.debug.isFirstIssue := io.in.bits.isFirstIssue 58 59 io.out.bits := DontCare 60 io.out.bits.vaddr := saddr 61 62 // Now data use its own io 63 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 64 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 65 io.out.bits.uop := io.in.bits.uop 66 io.out.bits.miss := DontCare 67 io.out.bits.rsIdx := io.in.bits.iqIdx // guarded by io.in.valid 68 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.fuOpType(1,0)) 69 io.out.bits.isFirstIssue := io.in.bits.isFirstIssue // guarded by io.in.valid 70 io.out.bits.wlineflag := io.in.bits.uop.fuOpType === LSUOpType.cbo_zero 71 io.out.valid := io.in.valid 72 io.in.ready := io.out.ready 73 74 // exception check 75 val addrAligned = LookupTree(io.in.bits.uop.fuOpType(1,0), List( 76 "b00".U -> true.B, //b 77 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 78 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 79 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 80 )) 81 82 io.out.bits.uop.exceptionVec(storeAddrMisaligned) := !addrAligned 83 84 XSPerfAccumulate("in_valid", io.in.valid) 85 XSPerfAccumulate("in_fire", io.in.fire) 86 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 87 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 88 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 89 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.in.bits.isFirstIssue) 90 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.in.bits.isFirstIssue) 91} 92 93// Store Pipeline Stage 1 94// TLB resp (send paddr to dcache) 95class StoreUnit_S1(implicit p: Parameters) extends XSModule { 96 val io = IO(new Bundle() { 97 val in = Flipped(Decoupled(new LsPipelineBundle)) 98 val out = Decoupled(new LsPipelineBundle) 99 val lsq = ValidIO(new LsPipelineBundle()) 100 val dtlbResp = Flipped(DecoupledIO(new TlbResp())) 101 val rsFeedback = ValidIO(new RSFeedback) 102 val reExecuteQuery = Valid(new LoadReExecuteQueryIO) 103 }) 104 105 // mmio cbo decoder 106 val is_mmio_cbo = io.in.bits.uop.fuOpType === LSUOpType.cbo_clean || 107 io.in.bits.uop.fuOpType === LSUOpType.cbo_flush || 108 io.in.bits.uop.fuOpType === LSUOpType.cbo_inval 109 110 val s1_paddr = io.dtlbResp.bits.paddr(0) 111 val s1_tlb_miss = io.dtlbResp.bits.miss 112 val s1_mmio = is_mmio_cbo 113 val s1_exception = ExceptionNO.selectByFu(io.out.bits.uop.exceptionVec, StaCfg).asUInt.orR 114 115 io.in.ready := true.B 116 117 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 118 119 // st-ld violation dectect request. 120 io.reExecuteQuery.valid := io.in.valid && !s1_tlb_miss 121 io.reExecuteQuery.bits.robIdx := io.in.bits.uop.robIdx 122 io.reExecuteQuery.bits.paddr := s1_paddr 123 io.reExecuteQuery.bits.mask := io.in.bits.mask 124 125 // Send TLB feedback to store issue queue 126 // Store feedback is generated in store_s1, sent to RS in store_s2 127 io.rsFeedback.valid := io.in.valid 128 io.rsFeedback.bits.hit := !s1_tlb_miss 129 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 130 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 131 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 132 XSDebug(io.rsFeedback.valid, 133 "S1 Store: tlbHit: %d robIdx: %d\n", 134 io.rsFeedback.bits.hit, 135 io.rsFeedback.bits.rsIdx 136 ) 137 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 138 139 // get paddr from dtlb, check if rollback is needed 140 // writeback store inst to lsq 141 io.out.valid := io.in.valid && !s1_tlb_miss 142 io.out.bits := io.in.bits 143 io.out.bits.paddr := s1_paddr 144 io.out.bits.miss := false.B 145 io.out.bits.mmio := s1_mmio 146 io.out.bits.atomic := s1_mmio 147 io.out.bits.uop.exceptionVec(storePageFault) := io.dtlbResp.bits.excp(0).pf.st 148 io.out.bits.uop.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp(0).af.st 149 150 io.lsq.valid := io.in.valid 151 io.lsq.bits := io.out.bits 152 io.lsq.bits.miss := s1_tlb_miss 153 154 // mmio inst with exception will be writebacked immediately 155 // io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 156 157 XSPerfAccumulate("in_valid", io.in.valid) 158 XSPerfAccumulate("in_fire", io.in.fire) 159 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 160 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 161 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 162} 163 164class StoreUnit_S2(implicit p: Parameters) extends XSModule { 165 val io = IO(new Bundle() { 166 val in = Flipped(Decoupled(new LsPipelineBundle)) 167 val pmpResp = Flipped(new PMPRespBundle) 168 val static_pm = Input(Valid(Bool())) 169 val out = Decoupled(new LsPipelineBundle) 170 }) 171 val pmp = WireInit(io.pmpResp) 172 when (io.static_pm.valid) { 173 pmp.ld := false.B 174 pmp.st := false.B 175 pmp.instr := false.B 176 pmp.mmio := io.static_pm.bits 177 } 178 179 val s2_exception = ExceptionNO.selectByFu(io.out.bits.uop.exceptionVec, StaCfg).asUInt.orR 180 val is_mmio = io.in.bits.mmio || pmp.mmio 181 182 io.in.ready := true.B 183 io.out.bits := io.in.bits 184 io.out.bits.mmio := is_mmio && !s2_exception 185 io.out.bits.atomic := io.in.bits.atomic || pmp.atomic 186 io.out.bits.uop.exceptionVec(storeAccessFault) := io.in.bits.uop.exceptionVec(storeAccessFault) || pmp.st 187 io.out.valid := io.in.valid && (!is_mmio || s2_exception) 188} 189 190class StoreUnit_S3(implicit p: Parameters) extends XSModule { 191 val io = IO(new Bundle() { 192 val in = Flipped(Decoupled(new LsPipelineBundle)) 193 val stout = DecoupledIO(new MemExuOutput) // writeback store 194 }) 195 196 io.in.ready := true.B 197 198 io.stout.valid := io.in.valid 199 io.stout.bits.uop := io.in.bits.uop 200 io.stout.bits.data := DontCare 201 io.stout.bits.debug.isMMIO := io.in.bits.mmio 202 io.stout.bits.debug.paddr := io.in.bits.paddr 203 io.stout.bits.debug.vaddr := io.in.bits.vaddr 204 io.stout.bits.debug.isPerfCnt := false.B 205} 206 207class StoreUnit(implicit p: Parameters) extends XSModule { 208 val io = IO(new Bundle() { 209 val stin = Flipped(Decoupled(new MemExuInput)) 210 val redirect = Flipped(ValidIO(new Redirect)) 211 val feedbackSlow = ValidIO(new RSFeedback) 212 val tlb = new TlbRequestIO() 213 val pmp = Flipped(new PMPRespBundle()) 214 val lsq = ValidIO(new LsPipelineBundle) 215 val lsq_replenish = Output(new LsPipelineBundle()) 216 val stout = DecoupledIO(new MemExuOutput) // writeback store 217 // store mask, send to sq in store_s0 218 val storeMaskOut = Valid(new StoreMaskBundle) 219 val reExecuteQuery = Valid(new LoadReExecuteQueryIO) 220 val issue = Valid(new MemExuInput) 221 }) 222 223 val store_s0 = Module(new StoreUnit_S0) 224 val store_s1 = Module(new StoreUnit_S1) 225 val store_s2 = Module(new StoreUnit_S2) 226 val store_s3 = Module(new StoreUnit_S3) 227 228 store_s0.io.in <> io.stin 229 store_s0.io.dtlbReq <> io.tlb.req 230 io.tlb.req_kill := false.B 231 232 io.storeMaskOut.valid := store_s0.io.in.valid 233 io.storeMaskOut.bits.mask := store_s0.io.out.bits.mask 234 io.storeMaskOut.bits.sqIdx := store_s0.io.out.bits.uop.sqIdx 235 236 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 237 io.issue.valid := store_s1.io.in.valid && !store_s1.io.dtlbResp.bits.miss 238 io.issue.bits := RegEnable(store_s0.io.in.bits, store_s0.io.in.valid) 239 240 store_s1.io.dtlbResp <> io.tlb.resp 241 io.lsq <> store_s1.io.lsq 242 io.reExecuteQuery := store_s1.io.reExecuteQuery 243 244 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 245 246 // feedback tlb miss to RS in store_s2 247 io.feedbackSlow.bits := RegNext(store_s1.io.rsFeedback.bits) 248 io.feedbackSlow.valid := RegNext(store_s1.io.rsFeedback.valid && !store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 249 250 store_s2.io.pmpResp <> io.pmp 251 store_s2.io.static_pm := RegNext(io.tlb.resp.bits.static_pm) 252 io.lsq_replenish := store_s2.io.out.bits // mmio and exception 253 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 254 255 store_s3.io.stout <> io.stout 256 257 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 258 XSDebug(cond, 259 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 260 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 261 p"op ${Binary(pipeline.uop.fuOpType)} " + 262 p"data ${Hexadecimal(pipeline.data)} " + 263 p"mask ${Hexadecimal(pipeline.mask)}\n" 264 ) 265 } 266 267 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 268 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 269} 270