1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10import xiangshan.backend.fu.fpu.boxF32ToF64 11 12class LoadToLsroqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val forward = new LoadForwardQueryIO 16} 17 18// Load Pipeline Stage 0 19// Generate addr, use addr to query DCache and DTLB 20class LoadUnit_S0 extends XSModule { 21 val io = IO(new Bundle() { 22 val in = Flipped(Decoupled(new ExuInput)) 23 val out = Decoupled(new LsPipelineBundle) 24 val redirect = Flipped(ValidIO(new Redirect)) 25 val dtlbReq = DecoupledIO(new TlbReq) 26 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 27 val tlbFeedback = ValidIO(new TlbFeedback) 28 val dcacheReq = DecoupledIO(new DCacheLoadReq) 29 }) 30 31 val s0_uop = io.in.bits.uop 32 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 33 val s0_paddr = io.dtlbResp.bits.paddr 34 val s0_tlb_miss = io.dtlbResp.bits.miss 35 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 36 37 // query DTLB 38 io.dtlbReq.valid := io.out.valid 39 io.dtlbReq.bits.vaddr := s0_vaddr 40 io.dtlbReq.bits.cmd := TlbCmd.read 41 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 42 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 43 io.dtlbReq.bits.debug.lsroqIdx := s0_uop.lsroqIdx 44 io.dtlbResp.ready := io.out.ready 45 // FIXME: tlb change to DecoupledIO, need to fix tlb's usage 46 47 // feedback tlb result to RS 48 // Note: can be moved to s1 49 io.tlbFeedback.valid := io.out.valid 50 io.tlbFeedback.bits.hit := !s0_tlb_miss 51 io.tlbFeedback.bits.roqIdx := s0_uop.roqIdx 52 53 // query DCache 54 io.dcacheReq.valid := io.in.valid && !s0_uop.roqIdx.needFlush(io.redirect) 55 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 56 io.dcacheReq.bits.addr := s0_vaddr 57 io.dcacheReq.bits.mask := s0_mask 58 io.dcacheReq.bits.data := DontCare 59 60 // TODO: update cache meta 61 io.dcacheReq.bits.meta.id := DontCare 62 io.dcacheReq.bits.meta.vaddr := s0_vaddr 63 io.dcacheReq.bits.meta.paddr := DontCare 64 io.dcacheReq.bits.meta.uop := s0_uop 65 io.dcacheReq.bits.meta.mmio := false.B 66 io.dcacheReq.bits.meta.tlb_miss := false.B 67 io.dcacheReq.bits.meta.mask := s0_mask 68 io.dcacheReq.bits.meta.replay := false.B 69 70 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 71 "b00".U -> true.B, //b 72 "b01".U -> (s0_vaddr(0) === 0.U), //h 73 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 74 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 75 )) 76 77 io.out.valid := io.dcacheReq.fire() // dcache may not accept load request 78 io.out.bits := DontCare 79 io.out.bits.vaddr := s0_vaddr 80 io.out.bits.paddr := s0_paddr 81 io.out.bits.tlbMiss := io.dtlbResp.bits.miss 82 io.out.bits.mask := s0_mask 83 io.out.bits.uop := s0_uop 84 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 85 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 86 87 io.in.ready := io.out.fire() 88 89 XSDebug(io.dcacheReq.fire(), "[DCACHE LOAD REQ] pc %x vaddr %x paddr will be %x\n", 90 s0_uop.cf.pc, s0_vaddr, s0_paddr 91 ) 92} 93 94 95// Load Pipeline Stage 1 96// TLB resp (send paddr to dcache) 97class LoadUnit_S1 extends XSModule { 98 val io = IO(new Bundle() { 99 val in = Flipped(Decoupled(new LsPipelineBundle)) 100 val out = Decoupled(new LsPipelineBundle) 101 val redirect = Flipped(ValidIO(new Redirect)) 102 val s1_paddr = Output(UInt(PAddrBits.W)) 103 val sbuffer = new LoadForwardQueryIO 104 val lsroq = new LoadForwardQueryIO 105 }) 106 107 val s1_uop = io.in.bits.uop 108 val s1_paddr = io.in.bits.paddr 109 val s1_tlb_miss = io.in.bits.tlbMiss 110 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) 111 val s1_mask = io.in.bits.mask 112 113 io.out.bits := io.in.bits // forwardXX field will be updated in s1 114 io.s1_paddr := s1_paddr 115 116 // load forward query datapath 117 io.sbuffer.valid := io.in.valid 118 io.sbuffer.paddr := s1_paddr 119 io.sbuffer.uop := s1_uop 120 io.sbuffer.sqIdx := s1_uop.sqIdx 121 io.sbuffer.lsroqIdx := s1_uop.lsroqIdx 122 io.sbuffer.mask := s1_mask 123 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 124 125 io.lsroq.valid := io.in.valid 126 io.lsroq.paddr := s1_paddr 127 io.lsroq.uop := s1_uop 128 io.lsroq.sqIdx := s1_uop.sqIdx 129 io.lsroq.lsroqIdx := s1_uop.lsroqIdx 130 io.lsroq.mask := s1_mask 131 io.lsroq.pc := s1_uop.cf.pc // FIXME: remove it 132 133 io.out.bits.forwardMask := io.sbuffer.forwardMask 134 io.out.bits.forwardData := io.sbuffer.forwardData 135 // generate XLEN/8 Muxs 136 for (i <- 0 until XLEN / 8) { 137 when(io.lsroq.forwardMask(i)) { 138 io.out.bits.forwardMask(i) := true.B 139 io.out.bits.forwardData(i) := io.lsroq.forwardData(i) 140 } 141 } 142 143 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 144 s1_uop.cf.pc, 145 io.lsroq.forwardData.asUInt, io.lsroq.forwardMask.asUInt, 146 io.sbuffer.forwardData.asUInt, io.sbuffer.forwardMask.asUInt 147 ) 148 149 io.out.valid := io.in.valid && !s1_tlb_miss && !s1_uop.roqIdx.needFlush(io.redirect) 150 io.out.bits.paddr := s1_paddr 151 io.out.bits.mmio := s1_mmio 152 io.out.bits.tlbMiss := s1_tlb_miss 153 154 io.in.ready := io.out.ready || !io.in.valid 155 156} 157 158 159// Load Pipeline Stage 2 160// DCache resp 161class LoadUnit_S2 extends XSModule { 162 val io = IO(new Bundle() { 163 val in = Flipped(Decoupled(new LsPipelineBundle)) 164 val out = Decoupled(new LsPipelineBundle) 165 val redirect = Flipped(ValidIO(new Redirect)) 166 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 167 }) 168 169 val s2_uop = io.in.bits.uop 170 val s2_mask = io.in.bits.mask 171 val s2_paddr = io.in.bits.paddr 172 val s2_cache_miss = io.dcacheResp.bits.miss 173 val s2_cache_nack = io.dcacheResp.bits.nack 174 175 176 io.dcacheResp.ready := true.B 177 assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost") 178 179 val forwardMask = io.in.bits.forwardMask 180 val forwardData = io.in.bits.forwardData 181 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 182 183 // data merge 184 val rdata = VecInit((0 until XLEN / 8).map(j => 185 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 186 val rdataSel = LookupTree(s2_paddr(2, 0), List( 187 "b000".U -> rdata(63, 0), 188 "b001".U -> rdata(63, 8), 189 "b010".U -> rdata(63, 16), 190 "b011".U -> rdata(63, 24), 191 "b100".U -> rdata(63, 32), 192 "b101".U -> rdata(63, 40), 193 "b110".U -> rdata(63, 48), 194 "b111".U -> rdata(63, 56) 195 )) 196 val rdataPartialLoad = LookupTree(s2_uop.ctrl.fuOpType, List( 197 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 198 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 199 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 200 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 201 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 202 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 203 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN), 204 LSUOpType.flw -> boxF32ToF64(rdataSel(31, 0)) 205 )) 206 207 // TODO: ECC check 208 209 io.out.valid := io.in.valid // && !s2_uop.needFlush(io.redirect) will cause comb. loop 210 // Inst will be canceled in store queue / lsroq, 211 // so we do not need to care about flush in load / store unit's out.valid 212 io.out.bits := io.in.bits 213 io.out.bits.data := rdataPartialLoad 214 io.out.bits.miss := (s2_cache_miss || s2_cache_nack) && !fullForward 215 io.out.bits.mmio := io.in.bits.mmio 216 217 io.in.ready := io.out.ready || !io.in.valid 218 219 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 220 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 221 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 222 ) 223 224} 225 226 227class LoadUnit extends XSModule { 228 val io = IO(new Bundle() { 229 val ldin = Flipped(Decoupled(new ExuInput)) 230 val ldout = Decoupled(new ExuOutput) 231 val redirect = Flipped(ValidIO(new Redirect)) 232 val tlbFeedback = ValidIO(new TlbFeedback) 233 val dcache = new DCacheLoadIO 234 val dtlb = new TlbRequestIO() 235 val sbuffer = new LoadForwardQueryIO 236 val lsroq = new LoadToLsroqIO 237 }) 238 239 val load_s0 = Module(new LoadUnit_S0) 240 val load_s1 = Module(new LoadUnit_S1) 241 val load_s2 = Module(new LoadUnit_S2) 242 243 load_s0.io.in <> io.ldin 244 load_s0.io.redirect <> io.redirect 245 load_s0.io.dtlbReq <> io.dtlb.req 246 load_s0.io.dtlbResp <> io.dtlb.resp 247 load_s0.io.dcacheReq <> io.dcache.req 248 load_s0.io.tlbFeedback <> io.tlbFeedback 249 250 PipelineConnect(load_s0.io.out, load_s1.io.in, load_s1.io.out.fire() || load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect), false.B) 251 252 io.dcache.s1_paddr := load_s1.io.out.bits.paddr 253 load_s1.io.redirect <> io.redirect 254 io.dcache.s1_kill := DontCare // FIXME 255 io.sbuffer <> load_s1.io.sbuffer 256 io.lsroq.forward <> load_s1.io.lsroq 257 258 PipelineConnect(load_s1.io.out, load_s2.io.in, load_s2.io.out.fire() || load_s1.io.out.bits.tlbMiss, false.B) 259 260 load_s2.io.redirect <> io.redirect 261 load_s2.io.dcacheResp <> io.dcache.resp 262 263 XSDebug(load_s0.io.out.valid, 264 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 265 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 266 XSDebug(load_s1.io.out.valid, 267 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 268 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 269 270 // writeback to LSROQ 271 // Current dcache use MSHR 272 io.lsroq.loadIn.valid := load_s2.io.out.valid 273 io.lsroq.loadIn.bits := load_s2.io.out.bits 274 275 val hitLoadOut = Wire(Valid(new ExuOutput)) 276 hitLoadOut.valid := load_s2.io.out.valid && !load_s2.io.out.bits.miss 277 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 278 hitLoadOut.bits.data := load_s2.io.out.bits.data 279 hitLoadOut.bits.redirectValid := false.B 280 hitLoadOut.bits.redirect := DontCare 281 hitLoadOut.bits.brUpdate := DontCare 282 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 283 hitLoadOut.bits.fflags := DontCare 284 285 // TODO: arbiter 286 // if hit, writeback result to CDB 287 // val ldout = Vec(2, Decoupled(new ExuOutput)) 288 // when io.loadIn(i).fire() && !io.io.loadIn(i).miss, commit load to cdb 289 // val cdbArb = Module(new Arbiter(new ExuOutput, 2)) 290 // io.ldout <> cdbArb.io.out 291 // hitLoadOut <> cdbArb.io.in(0) 292 // io.lsroq.ldout <> cdbArb.io.in(1) // missLoadOut 293 load_s2.io.out.ready := true.B 294 io.lsroq.ldout.ready := !hitLoadOut.valid 295 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsroq.ldout.bits) 296 io.ldout.valid := hitLoadOut.valid || io.lsroq.ldout.valid 297 298 when(io.ldout.fire()){ 299 XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen) 300 } 301} 302