1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val loadDataForwarded = Output(Bool()) 16 val forward = new LoadForwardQueryIO 17} 18 19// Load Pipeline Stage 0 20// Generate addr, use addr to query DCache and DTLB 21class LoadUnit_S0 extends XSModule { 22 val io = IO(new Bundle() { 23 val in = Flipped(Decoupled(new ExuInput)) 24 val out = Decoupled(new LsPipelineBundle) 25 val dtlbReq = DecoupledIO(new TlbReq) 26 val dcacheReq = DecoupledIO(new DCacheWordReq) 27 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 28 }) 29 30 val s0_uop = io.in.bits.uop 31 val s0_vaddr_old = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN) 32 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 33 val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 34 val s0_vaddr_hi = Mux(imm12(11), 35 Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)), 36 Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12)) 37 ) 38 val s0_vaddr = Cat(s0_vaddr_hi, s0_vaddr_lo(11,0)) 39 when(io.in.fire() && s0_vaddr(VAddrBits-1,0) =/= (io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN))(VAddrBits-1,0)){ 40 printf("s0_vaddr %x s0_vaddr_old %x\n", s0_vaddr, s0_vaddr_old(VAddrBits-1,0)) 41 } 42 val s0_mask = genWmask(s0_vaddr_lo, s0_uop.ctrl.fuOpType(1,0)) 43 44 // query DTLB 45 io.dtlbReq.valid := io.in.valid 46 io.dtlbReq.bits.vaddr := s0_vaddr 47 io.dtlbReq.bits.cmd := TlbCmd.read 48 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 49 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 50 51 // query DCache 52 io.dcacheReq.valid := io.in.valid 53 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 54 io.dcacheReq.bits.addr := s0_vaddr 55 io.dcacheReq.bits.mask := s0_mask 56 io.dcacheReq.bits.data := DontCare 57 58 // TODO: update cache meta 59 io.dcacheReq.bits.id := DontCare 60 61 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 62 "b00".U -> true.B, //b 63 "b01".U -> (s0_vaddr(0) === 0.U), //h 64 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 65 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 66 )) 67 68 io.out.valid := io.in.valid && io.dcacheReq.ready 69 70 io.out.bits := DontCare 71 io.out.bits.vaddr := s0_vaddr 72 io.out.bits.mask := s0_mask 73 io.out.bits.uop := s0_uop 74 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 75 io.out.bits.rsIdx := io.rsIdx 76 77 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 78 79 XSDebug(io.dcacheReq.fire(), 80 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 81 ) 82} 83 84 85// Load Pipeline Stage 1 86// TLB resp (send paddr to dcache) 87class LoadUnit_S1 extends XSModule { 88 val io = IO(new Bundle() { 89 val in = Flipped(Decoupled(new LsPipelineBundle)) 90 val out = Decoupled(new LsPipelineBundle) 91 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 92 val dcachePAddr = Output(UInt(PAddrBits.W)) 93 val dcacheKill = Output(Bool()) 94 val sbuffer = new LoadForwardQueryIO 95 val lsq = new LoadForwardQueryIO 96 }) 97 98 val s1_uop = io.in.bits.uop 99 val s1_paddr = io.dtlbResp.bits.paddr 100 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 101 val s1_tlb_miss = io.dtlbResp.bits.miss 102 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 103 val s1_mask = io.in.bits.mask 104 105 io.out.bits := io.in.bits // forwardXX field will be updated in s1 106 107 io.dtlbResp.ready := true.B 108 109 // TOOD: PMA check 110 io.dcachePAddr := s1_paddr 111 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 112 113 // load forward query datapath 114 io.sbuffer.valid := io.in.valid 115 io.sbuffer.paddr := s1_paddr 116 io.sbuffer.uop := s1_uop 117 io.sbuffer.sqIdx := s1_uop.sqIdx 118 io.sbuffer.mask := s1_mask 119 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 120 121 io.lsq.valid := io.in.valid 122 io.lsq.paddr := s1_paddr 123 io.lsq.uop := s1_uop 124 io.lsq.sqIdx := s1_uop.sqIdx 125 io.lsq.mask := s1_mask 126 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 127 128 io.out.valid := io.in.valid// && !s1_tlb_miss 129 io.out.bits.paddr := s1_paddr 130 io.out.bits.mmio := s1_mmio && !s1_exception 131 io.out.bits.tlbMiss := s1_tlb_miss 132 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 133 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 134 io.out.bits.rsIdx := io.in.bits.rsIdx 135 136 io.in.ready := !io.in.valid || io.out.ready 137 138} 139 140 141// Load Pipeline Stage 2 142// DCache resp 143class LoadUnit_S2 extends XSModule with HasLoadHelper { 144 val io = IO(new Bundle() { 145 val in = Flipped(Decoupled(new LsPipelineBundle)) 146 val out = Decoupled(new LsPipelineBundle) 147 val tlbFeedback = ValidIO(new TlbFeedback) 148 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 149 val lsq = new LoadForwardQueryIO 150 val sbuffer = new LoadForwardQueryIO 151 val dataForwarded = Output(Bool()) 152 }) 153 154 val s2_uop = io.in.bits.uop 155 val s2_mask = io.in.bits.mask 156 val s2_paddr = io.in.bits.paddr 157 val s2_tlb_miss = io.in.bits.tlbMiss 158 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 159 val s2_mmio = io.in.bits.mmio && !s2_exception 160 val s2_cache_miss = io.dcacheResp.bits.miss 161 val s2_cache_replay = io.dcacheResp.bits.replay 162 163 io.dcacheResp.ready := true.B 164 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 165 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 166 167 // feedback tlb result to RS 168 io.tlbFeedback.valid := io.in.valid 169 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 170 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 171 172 val forwardMask = io.out.bits.forwardMask 173 val forwardData = io.out.bits.forwardData 174 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 175 176 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 177 s2_uop.cf.pc, 178 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 179 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 180 ) 181 182 // data merge 183 val rdata = VecInit((0 until XLEN / 8).map(j => 184 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 185 val rdataSel = LookupTree(s2_paddr(2, 0), List( 186 "b000".U -> rdata(63, 0), 187 "b001".U -> rdata(63, 8), 188 "b010".U -> rdata(63, 16), 189 "b011".U -> rdata(63, 24), 190 "b100".U -> rdata(63, 32), 191 "b101".U -> rdata(63, 40), 192 "b110".U -> rdata(63, 48), 193 "b111".U -> rdata(63, 56) 194 )) 195 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 196 197 // TODO: ECC check 198 199 io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception) 200 // Inst will be canceled in store queue / lsq, 201 // so we do not need to care about flush in load / store unit's out.valid 202 io.out.bits := io.in.bits 203 io.out.bits.data := rdataPartialLoad 204 // when exception occurs, set it to not miss and let it write back to roq (via int port) 205 io.out.bits.miss := s2_cache_miss && !s2_exception 206 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 207 io.out.bits.mmio := s2_mmio 208 209 // For timing reasons, we can not let 210 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 211 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 212 // and dcache query is no longer needed. 213 // Such inst will be writebacked from load queue. 214 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception 215 216 io.in.ready := io.out.ready || !io.in.valid 217 218 // merge forward result 219 // lsq has higher priority than sbuffer 220 io.lsq := DontCare 221 io.sbuffer := DontCare 222 // generate XLEN/8 Muxs 223 for (i <- 0 until XLEN / 8) { 224 when (io.sbuffer.forwardMask(i)) { 225 io.out.bits.forwardMask(i) := true.B 226 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 227 } 228 when (io.lsq.forwardMask(i)) { 229 io.out.bits.forwardMask(i) := true.B 230 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 231 } 232 } 233 234 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 235 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 236 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 237 ) 238} 239 240class LoadUnit extends XSModule with HasLoadHelper { 241 val io = IO(new Bundle() { 242 val ldin = Flipped(Decoupled(new ExuInput)) 243 val ldout = Decoupled(new ExuOutput) 244 val fpout = Decoupled(new ExuOutput) 245 val redirect = Flipped(ValidIO(new Redirect)) 246 val flush = Input(Bool()) 247 val tlbFeedback = ValidIO(new TlbFeedback) 248 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 249 val dcache = new DCacheLoadIO 250 val dtlb = new TlbRequestIO() 251 val sbuffer = new LoadForwardQueryIO 252 val lsq = new LoadToLsqIO 253 }) 254 255 val load_s0 = Module(new LoadUnit_S0) 256 val load_s1 = Module(new LoadUnit_S1) 257 val load_s2 = Module(new LoadUnit_S2) 258 259 load_s0.io.in <> io.ldin 260 load_s0.io.dtlbReq <> io.dtlb.req 261 load_s0.io.dcacheReq <> io.dcache.req 262 load_s0.io.rsIdx := io.rsIdx 263 264 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 265 266 load_s1.io.dtlbResp <> io.dtlb.resp 267 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 268 io.dcache.s1_kill <> load_s1.io.dcacheKill 269 load_s1.io.sbuffer <> io.sbuffer 270 load_s1.io.lsq <> io.lsq.forward 271 272 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 273 274 load_s2.io.tlbFeedback <> io.tlbFeedback 275 load_s2.io.dcacheResp <> io.dcache.resp 276 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 277 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 278 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 279 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 280 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 281 282 // use s2_hit_way to select data received in s1 283 load_s2.io.dcacheResp.bits.data := Mux1H(io.dcache.s2_hit_way, RegNext(io.dcache.s1_data)) 284 assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 285 286 XSDebug(load_s0.io.out.valid, 287 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 288 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 289 XSDebug(load_s1.io.out.valid, 290 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 291 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 292 293 // writeback to LSQ 294 // Current dcache use MSHR 295 // Load queue will be updated at s2 for both hit/miss int/fp load 296 io.lsq.loadIn.valid := load_s2.io.out.valid 297 io.lsq.loadIn.bits := load_s2.io.out.bits 298 299 // write to rob and writeback bus 300 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 301 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 302 303 // Int load, if hit, will be writebacked at s2 304 val intHitLoadOut = Wire(Valid(new ExuOutput)) 305 intHitLoadOut.valid := s2_wb_valid && !load_s2.io.out.bits.uop.ctrl.fpWen 306 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 307 intHitLoadOut.bits.data := load_s2.io.out.bits.data 308 intHitLoadOut.bits.redirectValid := false.B 309 intHitLoadOut.bits.redirect := DontCare 310 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 311 intHitLoadOut.bits.debug.isPerfCnt := false.B 312 intHitLoadOut.bits.fflags := DontCare 313 314 load_s2.io.out.ready := true.B 315 316 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 317 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 318 319 // Fp load, if hit, will be send to recoder at s2, then it will be recoded & writebacked at s3 320 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 321 fpHitLoadOut.valid := s2_wb_valid && load_s2.io.out.bits.uop.ctrl.fpWen 322 fpHitLoadOut.bits := intHitLoadOut.bits 323 324 val fpLoadOut = Wire(Valid(new ExuOutput)) 325 fpLoadOut.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 326 fpLoadOut.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 327 328 val fpLoadOutReg = RegNext(fpLoadOut) 329 io.fpout.bits := fpLoadOutReg.bits 330 io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode 331 io.fpout.valid := RegNext(fpLoadOut.valid) 332 333 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 334 335 when(io.ldout.fire()){ 336 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 337 } 338 339 when(io.fpout.fire()){ 340 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 341 } 342} 343