1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache._ 27import xiangshan.cache.mmu.{TLB, TlbCmd, TlbPtwIO, TlbReq, TlbRequestIO, TlbResp} 28 29class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 30 val loadIn = ValidIO(new LsPipelineBundle) 31 val ldout = Flipped(DecoupledIO(new ExuOutput)) 32 val loadDataForwarded = Output(Bool()) 33 val needReplayFromRS = Output(Bool()) 34 val forward = new PipeLoadForwardQueryIO 35 val loadViolationQuery = new LoadViolationQueryIO 36} 37 38class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 39 // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 40 val data = UInt(XLEN.W) 41 val valid = Bool() 42} 43 44// Load Pipeline Stage 0 45// Generate addr, use addr to query DCache and DTLB 46class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParameters{ 47 val io = IO(new Bundle() { 48 val in = Flipped(Decoupled(new ExuInput)) 49 val out = Decoupled(new LsPipelineBundle) 50 val fastpath = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 51 val dtlbReq = DecoupledIO(new TlbReq) 52 val dcacheReq = DecoupledIO(new DCacheWordReq) 53 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 54 val isFirstIssue = Input(Bool()) 55 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 56 }) 57 require(LoadPipelineWidth == exuParameters.LduCnt) 58 59 val s0_uop = io.in.bits.uop 60 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 61 62 // slow vaddr from non-load insts 63 val slowpath_vaddr = io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 64 val slowpath_mask = genWmask(slowpath_vaddr, s0_uop.ctrl.fuOpType(1,0)) 65 66 // fast vaddr from load insts 67 val fastpath_vaddrs = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 68 io.fastpath(i).data + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 69 }))) 70 val fastpath_masks = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 71 genWmask(fastpath_vaddrs(i), s0_uop.ctrl.fuOpType(1,0)) 72 }))) 73 val fastpath_vaddr = Mux1H(io.loadFastMatch, fastpath_vaddrs) 74 val fastpath_mask = Mux1H(io.loadFastMatch, fastpath_masks) 75 76 // select vaddr from 2 alus 77 val s0_vaddr = Mux(io.loadFastMatch.orR, fastpath_vaddr, slowpath_vaddr) 78 val s0_mask = Mux(io.loadFastMatch.orR, fastpath_mask, slowpath_mask) 79 XSPerfAccumulate("load_to_load_forward", io.loadFastMatch.orR && io.in.fire()) 80 81 val isSoftPrefetch = Wire(Bool()) 82 isSoftPrefetch := s0_uop.ctrl.isORI //it's a ORI but it exists in ldu, which means it's a softprefecth 83 val isSoftPrefetchRead = Wire(Bool()) 84 val isSoftPrefetchWrite = Wire(Bool()) 85 isSoftPrefetchRead := s0_uop.ctrl.isSoftPrefetchRead 86 isSoftPrefetchWrite := s0_uop.ctrl.isSoftPrefetchWrite 87 88 // query DTLB 89 io.dtlbReq.valid := io.in.valid 90 io.dtlbReq.bits.vaddr := s0_vaddr 91 io.dtlbReq.bits.cmd := TlbCmd.read 92 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 93 io.dtlbReq.bits.robIdx := s0_uop.robIdx 94 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 95 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 96 97 // query DCache 98 io.dcacheReq.valid := io.in.valid 99 when (isSoftPrefetchRead) { 100 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFR 101 }.elsewhen (isSoftPrefetchWrite) { 102 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFW 103 }.otherwise { 104 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 105 } 106 io.dcacheReq.bits.addr := s0_vaddr 107 io.dcacheReq.bits.mask := s0_mask 108 io.dcacheReq.bits.data := DontCare 109 when(isSoftPrefetch) { 110 io.dcacheReq.bits.instrtype := SOFT_PREFETCH.U 111 }.otherwise { 112 io.dcacheReq.bits.instrtype := LOAD_SOURCE.U 113 } 114 115 // TODO: update cache meta 116 io.dcacheReq.bits.id := DontCare 117 118 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 119 "b00".U -> true.B, //b 120 "b01".U -> (s0_vaddr(0) === 0.U), //h 121 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 122 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 123 )) 124 125 io.out.valid := io.in.valid && io.dcacheReq.ready 126 127 io.out.bits := DontCare 128 io.out.bits.vaddr := s0_vaddr 129 io.out.bits.mask := s0_mask 130 io.out.bits.uop := s0_uop 131 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 132 io.out.bits.rsIdx := io.rsIdx 133 io.out.bits.isFirstIssue := io.isFirstIssue 134 io.out.bits.isSoftPrefetch := isSoftPrefetch 135 136 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 137 138 XSDebug(io.dcacheReq.fire(), 139 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 140 ) 141 XSPerfAccumulate("in_valid", io.in.valid) 142 XSPerfAccumulate("in_fire", io.in.fire) 143 XSPerfAccumulate("in_fire_first_issue", io.in.valid && io.isFirstIssue) 144 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 145 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 146 XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 147 XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 148 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 149 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 150} 151 152 153// Load Pipeline Stage 1 154// TLB resp (send paddr to dcache) 155class LoadUnit_S1(implicit p: Parameters) extends XSModule { 156 val io = IO(new Bundle() { 157 val in = Flipped(Decoupled(new LsPipelineBundle)) 158 val out = Decoupled(new LsPipelineBundle) 159 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 160 val dcachePAddr = Output(UInt(PAddrBits.W)) 161 val dcacheKill = Output(Bool()) 162 val dcacheBankConflict = Input(Bool()) 163 val fullForwardFast = Output(Bool()) 164 val sbuffer = new LoadForwardQueryIO 165 val lsq = new PipeLoadForwardQueryIO 166 val loadViolationQueryReq = Decoupled(new LoadViolationQueryReq) 167 val rsFeedback = ValidIO(new RSFeedback) 168 val csrCtrl = Flipped(new CustomCSRCtrlIO) 169 val needLdVioCheckRedo = Output(Bool()) 170 }) 171 172 val s1_uop = io.in.bits.uop 173 val s1_paddr = io.dtlbResp.bits.paddr 174 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR // af & pf exception were modified below. 175 val s1_tlb_miss = io.dtlbResp.bits.miss 176 val s1_mask = io.in.bits.mask 177 val s1_bank_conflict = io.dcacheBankConflict 178 179 io.out.bits := io.in.bits // forwardXX field will be updated in s1 180 181 io.dtlbResp.ready := true.B 182 183 // TOOD: PMA check 184 io.dcachePAddr := s1_paddr 185 //io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 186 io.dcacheKill := s1_tlb_miss || s1_exception 187 188 // load forward query datapath 189 io.sbuffer.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 190 io.sbuffer.vaddr := io.in.bits.vaddr 191 io.sbuffer.paddr := s1_paddr 192 io.sbuffer.uop := s1_uop 193 io.sbuffer.sqIdx := s1_uop.sqIdx 194 io.sbuffer.mask := s1_mask 195 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 196 197 io.lsq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 198 io.lsq.vaddr := io.in.bits.vaddr 199 io.lsq.paddr := s1_paddr 200 io.lsq.uop := s1_uop 201 io.lsq.sqIdx := s1_uop.sqIdx 202 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 203 io.lsq.mask := s1_mask 204 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 205 206 // ld-ld violation query 207 io.loadViolationQueryReq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 208 io.loadViolationQueryReq.bits.paddr := s1_paddr 209 io.loadViolationQueryReq.bits.uop := s1_uop 210 211 // Generate forwardMaskFast to wake up insts earlier 212 val forwardMaskFast = io.lsq.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt 213 io.fullForwardFast := (~forwardMaskFast & s1_mask) === 0.U 214 215 // Generate feedback signal caused by: 216 // * dcache bank conflict 217 // * need redo ld-ld violation check 218 val needLdVioCheckRedo = io.loadViolationQueryReq.valid && 219 !io.loadViolationQueryReq.ready && 220 RegNext(io.csrCtrl.ldld_vio_check) 221 io.needLdVioCheckRedo := needLdVioCheckRedo 222 io.rsFeedback.valid := io.in.valid && (s1_bank_conflict || needLdVioCheckRedo) 223 io.rsFeedback.bits.hit := false.B // we have found s1_bank_conflict / re do ld-ld violation check 224 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 225 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 226 io.rsFeedback.bits.sourceType := Mux(s1_bank_conflict, RSFeedbackType.bankConflict, RSFeedbackType.ldVioCheckRedo) 227 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 228 229 // if replay is detected in load_s1, 230 // load inst will be canceled immediately 231 io.out.valid := io.in.valid && !io.rsFeedback.valid 232 io.out.bits.paddr := s1_paddr 233 io.out.bits.tlbMiss := s1_tlb_miss 234 235 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 236 // af & pf exception were modified 237 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 238 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 239 240 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 241 io.out.bits.rsIdx := io.in.bits.rsIdx 242 243 io.out.bits.isSoftPrefetch := io.in.bits.isSoftPrefetch 244 245 io.in.ready := !io.in.valid || io.out.ready 246 247 XSPerfAccumulate("in_valid", io.in.valid) 248 XSPerfAccumulate("in_fire", io.in.fire) 249 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 250 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 251 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 252 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 253} 254 255// Load Pipeline Stage 2 256// DCache resp 257class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper { 258 val io = IO(new Bundle() { 259 val in = Flipped(Decoupled(new LsPipelineBundle)) 260 val out = Decoupled(new LsPipelineBundle) 261 val rsFeedback = ValidIO(new RSFeedback) 262 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 263 val pmpResp = Flipped(new PMPRespBundle()) 264 val lsq = new LoadForwardQueryIO 265 val dataInvalidSqIdx = Input(UInt()) 266 val sbuffer = new LoadForwardQueryIO 267 val dataForwarded = Output(Bool()) 268 val needReplayFromRS = Output(Bool()) 269 val fullForward = Output(Bool()) 270 val fastpath = Output(new LoadToLoadIO) 271 val dcache_kill = Output(Bool()) 272 val loadViolationQueryResp = Flipped(Valid(new LoadViolationQueryResp)) 273 val csrCtrl = Flipped(new CustomCSRCtrlIO) 274 val sentFastUop = Input(Bool()) 275 }) 276 val isSoftPrefetch = io.in.bits.isSoftPrefetch 277 val excep = WireInit(io.in.bits.uop.cf.exceptionVec) 278 excep(loadAccessFault) := io.in.bits.uop.cf.exceptionVec(loadAccessFault) || io.pmpResp.ld 279 when (isSoftPrefetch) { 280 excep := 0.U.asTypeOf(excep.cloneType) 281 } 282 val s2_exception = selectLoad(excep, false).asUInt.orR 283 284 val actually_mmio = io.pmpResp.mmio 285 val s2_uop = io.in.bits.uop 286 val s2_mask = io.in.bits.mask 287 val s2_paddr = io.in.bits.paddr 288 val s2_tlb_miss = io.in.bits.tlbMiss 289 val s2_data_invalid = io.lsq.dataInvalid 290 val s2_mmio = !isSoftPrefetch && actually_mmio && !s2_exception 291 val s2_cache_miss = io.dcacheResp.bits.miss 292 val s2_cache_replay = io.dcacheResp.bits.replay 293 294 val s2_cache_miss_enter = io.dcacheResp.bits.miss_enter //missReq enter the mshr successfully 295 val isSoftPreExcept = io.in.bits.isSoftPreExcept 296 val isSoftPremmio = isSoftPrefetch && actually_mmio //TODO, fix it 297 // val cnt = RegInit(127.U) 298 // cnt := cnt + io.in.valid.asUInt 299 // val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid || cnt === 0.U 300 301 val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid 302 // assert(!s2_forward_fail) 303 io.dcache_kill := false.B // move pmp resp kill to outside 304 io.dcacheResp.ready := true.B 305 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 306 assert(!(io.in.valid && (dcacheShouldResp && !io.dcacheResp.valid) && (!isSoftPreExcept) && (!isSoftPremmio)), "DCache response got lost") 307 308 // merge forward result 309 // lsq has higher priority than sbuffer 310 val forwardMask = Wire(Vec(8, Bool())) 311 val forwardData = Wire(Vec(8, UInt(8.W))) 312 313 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U && !io.lsq.dataInvalid 314 io.lsq := DontCare 315 io.sbuffer := DontCare 316 io.fullForward := fullForward 317 318 // generate XLEN/8 Muxs 319 for (i <- 0 until XLEN / 8) { 320 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 321 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 322 } 323 324 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 325 s2_uop.cf.pc, 326 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 327 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 328 ) 329 330 // data merge 331 val rdataVec = VecInit((0 until XLEN / 8).map(j => 332 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 333 val rdata = rdataVec.asUInt 334 val rdataSel = LookupTree(s2_paddr(2, 0), List( 335 "b000".U -> rdata(63, 0), 336 "b001".U -> rdata(63, 8), 337 "b010".U -> rdata(63, 16), 338 "b011".U -> rdata(63, 24), 339 "b100".U -> rdata(63, 32), 340 "b101".U -> rdata(63, 40), 341 "b110".U -> rdata(63, 48), 342 "b111".U -> rdata(63, 56) 343 )) 344 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 345 346 io.out.valid := io.in.valid && !s2_tlb_miss && !s2_data_invalid 347 // Inst will be canceled in store queue / lsq, 348 // so we do not need to care about flush in load / store unit's out.valid 349 io.out.bits := io.in.bits 350 io.out.bits.data := rdataPartialLoad 351 // when exception occurs, set it to not miss and let it write back to rob (via int port) 352 if (EnableFastForward) { 353 when(io.in.bits.isSoftPrefetch) { 354 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail && !fullForward && !s2_cache_miss_enter && !isSoftPreExcept && !isSoftPremmio 355 }.otherwise { 356 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail && !fullForward 357 } 358 } else { 359 when(io.in.bits.isSoftPrefetch) { 360 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail && !s2_cache_miss_enter && !isSoftPreExcept && !isSoftPremmio 361 }.otherwise { 362 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail 363 } 364 } 365 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 366 // if forward fail, replay this inst from fetch 367 val forwardFailReplay = s2_forward_fail && !s2_mmio 368 // if ld-ld violation is detected, replay from this inst from fetch 369 val ldldVioReplay = io.loadViolationQueryResp.valid && 370 io.loadViolationQueryResp.bits.have_violation && 371 RegNext(io.csrCtrl.ldld_vio_check) 372 io.out.bits.uop.ctrl.replayInst := forwardFailReplay || ldldVioReplay 373 io.out.bits.mmio := s2_mmio 374 io.out.bits.uop.ctrl.flushPipe := io.in.bits.uop.ctrl.flushPipe || (s2_mmio && io.sentFastUop) 375 io.out.bits.uop.cf.exceptionVec := excep 376 377 // For timing reasons, sometimes we can not let 378 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 379 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 380 // and dcache query is no longer needed. 381 // Such inst will be writebacked from load queue. 382 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception && !s2_forward_fail 383 // io.out.bits.forwardX will be send to lq 384 io.out.bits.forwardMask := forwardMask 385 // data retbrived from dcache is also included in io.out.bits.forwardData 386 io.out.bits.forwardData := rdataVec 387 388 io.in.ready := io.out.ready || !io.in.valid 389 390 // feedback tlb result to RS 391 io.rsFeedback.valid := io.in.valid 392 when (io.in.bits.isSoftPrefetch) { 393 io.rsFeedback.bits.hit := (!s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid) || s2_cache_miss_enter || isSoftPreExcept || isSoftPremmio 394 }.otherwise { 395 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid 396 } 397 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 398 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 399 io.rsFeedback.bits.sourceType := Mux(s2_tlb_miss, RSFeedbackType.tlbMiss, 400 Mux(io.lsq.dataInvalid, 401 RSFeedbackType.dataInvalid, 402 RSFeedbackType.mshrFull 403 ) 404 ) 405 io.rsFeedback.bits.dataInvalidSqIdx.value := io.dataInvalidSqIdx 406 io.rsFeedback.bits.dataInvalidSqIdx.flag := DontCare 407 408 // s2_cache_replay is quite slow to generate, send it separately to LQ 409 io.needReplayFromRS := s2_cache_replay && !fullForward 410 411 // fast load to load forward 412 io.fastpath.valid := io.in.valid // for debug only 413 io.fastpath.data := rdata // raw data 414 415 416 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 417 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 418 forwardData.asUInt, forwardMask.asUInt 419 ) 420 421 XSPerfAccumulate("in_valid", io.in.valid) 422 XSPerfAccumulate("in_fire", io.in.fire) 423 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 424 XSPerfAccumulate("dcache_miss", io.in.fire && s2_cache_miss) 425 XSPerfAccumulate("dcache_miss_first_issue", io.in.fire && s2_cache_miss && io.in.bits.isFirstIssue) 426 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 427 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 428 XSPerfAccumulate("replay", io.rsFeedback.valid && !io.rsFeedback.bits.hit) 429 XSPerfAccumulate("replay_tlb_miss", io.rsFeedback.valid && !io.rsFeedback.bits.hit && s2_tlb_miss) 430 XSPerfAccumulate("replay_cache", io.rsFeedback.valid && !io.rsFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 431 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 432 XSPerfAccumulate("replay_from_fetch_forward", io.out.valid && forwardFailReplay) 433 XSPerfAccumulate("replay_from_fetch_load_vio", io.out.valid && ldldVioReplay) 434} 435 436class LoadUnit(implicit p: Parameters) extends XSModule with HasLoadHelper { 437 val io = IO(new Bundle() { 438 val ldin = Flipped(Decoupled(new ExuInput)) 439 val ldout = Decoupled(new ExuOutput) 440 val redirect = Flipped(ValidIO(new Redirect)) 441 val feedbackSlow = ValidIO(new RSFeedback) 442 val feedbackFast = ValidIO(new RSFeedback) 443 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 444 val isFirstIssue = Input(Bool()) 445 val dcache = new DCacheLoadIO 446 val sbuffer = new LoadForwardQueryIO 447 val lsq = new LoadToLsqIO 448 val fastUop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1 449 450 val tlb = new TlbRequestIO 451 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 452 453 val fastpathOut = Output(new LoadToLoadIO) 454 val fastpathIn = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 455 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 456 457 val csrCtrl = Flipped(new CustomCSRCtrlIO) 458 }) 459 460 val load_s0 = Module(new LoadUnit_S0) 461 val load_s1 = Module(new LoadUnit_S1) 462 val load_s2 = Module(new LoadUnit_S2) 463 464 load_s0.io.in <> io.ldin 465 load_s0.io.dtlbReq <> io.tlb.req 466 load_s0.io.dcacheReq <> io.dcache.req 467 load_s0.io.rsIdx := io.rsIdx 468 load_s0.io.isFirstIssue := io.isFirstIssue 469 load_s0.io.fastpath := io.fastpathIn 470 load_s0.io.loadFastMatch := io.loadFastMatch 471 472 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 473 474 load_s1.io.dtlbResp <> io.tlb.resp 475 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 476 io.dcache.s1_kill <> load_s1.io.dcacheKill 477 load_s1.io.sbuffer <> io.sbuffer 478 load_s1.io.lsq <> io.lsq.forward 479 load_s1.io.loadViolationQueryReq <> io.lsq.loadViolationQuery.req 480 load_s1.io.dcacheBankConflict <> io.dcache.s1_bank_conflict 481 load_s1.io.csrCtrl <> io.csrCtrl 482 483 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 484 485 io.dcache.s2_kill := load_s2.io.dcache_kill || (io.pmp.ld || io.pmp.mmio) // to kill mmio resp which are redirected 486 load_s2.io.dcacheResp <> io.dcache.resp 487 load_s2.io.pmpResp <> io.pmp 488 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 489 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 490 load_s2.io.lsq.forwardMaskFast <> io.lsq.forward.forwardMaskFast // should not be used in load_s2 491 load_s2.io.lsq.dataInvalid <> io.lsq.forward.dataInvalid 492 load_s2.io.lsq.matchInvalid <> io.lsq.forward.matchInvalid 493 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 494 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 495 load_s2.io.sbuffer.forwardMaskFast <> io.sbuffer.forwardMaskFast // should not be used in load_s2 496 load_s2.io.sbuffer.dataInvalid <> io.sbuffer.dataInvalid // always false 497 load_s2.io.sbuffer.matchInvalid <> io.sbuffer.matchInvalid 498 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 499 load_s2.io.fastpath <> io.fastpathOut 500 load_s2.io.dataInvalidSqIdx := io.lsq.forward.dataInvalidSqIdx // provide dataInvalidSqIdx to make wakeup faster 501 load_s2.io.loadViolationQueryResp <> io.lsq.loadViolationQuery.resp 502 load_s2.io.csrCtrl <> io.csrCtrl 503 load_s2.io.sentFastUop := RegEnable(io.fastUop.valid, load_s1.io.out.fire()) // RegNext is also ok 504 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 505 506 // feedback tlb miss / dcache miss queue full 507 io.feedbackSlow.bits := RegNext(load_s2.io.rsFeedback.bits) 508 io.feedbackSlow.valid := RegNext(load_s2.io.rsFeedback.valid && !load_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 509 510 // feedback bank conflict to rs 511 io.feedbackFast.bits := load_s1.io.rsFeedback.bits 512 io.feedbackFast.valid := load_s1.io.rsFeedback.valid 513 // If replay is reported at load_s1, inst will be canceled (will not enter load_s2), 514 // in that case: 515 // * replay should not be reported twice 516 assert(!(RegNext(RegNext(io.feedbackFast.valid)) && io.feedbackSlow.valid)) 517 // * io.fastUop.valid should not be reported 518 assert(!RegNext(io.feedbackFast.valid && io.fastUop.valid)) 519 520 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 521 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 522 io.lsq.forward.sqIdxMask := sqIdxMaskReg 523 524 // // use s2_hit_way to select data received in s1 525 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 526 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 527 528 io.fastUop.valid := io.dcache.s1_hit_way.orR && // dcache hit 529 !io.dcache.s1_disable_fast_wakeup && // load fast wakeup should be disabled when dcache data read is not ready 530 load_s1.io.in.valid && // valid laod request 531 !load_s1.io.dcacheKill && // not mmio or tlb miss 532 !io.lsq.forward.dataInvalidFast && // forward failed 533 !load_s1.io.needLdVioCheckRedo // load-load violation check: load paddr cam struct hazard 534 io.fastUop.bits := load_s1.io.out.bits.uop 535 536 XSDebug(load_s0.io.out.valid, 537 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 538 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 539 XSDebug(load_s1.io.out.valid, 540 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 541 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 542 543 // writeback to LSQ 544 // Current dcache use MSHR 545 // Load queue will be updated at s2 for both hit/miss int/fp load 546 io.lsq.loadIn.valid := load_s2.io.out.valid 547 io.lsq.loadIn.bits := load_s2.io.out.bits 548 549 // write to rob and writeback bus 550 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss && !load_s2.io.out.bits.mmio 551 552 // Int load, if hit, will be writebacked at s2 553 val hitLoadOut = Wire(Valid(new ExuOutput)) 554 hitLoadOut.valid := s2_wb_valid 555 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 556 hitLoadOut.bits.data := load_s2.io.out.bits.data 557 hitLoadOut.bits.redirectValid := false.B 558 hitLoadOut.bits.redirect := DontCare 559 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 560 hitLoadOut.bits.debug.isPerfCnt := false.B 561 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 562 hitLoadOut.bits.fflags := DontCare 563 564 load_s2.io.out.ready := true.B 565 566 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 567 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 568 569 io.lsq.ldout.ready := !hitLoadOut.valid 570 571 val perfinfo = IO(new Bundle(){ 572 val perfEvents = Output(new PerfEventsBundle(12)) 573 }) 574 575 val perfEvents = Seq( 576 ("load_s0_in_fire ", load_s0.io.in.fire() ), 577 ("load_to_load_forward ", load_s0.io.loadFastMatch.orR && load_s0.io.in.fire() ), 578 ("stall_dcache ", load_s0.io.out.valid && load_s0.io.out.ready && !load_s0.io.dcacheReq.ready ), 579 ("addr_spec_success ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) === load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 580 ("addr_spec_failed ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) =/= load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 581 ("load_s1_in_fire ", load_s1.io.in.fire ), 582 ("load_s1_tlb_miss ", load_s1.io.in.fire && load_s1.io.dtlbResp.bits.miss ), 583 ("load_s2_in_fire ", load_s2.io.in.fire ), 584 ("load_s2_dcache_miss ", load_s2.io.in.fire && load_s2.io.dcacheResp.bits.miss ), 585 ("load_s2_replay ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit ), 586 ("load_s2_replay_tlb_miss ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && load_s2.io.in.bits.tlbMiss ), 587 ("load_s2_replay_cache ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && !load_s2.io.in.bits.tlbMiss && load_s2.io.dcacheResp.bits.miss), 588 ) 589 590 for (((perf_out,(perf_name,perf)),i) <- perfinfo.perfEvents.perf_events.zip(perfEvents).zipWithIndex) { 591 perf_out.incr_step := RegNext(perf) 592 } 593 594 when(io.ldout.fire()){ 595 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 596 } 597} 598