1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.rob.RobPtr 31import xiangshan.cache._ 32import xiangshan.cache.wpu.ReplayCarry 33import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 34import xiangshan.mem.mdp._ 35 36class LoadToLsqReplayIO(implicit p: Parameters) extends XSBundle with HasDCacheParameters { 37 // mshr refill index 38 val mshr_id = UInt(log2Up(cfg.nMissEntries).W) 39 // get full data from store queue and sbuffer 40 val full_fwd = Bool() 41 // wait for data from store inst's store queue index 42 val data_inv_sq_idx = new SqPtr 43 // wait for address from store queue index 44 val addr_inv_sq_idx = new SqPtr 45 // replay carry 46 val rep_carry = new ReplayCarry(nWays) 47 // data in last beat 48 val last_beat = Bool() 49 // replay cause 50 val cause = Vec(LoadReplayCauses.allCauses, Bool()) 51 // performance debug information 52 val debug = new PerfDebugInfo 53 54 // alias 55 def tlb_miss = cause(LoadReplayCauses.C_TM) 56 def nuke = cause(LoadReplayCauses.C_NK) 57 def mem_amb = cause(LoadReplayCauses.C_MA) 58 def fwd_fail = cause(LoadReplayCauses.C_FF) 59 def dcache_miss = cause(LoadReplayCauses.C_DM) 60 def bank_conflict = cause(LoadReplayCauses.C_BC) 61 def dcache_rep = cause(LoadReplayCauses.C_DR) 62 def rar_nack = cause(LoadReplayCauses.C_RAR) 63 def raw_nack = cause(LoadReplayCauses.C_RAW) 64 def need_rep = cause.asUInt.orR 65} 66 67 68class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 69 val ldin = DecoupledIO(new LqWriteBundle) 70 val uncache = Flipped(DecoupledIO(new MemExuOutput)) 71 val ld_raw_data = Input(new LoadDataFromLQBundle) 72 val forward = new PipeLoadForwardQueryIO 73 val stld_nuke_query = new LoadNukeQueryIO 74 val ldld_nuke_query = new LoadNukeQueryIO 75 val trigger = Flipped(new LqTriggerIO) 76} 77 78class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 79 val valid = Bool() 80 val data = UInt(XLEN.W) // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 81 val dly_ld_err = Bool() 82} 83 84class LoadUnitTriggerIO(implicit p: Parameters) extends XSBundle { 85 val tdata2 = Input(UInt(64.W)) 86 val matchType = Input(UInt(2.W)) 87 val tEnable = Input(Bool()) // timing is calculated before this 88 val addrHit = Output(Bool()) 89 val lastDataHit = Output(Bool()) 90} 91 92class LoadUnit(implicit p: Parameters) extends XSModule 93 with HasLoadHelper 94 with HasPerfEvents 95 with HasDCacheParameters 96 with HasCircularQueuePtrHelper 97{ 98 val io = IO(new Bundle() { 99 // control 100 val redirect = Flipped(ValidIO(new Redirect)) 101 val csrCtrl = Flipped(new CustomCSRCtrlIO) 102 103 // int issue path 104 val ldin = Flipped(Decoupled(new MemExuInput)) 105 val ldout = Decoupled(new MemExuOutput) 106 107 // data path 108 val tlb = new TlbRequestIO(2) 109 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 110 val dcache = new DCacheLoadIO 111 val sbuffer = new LoadForwardQueryIO 112 val lsq = new LoadToLsqIO 113 val tl_d_channel = Input(new DcacheToLduForwardIO) 114 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 115 val refill = Flipped(ValidIO(new Refill)) 116 val l2_hint = Input(Valid(new L2ToL1Hint)) 117 118 // fast wakeup 119 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 120 121 // trigger 122 val trigger = Vec(3, new LoadUnitTriggerIO) 123 124 // prefetch 125 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info 126 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) // hardware prefetch to l1 cache req 127 128 // load to load fast path 129 val l2l_fwd_in = Input(new LoadToLoadIO) 130 val l2l_fwd_out = Output(new LoadToLoadIO) 131 val ld_fast_match = Input(Bool()) 132 val ld_fast_imm = Input(UInt(12.W)) 133 134 // rs feedback 135 val feedback_fast = ValidIO(new RSFeedback) // stage 2 136 val feedback_slow = ValidIO(new RSFeedback) // stage 3 137 val ldCancel = Output(new LoadCancelIO()) // use to cancel the uops waked by this load, and cancel load 138 139 // load ecc error 140 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 141 142 // schedule error query 143 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 144 145 // queue-based replay 146 val replay = Flipped(Decoupled(new LsPipelineBundle)) 147 val lq_rep_full = Input(Bool()) 148 149 // misc 150 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 151 152 // Load fast replay path 153 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 154 val fast_rep_out = Decoupled(new LqWriteBundle) 155 156 // perf 157 val debug_ls = Output(new DebugLsInfoBundle) 158 val lsTopdownInfo = Output(new LsTopdownInfo) 159 }) 160 161 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 162 163 // Pipeline 164 // -------------------------------------------------------------------------------- 165 // stage 0 166 // -------------------------------------------------------------------------------- 167 // generate addr, use addr to query DCache and DTLB 168 val s0_valid = Wire(Bool()) 169 val s0_kill = Wire(Bool()) 170 val s0_vaddr = Wire(UInt(VAddrBits.W)) 171 val s0_mask = Wire(UInt((VLEN/8).W)) 172 val s0_uop = Wire(new DynInst) 173 val s0_has_rob_entry = Wire(Bool()) 174 val s0_rsIdx = Wire(UInt(log2Up(MemIQSizeMax).W)) 175 val s0_sqIdx = Wire(new SqPtr) 176 val s0_mshrid = Wire(UInt()) 177 val s0_try_l2l = Wire(Bool()) 178 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 179 val s0_isFirstIssue = Wire(Bool()) 180 val s0_fast_rep = Wire(Bool()) 181 val s0_ld_rep = Wire(Bool()) 182 val s0_l2l_fwd = Wire(Bool()) 183 val s0_sched_idx = Wire(UInt()) 184 // Record the issue port idx of load issue queue. This signal is used by load cancel. 185 val s0_deqPortIdx = Wire(UInt(log2Ceil(LoadPipelineWidth).W)) 186 val s0_can_go = s1_ready 187 val s0_fire = s0_valid && s0_can_go 188 val s0_out = Wire(new LqWriteBundle) 189 190 // load flow select/gen 191 // src0: super load replayed by LSQ (cache miss replay) (io.replay) 192 // src1: fast load replay (io.fast_rep_in) 193 // src2: load replayed by LSQ (io.replay) 194 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 195 // src4: int read / software prefetch first issue from RS (io.in) 196 // src5: vec read first issue from RS (TODO) 197 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 198 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 199 // priority: high to low 200 val s0_rep_stall = io.ldin.valid && isAfter(io.replay.bits.uop.robIdx, io.ldin.bits.uop.robIdx) 201 val s0_super_ld_rep_valid = io.replay.valid && io.replay.bits.forward_tlDchannel 202 val s0_ld_fast_rep_valid = io.fast_rep_in.valid 203 val s0_ld_rep_valid = io.replay.valid && !io.replay.bits.forward_tlDchannel && !s0_rep_stall 204 val s0_high_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence > 0.U 205 val s0_int_iss_valid = io.ldin.valid // int flow first issue or software prefetch 206 val s0_vec_iss_valid = WireInit(false.B) // TODO 207 val s0_l2l_fwd_valid = io.l2l_fwd_in.valid 208 val s0_low_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence === 0.U 209 dontTouch(s0_super_ld_rep_valid) 210 dontTouch(s0_ld_fast_rep_valid) 211 dontTouch(s0_ld_rep_valid) 212 dontTouch(s0_high_conf_prf_valid) 213 dontTouch(s0_int_iss_valid) 214 dontTouch(s0_vec_iss_valid) 215 dontTouch(s0_l2l_fwd_valid) 216 dontTouch(s0_low_conf_prf_valid) 217 218 // load flow source ready 219 val s0_super_ld_rep_ready = WireInit(true.B) 220 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 221 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 222 !s0_ld_fast_rep_valid 223 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 224 !s0_ld_fast_rep_valid && 225 !s0_ld_rep_valid 226 227 val s0_int_iss_ready = !s0_super_ld_rep_valid && 228 !s0_ld_fast_rep_valid && 229 !s0_ld_rep_valid && 230 !s0_high_conf_prf_valid 231 232 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 233 !s0_ld_fast_rep_valid && 234 !s0_ld_rep_valid && 235 !s0_high_conf_prf_valid && 236 !s0_int_iss_valid 237 238 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 239 !s0_ld_fast_rep_valid && 240 !s0_ld_rep_valid && 241 !s0_high_conf_prf_valid && 242 !s0_int_iss_valid && 243 !s0_vec_iss_valid 244 245 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 246 !s0_ld_fast_rep_valid && 247 !s0_ld_rep_valid && 248 !s0_high_conf_prf_valid && 249 !s0_int_iss_valid && 250 !s0_vec_iss_valid && 251 !s0_l2l_fwd_valid 252 dontTouch(s0_super_ld_rep_ready) 253 dontTouch(s0_ld_fast_rep_ready) 254 dontTouch(s0_ld_rep_ready) 255 dontTouch(s0_high_conf_prf_ready) 256 dontTouch(s0_int_iss_ready) 257 dontTouch(s0_vec_iss_ready) 258 dontTouch(s0_l2l_fwd_ready) 259 dontTouch(s0_low_conf_prf_ready) 260 261 // load flow source select (OH) 262 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 263 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 264 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 265 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 266 s0_low_conf_prf_ready && s0_low_conf_prf_valid 267 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 268 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 269 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 270 assert(!s0_vec_iss_select) // to be added 271 dontTouch(s0_super_ld_rep_select) 272 dontTouch(s0_ld_fast_rep_select) 273 dontTouch(s0_ld_rep_select) 274 dontTouch(s0_hw_prf_select) 275 dontTouch(s0_int_iss_select) 276 dontTouch(s0_vec_iss_select) 277 dontTouch(s0_l2l_fwd_select) 278 279 s0_valid := (s0_super_ld_rep_valid || 280 s0_ld_fast_rep_valid || 281 s0_ld_rep_valid || 282 s0_high_conf_prf_valid || 283 s0_int_iss_valid || 284 s0_vec_iss_valid || 285 s0_l2l_fwd_valid || 286 s0_low_conf_prf_valid) && io.dcache.req.ready && !s0_kill 287 288 // which is S0's out is ready and dcache is ready 289 val s0_try_ptr_chasing = s0_l2l_fwd_select 290 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.dcache.req.ready 291 val s0_ptr_chasing_vaddr = io.l2l_fwd_in.data(5, 0) +& io.ld_fast_imm(5, 0) 292 val s0_ptr_chasing_canceled = WireInit(false.B) 293 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 294 295 // prefetch related ctrl signal 296 val s0_prf = Wire(Bool()) 297 val s0_prf_rd = Wire(Bool()) 298 val s0_prf_wr = Wire(Bool()) 299 val s0_hw_prf = s0_hw_prf_select 300 301 // query DTLB 302 io.tlb.req.valid := s0_valid 303 io.tlb.req.bits.cmd := Mux(s0_prf, 304 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 305 TlbCmd.read 306 ) 307 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.prefetch_req.bits.paddr, s0_vaddr) 308 io.tlb.req.bits.size := LSUOpType.size(s0_uop.fuOpType) 309 io.tlb.req.bits.kill := s0_kill 310 io.tlb.req.bits.memidx.is_ld := true.B 311 io.tlb.req.bits.memidx.is_st := false.B 312 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 313 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 314 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 315 io.tlb.req.bits.debug.pc := s0_uop.pc 316 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 317 318 // query DCache 319 io.dcache.req.valid := s0_valid 320 io.dcache.req.bits.cmd := Mux(s0_prf_rd, 321 MemoryOpConstants.M_PFR, 322 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD) 323 ) 324 io.dcache.req.bits.vaddr := s0_vaddr 325 io.dcache.req.bits.mask := s0_mask 326 io.dcache.req.bits.data := DontCare 327 io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 328 io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 329 io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 330 io.dcache.req.bits.replayCarry := s0_rep_carry 331 io.dcache.req.bits.id := DontCare // TODO: update cache meta 332 333 // load flow priority mux 334 def fromNullSource() = { 335 s0_vaddr := 0.U 336 s0_mask := 0.U 337 s0_uop := 0.U.asTypeOf(new DynInst) 338 s0_try_l2l := false.B 339 s0_has_rob_entry := false.B 340 s0_sqIdx := 0.U.asTypeOf(new SqPtr) 341 s0_rsIdx := 0.U 342 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 343 s0_mshrid := 0.U 344 s0_isFirstIssue := false.B 345 s0_fast_rep := false.B 346 s0_ld_rep := false.B 347 s0_l2l_fwd := false.B 348 s0_prf := false.B 349 s0_prf_rd := false.B 350 s0_prf_wr := false.B 351 s0_sched_idx := 0.U 352 s0_deqPortIdx := 0.U 353 } 354 355 def fromFastReplaySource(src: LqWriteBundle) = { 356 s0_vaddr := src.vaddr 357 s0_mask := src.mask 358 s0_uop := src.uop 359 s0_try_l2l := false.B 360 s0_has_rob_entry := src.hasROBEntry 361 s0_sqIdx := src.uop.sqIdx 362 s0_rep_carry := src.rep_info.rep_carry 363 s0_mshrid := src.rep_info.mshr_id 364 s0_rsIdx := src.rsIdx 365 s0_isFirstIssue := false.B 366 s0_fast_rep := true.B 367 s0_ld_rep := src.isLoadReplay 368 s0_l2l_fwd := false.B 369 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 370 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 371 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 372 s0_sched_idx := src.schedIndex 373 s0_deqPortIdx := src.deqPortIdx 374 } 375 376 def fromNormalReplaySource(src: LsPipelineBundle) = { 377 s0_vaddr := src.vaddr 378 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 379 s0_uop := src.uop 380 s0_try_l2l := false.B 381 s0_has_rob_entry := true.B 382 s0_sqIdx := src.uop.sqIdx 383 s0_rsIdx := src.rsIdx 384 s0_rep_carry := src.replayCarry 385 s0_mshrid := src.mshrid 386 s0_isFirstIssue := false.B 387 s0_fast_rep := false.B 388 s0_ld_rep := true.B 389 s0_l2l_fwd := false.B 390 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 391 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 392 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 393 s0_sched_idx := src.schedIndex 394 s0_deqPortIdx := src.deqPortIdx 395 } 396 397 def fromPrefetchSource(src: L1PrefetchReq) = { 398 s0_vaddr := src.getVaddr() 399 s0_mask := 0.U 400 s0_uop := DontCare 401 s0_try_l2l := false.B 402 s0_has_rob_entry := false.B 403 s0_sqIdx := DontCare 404 s0_rsIdx := DontCare 405 s0_rep_carry := DontCare 406 s0_mshrid := DontCare 407 s0_isFirstIssue := false.B 408 s0_fast_rep := false.B 409 s0_ld_rep := false.B 410 s0_l2l_fwd := false.B 411 s0_prf := true.B 412 s0_prf_rd := !src.is_store 413 s0_prf_wr := src.is_store 414 s0_sched_idx := 0.U 415 s0_deqPortIdx := 0.U 416 } 417 418 def fromIntIssueSource(src: MemExuInput) = { 419 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 420 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 421 s0_uop := src.uop 422 s0_try_l2l := false.B 423 s0_has_rob_entry := true.B 424 s0_sqIdx := src.uop.sqIdx 425 s0_rsIdx := src.iqIdx 426 s0_rep_carry := DontCare 427 s0_mshrid := DontCare 428 s0_isFirstIssue := true.B 429 s0_fast_rep := false.B 430 s0_ld_rep := false.B 431 s0_l2l_fwd := false.B 432 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 433 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 434 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 435 s0_sched_idx := 0.U 436 s0_deqPortIdx := src.deqPortIdx 437 } 438 439 def fromVecIssueSource() = { 440 s0_vaddr := 0.U 441 s0_mask := 0.U 442 s0_uop := 0.U.asTypeOf(new DynInst) 443 s0_try_l2l := false.B 444 s0_has_rob_entry := false.B 445 s0_sqIdx := 0.U.asTypeOf(new SqPtr) 446 s0_rsIdx := 0.U 447 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 448 s0_mshrid := 0.U 449 s0_isFirstIssue := false.B 450 s0_fast_rep := false.B 451 s0_ld_rep := false.B 452 s0_l2l_fwd := false.B 453 s0_prf := false.B 454 s0_prf_rd := false.B 455 s0_prf_wr := false.B 456 s0_sched_idx := 0.U 457 s0_deqPortIdx := 0.U 458 } 459 460 def fromLoadToLoadSource(src: LoadToLoadIO) = { 461 s0_vaddr := Cat(io.l2l_fwd_in.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 462 s0_mask := genVWmask(Cat(s0_ptr_chasing_vaddr(3), 0.U(3.W)), LSUOpType.ld) 463 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 464 // Assume the pointer chasing is always ld. 465 s0_uop.fuOpType := LSUOpType.ld 466 s0_try_l2l := s0_l2l_fwd_select 467 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx and s0_deqPortIdx in S0 when trying pointchasing 468 // because these signals will be updated in S1 469 s0_has_rob_entry := false.B 470 s0_sqIdx := DontCare 471 s0_rsIdx := DontCare 472 s0_mshrid := DontCare 473 s0_rep_carry := DontCare 474 s0_isFirstIssue := true.B 475 s0_fast_rep := false.B 476 s0_ld_rep := false.B 477 s0_l2l_fwd := true.B 478 s0_prf := false.B 479 s0_prf_rd := false.B 480 s0_prf_wr := false.B 481 s0_sched_idx := 0.U 482 s0_deqPortIdx := 0.U 483 } 484 485 // set default 486 s0_uop := DontCare 487 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 488 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.fast_rep_in.bits) } 489 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 490 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.prefetch_req.bits) } 491 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.ldin.bits) } 492 .elsewhen (s0_vec_iss_select) { fromVecIssueSource() } 493 .otherwise { 494 if (EnableLoadToLoadForward) { 495 fromLoadToLoadSource(io.l2l_fwd_in) 496 } else { 497 fromNullSource() 498 } 499 } 500 501 // address align check 502 val s0_addr_aligned = LookupTree(s0_uop.fuOpType(1, 0), List( 503 "b00".U -> true.B, //b 504 "b01".U -> (s0_vaddr(0) === 0.U), //h 505 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 506 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 507 )) 508 509 // accept load flow if dcache ready (tlb is always ready) 510 // TODO: prefetch need writeback to loadQueueFlag 511 s0_out := DontCare 512 s0_out.rsIdx := s0_rsIdx 513 s0_out.vaddr := s0_vaddr 514 s0_out.mask := s0_mask 515 s0_out.uop := s0_uop 516 s0_out.isFirstIssue := s0_isFirstIssue 517 s0_out.hasROBEntry := s0_has_rob_entry 518 s0_out.isPrefetch := s0_prf 519 s0_out.isHWPrefetch := s0_hw_prf 520 s0_out.isFastReplay := s0_fast_rep 521 s0_out.isLoadReplay := s0_ld_rep 522 s0_out.isFastPath := s0_l2l_fwd 523 s0_out.mshrid := s0_mshrid 524 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned 525 s0_out.forward_tlDchannel := s0_super_ld_rep_select 526 when(io.tlb.req.valid && s0_isFirstIssue) { 527 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 528 }.otherwise{ 529 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 530 } 531 s0_out.schedIndex := s0_sched_idx 532 s0_out.deqPortIdx := s0_deqPortIdx 533 534 // load fast replay 535 io.fast_rep_in.ready := (s0_can_go && io.dcache.req.ready && s0_ld_fast_rep_ready) 536 537 // load flow source ready 538 // cache missed load has highest priority 539 // always accept cache missed load flow from load replay queue 540 io.replay.ready := (s0_can_go && io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 541 542 // accept load flow from rs when: 543 // 1) there is no lsq-replayed load 544 // 2) there is no fast replayed load 545 // 3) there is no high confidence prefetch request 546 io.ldin.ready := (s0_can_go && io.dcache.req.ready && s0_int_iss_ready) 547 548 // for hw prefetch load flow feedback, to be added later 549 // io.prefetch_in.ready := s0_hw_prf_select 550 551 // dcache replacement extra info 552 // TODO: should prefetch load update replacement? 553 io.dcache.replacementUpdated := Mux(s0_ld_rep_select, io.replay.bits.replacementUpdated, false.B) 554 555 XSDebug(io.dcache.req.fire, 556 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 557 ) 558 XSDebug(s0_valid, 559 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lId ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 560 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 561 562 // Pipeline 563 // -------------------------------------------------------------------------------- 564 // stage 1 565 // -------------------------------------------------------------------------------- 566 // TLB resp (send paddr to dcache) 567 val s1_valid = RegInit(false.B) 568 val s1_in = Wire(new LqWriteBundle) 569 val s1_out = Wire(new LqWriteBundle) 570 val s1_kill = Wire(Bool()) 571 val s1_can_go = s2_ready 572 val s1_fire = s1_valid && !s1_kill && s1_can_go 573 574 s1_ready := !s1_valid || s1_kill || s2_ready 575 when (s0_fire) { s1_valid := true.B } 576 .elsewhen (s1_fire) { s1_valid := false.B } 577 .elsewhen (s1_kill) { s1_valid := false.B } 578 s1_in := RegEnable(s0_out, s0_fire) 579 580 val s1_fast_rep_kill = RegEnable(io.fast_rep_in.bits.delayedLoadError, s0_fire) && s1_in.isFastReplay 581 val s1_l2l_fwd_kill = RegEnable(io.l2l_fwd_in.dly_ld_err, s0_fire) && s1_in.isFastPath 582 s1_kill := s1_l2l_fwd_kill || 583 s1_in.uop.robIdx.needFlush(io.redirect) || 584 RegEnable(s0_kill, false.B, io.ldin.valid || io.replay.valid || io.l2l_fwd_in.valid || io.fast_rep_in.valid) 585 586 val s1_vaddr_hi = Wire(UInt()) 587 val s1_vaddr_lo = Wire(UInt()) 588 val s1_vaddr = Wire(UInt()) 589 val s1_paddr_dup_lsu = Wire(UInt()) 590 val s1_paddr_dup_dcache = Wire(UInt()) 591 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 592 val s1_tlb_miss = io.tlb.resp.bits.miss 593 val s1_prf = s1_in.isPrefetch 594 val s1_hw_prf = s1_in.isHWPrefetch 595 val s1_sw_prf = s1_prf && !s1_hw_prf 596 val s1_tlb_memidx = io.tlb.resp.bits.memidx 597 598 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 599 s1_vaddr_lo := s1_in.vaddr(5, 0) 600 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 601 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 602 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 603 604 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_in.uop.lqIdx.value) { 605 // printf("load idx = %d\n", s1_tlb_memidx.idx) 606 s1_out.uop.debugInfo.tlbRespTime := GTimer() 607 } 608 609 io.tlb.req_kill := s1_kill || s1_fast_rep_kill 610 io.tlb.resp.ready := true.B 611 612 io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 613 io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 614 io.dcache.s1_kill := s1_kill || s1_fast_rep_kill || s1_tlb_miss || s1_exception 615 616 // store to load forwarding 617 io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf) 618 io.sbuffer.vaddr := s1_vaddr 619 io.sbuffer.paddr := s1_paddr_dup_lsu 620 io.sbuffer.uop := s1_in.uop 621 io.sbuffer.sqIdx := s1_in.uop.sqIdx 622 io.sbuffer.mask := s1_in.mask 623 io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 624 625 io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf) 626 io.lsq.forward.vaddr := s1_vaddr 627 io.lsq.forward.paddr := s1_paddr_dup_lsu 628 io.lsq.forward.uop := s1_in.uop 629 io.lsq.forward.sqIdx := s1_in.uop.sqIdx 630 io.lsq.forward.sqIdxMask := DontCare 631 io.lsq.forward.mask := s1_in.mask 632 io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 633 634 // st-ld violation query 635 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 636 io.stld_nuke_query(w).valid && // query valid 637 isAfter(s1_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 638 // TODO: Fix me when vector instruction 639 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 640 (s1_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 641 })).asUInt.orR && !s1_tlb_miss 642 // Generate forwardMaskFast to wake up insts earlier 643 val s1_fwd_mask_fast = ((~(io.lsq.forward.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt)).asUInt & s1_in.mask) === 0.U 644 645 s1_out := s1_in 646 s1_out.vaddr := s1_vaddr 647 s1_out.paddr := s1_paddr_dup_lsu 648 s1_out.tlbMiss := s1_tlb_miss 649 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 650 s1_out.rsIdx := s1_in.rsIdx 651 s1_out.rep_info.debug := s1_in.uop.debugInfo 652 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 653 s1_out.lateKill := s1_fast_rep_kill 654 s1_out.delayedLoadError := s1_l2l_fwd_kill || s1_fast_rep_kill 655 656 when (!s1_fast_rep_kill) { 657 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 658 // af & pf exception were modified 659 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 660 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 661 } .otherwise { 662 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B 663 s1_out.uop.exceptionVec(loadAccessFault) := s1_fast_rep_kill 664 } 665 666 // pointer chasing 667 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 668 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 669 val s1_fu_op_type_not_ld = WireInit(false.B) 670 val s1_not_fast_match = WireInit(false.B) 671 val s1_addr_mismatch = WireInit(false.B) 672 val s1_addr_misaligned = WireInit(false.B) 673 val s1_ptr_chasing_canceled = WireInit(false.B) 674 val s1_cancel_ptr_chasing = WireInit(false.B) 675 676 if (EnableLoadToLoadForward) { 677 // Sometimes, we need to cancel the load-load forwarding. 678 // These can be put at S0 if timing is bad at S1. 679 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 680 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 681 // Case 1: the address is not 64-bit aligned or the fuOpType is not LD 682 s1_addr_misaligned := s1_ptr_chasing_vaddr(2, 0).orR 683 s1_fu_op_type_not_ld := io.ldin.bits.uop.fuOpType =/= LSUOpType.ld 684 // Case 2: this is not a valid load-load pair 685 s1_not_fast_match := RegEnable(!io.ld_fast_match, s0_try_ptr_chasing) 686 // Case 3: this load-load uop is cancelled 687 s1_ptr_chasing_canceled := !io.ldin.valid 688 689 when (s1_try_ptr_chasing) { 690 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_fu_op_type_not_ld || s1_not_fast_match || s1_ptr_chasing_canceled 691 692 s1_in.uop := io.ldin.bits.uop 693 s1_in.rsIdx := io.ldin.bits.iqIdx 694 s1_in.isFirstIssue := io.ldin.bits.isFirstIssue 695 s1_in.deqPortIdx := io.ldin.bits.deqPortIdx 696 s1_vaddr_lo := Cat(s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 697 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 698 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 699 700 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 701 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 702 s1_in.uop.debugInfo.tlbRespTime := GTimer() 703 } 704 when (s1_cancel_ptr_chasing) { 705 s1_kill := true.B 706 }.otherwise { 707 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.replay.fire && !io.fast_rep_in.fire 708 when (s1_try_ptr_chasing) { 709 io.ldin.ready := true.B 710 } 711 } 712 } 713 714 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 715 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 716 // to enable load-load, sqIdxMask must be calculated based on ldin.uop 717 // If the timing here is not OK, load-load forwarding has to be disabled. 718 // Or we calculate sqIdxMask at RS?? 719 io.lsq.forward.sqIdxMask := s1_sqIdx_mask 720 if (EnableLoadToLoadForward) { 721 when (s1_try_ptr_chasing) { 722 io.lsq.forward.sqIdxMask := UIntToMask(io.ldin.bits.uop.sqIdx.value, StoreQueueSize) 723 } 724 } 725 726 io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel 727 io.forward_mshr.mshrid := s1_out.mshrid 728 io.forward_mshr.paddr := s1_out.paddr 729 730 XSDebug(s1_valid, 731 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 732 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 733 734 // Pipeline 735 // -------------------------------------------------------------------------------- 736 // stage 2 737 // -------------------------------------------------------------------------------- 738 // s2: DCache resp 739 val s2_valid = RegInit(false.B) 740 val s2_in = Wire(new LqWriteBundle) 741 val s2_out = Wire(new LqWriteBundle) 742 val s2_kill = Wire(Bool()) 743 val s2_can_go = s3_ready 744 val s2_fire = s2_valid && !s2_kill && s2_can_go 745 746 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 747 s2_ready := !s2_valid || s2_kill || s3_ready 748 when (s1_fire) { s2_valid := true.B } 749 .elsewhen (s2_fire) { s2_valid := false.B } 750 .elsewhen (s2_kill) { s2_valid := false.B } 751 s2_in := RegEnable(s1_out, s1_fire) 752 753 val s2_pmp = WireInit(io.pmp) 754 val s2_static_pm = RegNext(io.tlb.resp.bits.static_pm) 755 when (s2_static_pm.valid) { 756 s2_pmp.ld := false.B 757 s2_pmp.st := false.B 758 s2_pmp.instr := false.B 759 s2_pmp.mmio := s2_static_pm.bits 760 } 761 val s2_prf = s2_in.isPrefetch 762 val s2_hw_prf = s2_in.isHWPrefetch 763 764 // exception that may cause load addr to be invalid / illegal 765 // if such exception happen, that inst and its exception info 766 // will be force writebacked to rob 767 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 768 when (!s2_in.lateKill) { 769 s2_exception_vec(loadAccessFault) := s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld 770 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 771 when (s2_prf || s2_in.tlbMiss) { 772 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 773 } 774 } 775 val s2_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR 776 777 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 778 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.forward_mshr.forward() 779 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 780 val s2_cache_hit = io.dcache.s2_hit || s2_fwd_frm_d_chan_or_mshr 781 782 // writeback access fault caused by ecc error / bus error 783 // * ecc data error is slow to generate, so we will not use it until load stage 3 784 // * in load stage 3, an extra signal io.load_error will be used to 785 val s2_actually_mmio = s2_pmp.mmio 786 val s2_mmio = !s2_prf && s2_actually_mmio && !s2_exception && !s2_in.tlbMiss 787 val s2_full_fwd = Wire(Bool()) 788 val s2_cache_miss = io.dcache.resp.bits.miss && !s2_fwd_frm_d_chan_or_mshr 789 val s2_mq_nack = io.dcache.s2_mq_nack 790 val s2_bank_conflict = io.dcache.s2_bank_conflict && !io.dcache.resp.bits.miss && !s2_full_fwd 791 val s2_wpu_pred_fail = io.dcache.s2_wpu_pred_fail 792 val s2_cache_rep = s2_bank_conflict || s2_wpu_pred_fail 793 val s2_cache_handled = io.dcache.resp.bits.handled 794 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && io.dcache.resp.bits.tag_error 795 val s2_fwd_fail = io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid 796 val s2_mem_amb = s2_in.uop.storeSetHit && io.lsq.forward.addrInvalid && !s2_mmio && !s2_prf 797 val s2_data_inv = io.lsq.forward.dataInvalid && !s2_exception 798 val s2_dcache_kill = s2_pmp.ld || s2_pmp.mmio 799 val s2_troublem = !s2_exception && !s2_mmio && !s2_prf && !s2_in.lateKill 800 801 io.dcache.resp.ready := true.B 802 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_mmio || s2_prf) 803 assert(!(s2_valid && (s2_dcache_should_resp && !io.dcache.resp.valid)), "DCache response got lost") 804 805 // st-ld violation query 806 // NeedFastRecovery Valid when 807 // 1. Fast recovery query request Valid. 808 // 2. Load instruction is younger than requestors(store instructions). 809 // 3. Physical address match. 810 // 4. Data contains. 811 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 812 io.stld_nuke_query(w).valid && // query valid 813 isAfter(s2_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 814 // TODO: Fix me when vector instruction 815 (s2_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 816 (s2_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 817 })).asUInt.orR || s2_in.rep_info.nuke 818 819 // fast replay require 820 val s2_fast_rep = (s2_nuke || (!s2_mem_amb && !s2_in.tlbMiss && s2_cache_rep)) && s2_troublem 821 822 // need allocate new entry 823 val s2_can_query = !s2_in.tlbMiss && 824 !s2_mem_amb && 825 !s2_fast_rep && 826 !s2_in.rep_info.mem_amb && 827 s2_troublem 828 829 val s2_data_fwded = s2_cache_miss && (s2_full_fwd || s2_cache_tag_error) 830 831 // ld-ld violation require 832 io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 833 io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 834 io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 835 io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 836 io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd, true.B, !s2_cache_miss) && !s2_cache_rep 837 838 // st-ld violation require 839 io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 840 io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 841 io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 842 io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 843 io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd, true.B, !s2_cache_miss) && !s2_cache_rep 844 845 val s2_rar_nack = io.lsq.ldld_nuke_query.req.valid && !io.lsq.ldld_nuke_query.req.ready 846 val s2_raw_nack = io.lsq.stld_nuke_query.req.valid && !io.lsq.stld_nuke_query.req.ready 847 848 // merge forward result 849 // lsq has higher priority than sbuffer 850 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 851 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 852 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.lsq.forward.dataInvalid 853 // generate XLEN/8 Muxs 854 for (i <- 0 until VLEN / 8) { 855 s2_fwd_mask(i) := io.lsq.forward.forwardMask(i) || io.sbuffer.forwardMask(i) 856 s2_fwd_data(i) := Mux(io.lsq.forward.forwardMask(i), io.lsq.forward.forwardData(i), io.sbuffer.forwardData(i)) 857 } 858 859 XSDebug(s2_fire, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 860 s2_in.uop.pc, 861 io.lsq.forward.forwardData.asUInt, io.lsq.forward.forwardMask.asUInt, 862 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 863 ) 864 865 // 866 s2_out := s2_in 867 s2_out.data := 0.U // data will be generated in load s3 868 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception 869 s2_out.mmio := s2_mmio 870 s2_out.uop.flushPipe := false.B // io.fast_uop.valid && s2_mmio 871 s2_out.uop.exceptionVec := s2_exception_vec 872 s2_out.forwardMask := s2_fwd_mask 873 s2_out.forwardData := s2_fwd_data 874 s2_out.handledByMSHR := s2_cache_handled 875 s2_out.miss := s2_cache_miss && !s2_full_fwd && s2_troublem 876 s2_out.feedbacked := io.feedback_fast.valid 877 878 // Generate replay signal caused by: 879 // * st-ld violation check 880 // * tlb miss 881 // * dcache replay 882 // * forward data invalid 883 // * dcache miss 884 s2_out.rep_info.tlb_miss := s2_in.tlbMiss 885 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 886 s2_out.rep_info.nuke := s2_nuke && s2_troublem 887 s2_out.rep_info.fwd_fail := s2_data_inv && s2_troublem 888 s2_out.rep_info.dcache_rep := s2_cache_rep && s2_troublem 889 s2_out.rep_info.dcache_miss := s2_out.miss 890 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 891 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 892 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 893 s2_out.rep_info.full_fwd := s2_data_fwded 894 s2_out.rep_info.data_inv_sq_idx := io.lsq.forward.dataInvalidSqIdx 895 s2_out.rep_info.addr_inv_sq_idx := io.lsq.forward.addrInvalidSqIdx 896 s2_out.rep_info.rep_carry := io.dcache.resp.bits.replayCarry 897 s2_out.rep_info.mshr_id := io.dcache.resp.bits.mshr_id 898 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 899 s2_out.rep_info.debug := s2_in.uop.debugInfo 900 901 // if forward fail, replay this inst from fetch 902 val debug_fwd_fail_rep = s2_fwd_fail && !s2_mmio && !s2_prf && !s2_in.tlbMiss 903 // if ld-ld violation is detected, replay from this inst from fetch 904 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_mmio && !s2_is_prefetch && !s2_in.tlbMiss 905 // io.out.bits.uop.replayInst := false.B 906 907 // to be removed 908 io.feedback_fast.valid := s2_valid && // inst is valid 909 !s2_in.isLoadReplay && // already feedbacked 910 io.lq_rep_full && // LoadQueueReplay is full 911 s2_out.rep_info.need_rep && // need replay 912 !s2_exception && // no exception is triggered 913 !s2_hw_prf // not hardware prefetch 914 io.feedback_fast.bits.hit := false.B 915 io.feedback_fast.bits.flushState := s2_in.ptwBack 916 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 917 io.feedback_fast.bits.sourceType := RSFeedbackType.lrqFull 918 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 919 920 io.ldCancel.ld1Cancel.valid := s2_valid && ( 921 (s2_out.rep_info.need_rep && s2_out.isFirstIssue) || // exe fail and issued from IQ 922 s2_mmio // is mmio 923 ) 924 io.ldCancel.ld1Cancel.bits := s2_out.deqPortIdx 925 926 // fast wakeup 927 io.fast_uop.valid := RegNext( 928 !io.dcache.s1_disable_fast_wakeup && 929 s1_valid && 930 !s1_kill && 931 !s1_fast_rep_kill && 932 !io.tlb.resp.bits.fast_miss && 933 !io.lsq.forward.dataInvalidFast 934 ) && (s2_valid && !io.feedback_fast.valid && !s2_out.rep_info.need_rep && !s2_mmio) 935 io.fast_uop.bits := RegNext(s1_out.uop) 936 937 // 938 io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, s1_fire) 939 io.prefetch_train.valid := s2_valid && !s2_in.mmio && !s2_in.tlbMiss 940 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 941 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss 942 io.prefetch_train.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 943 io.prefetch_train.bits.meta_access := io.dcache.resp.bits.meta_access 944 if (env.FPGAPlatform){ 945 io.dcache.s0_pc := DontCare 946 io.dcache.s1_pc := DontCare 947 io.dcache.s2_pc := DontCare 948 }else{ 949 io.dcache.s0_pc := s0_out.uop.pc 950 io.dcache.s1_pc := s1_out.uop.pc 951 io.dcache.s2_pc := s2_out.uop.pc 952 } 953 io.dcache.s2_kill := s2_pmp.ld || s2_pmp.mmio || s2_kill 954 955 val s1_ld_left_fire = s1_valid && !s1_kill && !s1_fast_rep_kill && s2_ready 956 val s2_ld_valid_dup = RegInit(0.U(6.W)) 957 s2_ld_valid_dup := 0x0.U(6.W) 958 when (s1_ld_left_fire && !s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x3f.U(6.W) } 959 when (s1_kill || s1_fast_rep_kill || s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x0.U(6.W) } 960 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch))) 961 962 // Pipeline 963 // -------------------------------------------------------------------------------- 964 // stage 3 965 // -------------------------------------------------------------------------------- 966 // writeback and update load queue 967 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 968 val s3_in = RegEnable(s2_out, s2_fire) 969 val s3_out = Wire(Valid(new MemExuOutput)) 970 val s3_cache_rep = RegEnable(s2_cache_rep && s2_troublem, s2_fire) 971 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 972 val s3_fast_rep = Wire(Bool()) 973 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 974 s3_ready := !s3_valid || s3_kill || io.ldout.ready 975 976 // s3 load fast replay 977 io.fast_rep_out.valid := s3_valid && s3_fast_rep && !s3_in.uop.robIdx.needFlush(io.redirect) 978 io.fast_rep_out.bits := s3_in 979 980 io.lsq.ldin.valid := s3_valid && (!s3_fast_rep || !io.fast_rep_out.ready) && !s3_in.feedbacked && !s3_in.lateKill 981 io.lsq.ldin.bits := s3_in 982 983 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 984 io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 985 io.lsq.ldin.bits.replacementUpdated := io.dcache.resp.bits.replacementUpdated 986 987 val s3_dly_ld_err = 988 if (EnableAccurateLoadError) { 989 (s3_in.delayedLoadError || io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 990 } else { 991 WireInit(false.B) 992 } 993 io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 994 io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 995 io.lsq.ldin.bits.dcacheRequireReplay := s3_cache_rep 996 997 val s3_vp_match_fail = RegNext(io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid) 998 val s3_ldld_rep_inst = 999 io.lsq.ldld_nuke_query.resp.valid && 1000 io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1001 RegNext(io.csrCtrl.ldld_vio_check_enable) 1002 1003 val s3_rep_info = s3_in.rep_info 1004 val s3_rep_frm_fetch = s3_vp_match_fail || s3_ldld_rep_inst 1005 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1006 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_MA) || 1007 s3_sel_rep_cause(LoadReplayCauses.C_TM) || 1008 s3_sel_rep_cause(LoadReplayCauses.C_NK) 1009 1010 val s3_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR 1011 when ((s3_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1012 io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1013 } .otherwise { 1014 io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1015 } 1016 1017 // Int load, if hit, will be writebacked at s2 1018 s3_out.valid := s3_valid && !io.lsq.ldin.bits.rep_info.need_rep && !s3_in.mmio && !s3_in.lateKill 1019 s3_out.bits.uop := s3_in.uop 1020 s3_out.bits.uop.exceptionVec(loadAccessFault) := s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault) 1021 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1022 s3_out.bits.data := s3_in.data 1023 s3_out.bits.debug.isMMIO := s3_in.mmio 1024 s3_out.bits.debug.isPerfCnt := false.B 1025 s3_out.bits.debug.paddr := s3_in.paddr 1026 s3_out.bits.debug.vaddr := s3_in.vaddr 1027 1028 when (s3_force_rep) { 1029 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1030 } 1031 1032 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1033 1034 io.lsq.ldin.bits.uop := s3_out.bits.uop 1035 1036 val s3_revoke = s3_exception || io.lsq.ldin.bits.rep_info.need_rep 1037 io.lsq.ldld_nuke_query.revoke := s3_revoke 1038 io.lsq.stld_nuke_query.revoke := s3_revoke 1039 1040 // feedback slow 1041 s3_fast_rep := (RegNext(s2_fast_rep) || 1042 (s3_in.rep_info.dcache_miss && io.l2_hint.valid && io.l2_hint.bits.sourceId === s3_in.rep_info.mshr_id)) && 1043 !s3_in.feedbacked && 1044 !s3_in.lateKill && 1045 !s3_rep_frm_fetch && 1046 !s3_exception 1047 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.fast_rep_out.ready) && !s3_in.feedbacked 1048 1049 // 1050 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting 1051 io.feedback_slow.bits.hit := !io.lsq.ldin.bits.rep_info.need_rep || io.lsq.ldin.ready 1052 io.feedback_slow.bits.flushState := s3_in.ptwBack 1053 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1054 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1055 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1056 1057 io.ldCancel.ld2Cancel.valid := s3_valid && ( 1058 (io.lsq.ldin.bits.rep_info.need_rep && s3_in.isFirstIssue) || 1059 s3_in.mmio 1060 ) 1061 io.ldCancel.ld2Cancel.bits := s3_in.deqPortIdx 1062 1063 val s3_ld_wb_meta = Mux(s3_out.valid, s3_out.bits, io.lsq.uncache.bits) 1064 // data from load queue refill 1065 val s3_ld_raw_data_frm_uncache = io.lsq.ld_raw_data 1066 val s3_merged_data_frm_uncache = s3_ld_raw_data_frm_uncache.mergedData() 1067 val s3_picked_data_frm_uncache = LookupTree(s3_ld_raw_data_frm_uncache.addrOffset, List( 1068 "b000".U -> s3_merged_data_frm_uncache(63, 0), 1069 "b001".U -> s3_merged_data_frm_uncache(63, 8), 1070 "b010".U -> s3_merged_data_frm_uncache(63, 16), 1071 "b011".U -> s3_merged_data_frm_uncache(63, 24), 1072 "b100".U -> s3_merged_data_frm_uncache(63, 32), 1073 "b101".U -> s3_merged_data_frm_uncache(63, 40), 1074 "b110".U -> s3_merged_data_frm_uncache(63, 48), 1075 "b111".U -> s3_merged_data_frm_uncache(63, 56) 1076 )) 1077 val s3_ld_data_frm_uncache = rdataHelper(s3_ld_raw_data_frm_uncache.uop, s3_picked_data_frm_uncache) 1078 1079 // data from dcache hit 1080 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1081 s3_ld_raw_data_frm_cache.respDcacheData := io.dcache.resp.bits.data_delayed 1082 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1083 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1084 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1085 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1086 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, s2_valid) 1087 s3_ld_raw_data_frm_cache.forwardData_D := RegEnable(s2_fwd_data_frm_d_chan, s2_valid) 1088 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, s2_valid) 1089 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1090 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, s2_valid) 1091 1092 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1093 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1094 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1095 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1096 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1097 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1098 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1099 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1100 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1101 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1102 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1103 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1104 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1105 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1106 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1107 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1108 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1109 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1110 )) 1111 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1112 1113 // FIXME: add 1 cycle delay ? 1114 io.lsq.uncache.ready := !s3_out.valid 1115 io.ldout.bits := s3_ld_wb_meta 1116 io.ldout.bits.data := Mux(s3_out.valid, s3_ld_data_frm_cache, s3_ld_data_frm_uncache) 1117 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) || 1118 io.lsq.uncache.valid && !io.lsq.uncache.bits.uop.robIdx.needFlush(io.redirect) && !s3_out.valid 1119 1120 1121 // fast load to load forward 1122 io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill // for debug only 1123 io.l2l_fwd_out.data := Mux(s3_ld_raw_data_frm_cache.addrOffset(3), s3_merged_data_frm_cache(127, 64), s3_merged_data_frm_cache(63, 0)) // load to load is for ld only 1124 io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1125 1126 // trigger 1127 val last_valid_data = RegNext(RegEnable(io.ldout.bits.data, io.ldout.fire)) 1128 val hit_ld_addr_trig_hit_vec = Wire(Vec(3, Bool())) 1129 val lq_ld_addr_trig_hit_vec = io.lsq.trigger.lqLoadAddrTriggerHitVec 1130 (0 until 3).map{i => { 1131 val tdata2 = RegNext(io.trigger(i).tdata2) 1132 val matchType = RegNext(io.trigger(i).matchType) 1133 val tEnable = RegNext(io.trigger(i).tEnable) 1134 1135 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s2_out.vaddr), tdata2, matchType, tEnable) 1136 io.trigger(i).addrHit := Mux(s3_out.valid, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1137 io.trigger(i).lastDataHit := TriggerCmp(last_valid_data, tdata2, matchType, tEnable) 1138 }} 1139 io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1140 1141 // FIXME: please move this part to LoadQueueReplay 1142 io.debug_ls := DontCare 1143 1144 // Topdown 1145 io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1146 io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1147 io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1148 io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1149 io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1150 io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1151 1152 // perf cnt 1153 XSPerfAccumulate("s0_in_valid", io.ldin.valid) 1154 XSPerfAccumulate("s0_in_block", io.ldin.valid && !io.ldin.fire) 1155 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1156 XSPerfAccumulate("s0_lsq_fire_first_issue", io.replay.fire) 1157 XSPerfAccumulate("s0_ldu_fire_first_issue", io.ldin.fire && s0_isFirstIssue) 1158 XSPerfAccumulate("s0_fast_replay_issue", io.fast_rep_in.fire) 1159 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1160 XSPerfAccumulate("s0_stall_dcache", s0_valid && !io.dcache.req.ready) 1161 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12)) 1162 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12)) 1163 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1164 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1165 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1166 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1167 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1168 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.prefetch_req.valid && !s0_hw_prf_select) 1169 XSPerfAccumulate("s0_hardware_prefetch_total", io.prefetch_req.valid) 1170 1171 XSPerfAccumulate("s1_in_valid", s1_valid) 1172 XSPerfAccumulate("s1_in_fire", s1_fire) 1173 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1174 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1175 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1176 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1177 1178 XSPerfAccumulate("s2_in_valid", s2_valid) 1179 XSPerfAccumulate("s2_in_fire", s2_fire) 1180 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1181 XSPerfAccumulate("s2_dcache_miss", s2_fire && s2_cache_miss) 1182 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && s2_cache_miss && s2_in.isFirstIssue) 1183 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1184 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_cache_miss && s2_full_fwd) 1185 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1186 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1187 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && s2_cache_rep) // ignore prefetch for mshr full / miss req port conflict 1188 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && s2_cache_miss) // prefetch req miss in l1 1189 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !s2_cache_miss) // prefetch req hit in l1 1190 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && s2_cache_miss && !s2_cache_rep) // prefetch a missed line in l1, and l1 accepted it 1191 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fwd_frm_d_chan && s2_fwd_data_valid) 1192 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fwd_frm_mshr && s2_fwd_data_valid) 1193 1194 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1195 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1196 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1197 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1198 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1199 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1200 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1201 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1202 1203 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1204 // hardware performance counter 1205 val perfEvents = Seq( 1206 ("load_s0_in_fire ", s0_fire ), 1207 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1208 ("stall_dcache ", s0_valid && s0_can_go && !io.dcache.req.ready ), 1209 ("load_s1_in_fire ", s0_fire ), 1210 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1211 ("load_s2_in_fire ", s1_fire ), 1212 ("load_s2_dcache_miss ", s2_fire && io.dcache.resp.bits.miss ), 1213 ) 1214 generatePerfEvent() 1215 1216 when(io.ldout.fire){ 1217 XSDebug("ldout %x\n", io.ldout.bits.uop.pc) 1218 } 1219 // end 1220}