1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val loadDataForwarded = Output(Bool()) 16 val forward = new LoadForwardQueryIO 17} 18 19// Load Pipeline Stage 0 20// Generate addr, use addr to query DCache and DTLB 21class LoadUnit_S0 extends XSModule { 22 val io = IO(new Bundle() { 23 val in = Flipped(Decoupled(new ExuInput)) 24 val out = Decoupled(new LsPipelineBundle) 25 val dtlbReq = DecoupledIO(new TlbReq) 26 val dcacheReq = DecoupledIO(new DCacheWordReq) 27 }) 28 29 val s0_uop = io.in.bits.uop 30 val s0_vaddr_old = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN) 31 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 32 val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 33 val s0_vaddr_hi = Mux(imm12(11), 34 Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)), 35 Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12)) 36 ) 37 val s0_vaddr = Cat(s0_vaddr_hi, s0_vaddr_lo(11,0)) 38 when(io.in.fire() && s0_vaddr(VAddrBits-1,0) =/= (io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN))(VAddrBits-1,0)){ 39 printf("s0_vaddr %x s0_vaddr_old %x\n", s0_vaddr, s0_vaddr_old(VAddrBits-1,0)) 40 } 41 val s0_mask = genWmask(s0_vaddr_lo, s0_uop.ctrl.fuOpType(1,0)) 42 43 // query DTLB 44 io.dtlbReq.valid := io.in.valid 45 io.dtlbReq.bits.vaddr := s0_vaddr 46 io.dtlbReq.bits.cmd := TlbCmd.read 47 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 48 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 49 50 // query DCache 51 io.dcacheReq.valid := io.in.valid 52 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 53 io.dcacheReq.bits.addr := s0_vaddr 54 io.dcacheReq.bits.mask := s0_mask 55 io.dcacheReq.bits.data := DontCare 56 57 // TODO: update cache meta 58 io.dcacheReq.bits.id := DontCare 59 60 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 61 "b00".U -> true.B, //b 62 "b01".U -> (s0_vaddr(0) === 0.U), //h 63 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 64 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 65 )) 66 67 io.out.valid := io.in.valid && io.dcacheReq.ready 68 69 io.out.bits := DontCare 70 io.out.bits.vaddr := s0_vaddr 71 io.out.bits.mask := s0_mask 72 io.out.bits.uop := s0_uop 73 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 74 75 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 76 77 XSDebug(io.dcacheReq.fire(), 78 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 79 ) 80} 81 82 83// Load Pipeline Stage 1 84// TLB resp (send paddr to dcache) 85class LoadUnit_S1 extends XSModule { 86 val io = IO(new Bundle() { 87 val in = Flipped(Decoupled(new LsPipelineBundle)) 88 val out = Decoupled(new LsPipelineBundle) 89 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 90 val dcachePAddr = Output(UInt(PAddrBits.W)) 91 val dcacheKill = Output(Bool()) 92 val sbuffer = new LoadForwardQueryIO 93 val lsq = new LoadForwardQueryIO 94 }) 95 96 val s1_uop = io.in.bits.uop 97 val s1_paddr = io.dtlbResp.bits.paddr 98 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 99 val s1_tlb_miss = io.dtlbResp.bits.miss 100 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 101 val s1_mask = io.in.bits.mask 102 103 io.out.bits := io.in.bits // forwardXX field will be updated in s1 104 105 io.dtlbResp.ready := true.B 106 107 // TOOD: PMA check 108 io.dcachePAddr := s1_paddr 109 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 110 111 // load forward query datapath 112 io.sbuffer.valid := io.in.valid 113 io.sbuffer.paddr := s1_paddr 114 io.sbuffer.uop := s1_uop 115 io.sbuffer.sqIdx := s1_uop.sqIdx 116 io.sbuffer.mask := s1_mask 117 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 118 119 io.lsq.valid := io.in.valid 120 io.lsq.paddr := s1_paddr 121 io.lsq.uop := s1_uop 122 io.lsq.sqIdx := s1_uop.sqIdx 123 io.lsq.mask := s1_mask 124 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 125 126 io.out.valid := io.in.valid// && !s1_tlb_miss 127 io.out.bits.paddr := s1_paddr 128 io.out.bits.mmio := s1_mmio && !s1_exception 129 io.out.bits.tlbMiss := s1_tlb_miss 130 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 131 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 132 133 io.in.ready := !io.in.valid || io.out.ready 134 135} 136 137 138// Load Pipeline Stage 2 139// DCache resp 140class LoadUnit_S2 extends XSModule with HasLoadHelper { 141 val io = IO(new Bundle() { 142 val in = Flipped(Decoupled(new LsPipelineBundle)) 143 val out = Decoupled(new LsPipelineBundle) 144 val tlbFeedback = ValidIO(new TlbFeedback) 145 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 146 val lsq = new LoadForwardQueryIO 147 val sbuffer = new LoadForwardQueryIO 148 val dataForwarded = Output(Bool()) 149 }) 150 151 val s2_uop = io.in.bits.uop 152 val s2_mask = io.in.bits.mask 153 val s2_paddr = io.in.bits.paddr 154 val s2_tlb_miss = io.in.bits.tlbMiss 155 val s2_mmio = io.in.bits.mmio 156 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 157 val s2_cache_miss = io.dcacheResp.bits.miss 158 val s2_cache_replay = io.dcacheResp.bits.replay 159 160 io.dcacheResp.ready := true.B 161 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 162 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 163 164 // feedback tlb result to RS 165 io.tlbFeedback.valid := io.in.valid 166 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 167 io.tlbFeedback.bits.roqIdx := s2_uop.roqIdx 168 169 val forwardMask = io.out.bits.forwardMask 170 val forwardData = io.out.bits.forwardData 171 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 172 173 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 174 s2_uop.cf.pc, 175 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 176 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 177 ) 178 179 // data merge 180 val rdata = VecInit((0 until XLEN / 8).map(j => 181 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 182 val rdataSel = LookupTree(s2_paddr(2, 0), List( 183 "b000".U -> rdata(63, 0), 184 "b001".U -> rdata(63, 8), 185 "b010".U -> rdata(63, 16), 186 "b011".U -> rdata(63, 24), 187 "b100".U -> rdata(63, 32), 188 "b101".U -> rdata(63, 40), 189 "b110".U -> rdata(63, 48), 190 "b111".U -> rdata(63, 56) 191 )) 192 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 193 194 // TODO: ECC check 195 196 io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 197 // Inst will be canceled in store queue / lsq, 198 // so we do not need to care about flush in load / store unit's out.valid 199 io.out.bits := io.in.bits 200 io.out.bits.data := rdataPartialLoad 201 // when exception occurs, set it to not miss and let it write back to roq (via int port) 202 io.out.bits.miss := s2_cache_miss && !s2_exception 203 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 204 io.out.bits.mmio := s2_mmio 205 206 // For timing reasons, we can not let 207 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 208 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 209 // and dcache query is no longer needed. 210 // Such inst will be writebacked from load queue. 211 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception 212 213 io.in.ready := io.out.ready || !io.in.valid 214 215 // merge forward result 216 // lsq has higher priority than sbuffer 217 io.lsq := DontCare 218 io.sbuffer := DontCare 219 // generate XLEN/8 Muxs 220 for (i <- 0 until XLEN / 8) { 221 when (io.sbuffer.forwardMask(i)) { 222 io.out.bits.forwardMask(i) := true.B 223 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 224 } 225 when (io.lsq.forwardMask(i)) { 226 io.out.bits.forwardMask(i) := true.B 227 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 228 } 229 } 230 231 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 232 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 233 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 234 ) 235} 236 237class LoadUnit extends XSModule with HasLoadHelper { 238 val io = IO(new Bundle() { 239 val ldin = Flipped(Decoupled(new ExuInput)) 240 val ldout = Decoupled(new ExuOutput) 241 val fpout = Decoupled(new ExuOutput) 242 val redirect = Flipped(ValidIO(new Redirect)) 243 val tlbFeedback = ValidIO(new TlbFeedback) 244 val dcache = new DCacheLoadIO 245 val dtlb = new TlbRequestIO() 246 val sbuffer = new LoadForwardQueryIO 247 val lsq = new LoadToLsqIO 248 }) 249 250 val load_s0 = Module(new LoadUnit_S0) 251 val load_s1 = Module(new LoadUnit_S1) 252 val load_s2 = Module(new LoadUnit_S2) 253 254 load_s0.io.in <> io.ldin 255 load_s0.io.dtlbReq <> io.dtlb.req 256 load_s0.io.dcacheReq <> io.dcache.req 257 258 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 259 260 load_s1.io.dtlbResp <> io.dtlb.resp 261 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 262 io.dcache.s1_kill <> load_s1.io.dcacheKill 263 load_s1.io.sbuffer <> io.sbuffer 264 load_s1.io.lsq <> io.lsq.forward 265 266 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 267 268 load_s2.io.tlbFeedback <> io.tlbFeedback 269 load_s2.io.dcacheResp <> io.dcache.resp 270 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 271 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 272 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 273 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 274 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 275 276 // use s2_hit_way to select data received in s1 277 load_s2.io.dcacheResp.bits.data := Mux1H(io.dcache.s2_hit_way, RegNext(io.dcache.s1_data)) 278 assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 279 280 XSDebug(load_s0.io.out.valid, 281 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 282 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 283 XSDebug(load_s1.io.out.valid, 284 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 285 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 286 287 // writeback to LSQ 288 // Current dcache use MSHR 289 // Load queue will be updated at s2 for both hit/miss int/fp load 290 io.lsq.loadIn.valid := load_s2.io.out.valid 291 io.lsq.loadIn.bits := load_s2.io.out.bits 292 293 // write to rob and writeback bus 294 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 295 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 296 297 // Int load, if hit, will be writebacked at s2 298 val intHitLoadOut = Wire(Valid(new ExuOutput)) 299 intHitLoadOut.valid := s2_wb_valid && !load_s2.io.out.bits.uop.ctrl.fpWen 300 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 301 intHitLoadOut.bits.data := load_s2.io.out.bits.data 302 intHitLoadOut.bits.redirectValid := false.B 303 intHitLoadOut.bits.redirect := DontCare 304 intHitLoadOut.bits.brUpdate := DontCare 305 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 306 intHitLoadOut.bits.debug.isPerfCnt := false.B 307 intHitLoadOut.bits.fflags := DontCare 308 309 load_s2.io.out.ready := true.B 310 311 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 312 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 313 314 // Fp load, if hit, will be send to recoder at s2, then it will be recoded & writebacked at s3 315 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 316 fpHitLoadOut.valid := s2_wb_valid && load_s2.io.out.bits.uop.ctrl.fpWen 317 fpHitLoadOut.bits := intHitLoadOut.bits 318 319 val fpLoadOut = Wire(Valid(new ExuOutput)) 320 fpLoadOut.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 321 fpLoadOut.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 322 323 val fpLoadOutReg = RegNext(fpLoadOut) 324 io.fpout.bits := fpLoadOutReg.bits 325 io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode 326 io.fpout.valid := RegNext(fpLoadOut.valid) 327 328 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 329 330 when(io.ldout.fire()){ 331 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 332 } 333 334 when(io.fpout.fire()){ 335 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 336 } 337} 338