1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val loadDataForwarded = Output(Bool()) 16 val needReplayFromRS = Output(Bool()) 17 val forward = new MaskedLoadForwardQueryIO 18} 19 20// Load Pipeline Stage 0 21// Generate addr, use addr to query DCache and DTLB 22class LoadUnit_S0 extends XSModule { 23 val io = IO(new Bundle() { 24 val in = Flipped(Decoupled(new ExuInput)) 25 val out = Decoupled(new LsPipelineBundle) 26 val dtlbReq = DecoupledIO(new TlbReq) 27 val dcacheReq = DecoupledIO(new DCacheWordReq) 28 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 29 }) 30 31 val s0_uop = io.in.bits.uop 32 val s0_vaddr = io.in.bits.src1 + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 33 // val s0_vaddr_old = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN) 34 // val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 35 // val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 36 // val s0_vaddr_hi = Mux(imm12(11), 37 // Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12)), 38 // Mux((s0_vaddr_lo(12)), io.in.bits.src1(VAddrBits-1, 12)+1.U, io.in.bits.src1(VAddrBits-1, 12)) 39 // ) 40 // val s0_vaddr = Cat(s0_vaddr_hi, s0_vaddr_lo(11,0)) 41 // when(io.in.fire() && s0_vaddr(VAddrBits-1,0) =/= (io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN))(VAddrBits-1,0)){ 42 // printf("s0_vaddr %x s0_vaddr_old %x\n", s0_vaddr, s0_vaddr_old(VAddrBits-1,0)) 43 // } 44 // val s0_mask = genWmask(s0_vaddr_lo, s0_uop.ctrl.fuOpType(1,0)) 45 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 46 47 // query DTLB 48 io.dtlbReq.valid := io.in.valid 49 io.dtlbReq.bits.vaddr := s0_vaddr 50 io.dtlbReq.bits.cmd := TlbCmd.read 51 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 52 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 53 54 // query DCache 55 io.dcacheReq.valid := io.in.valid 56 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 57 io.dcacheReq.bits.addr := s0_vaddr 58 io.dcacheReq.bits.mask := s0_mask 59 io.dcacheReq.bits.data := DontCare 60 61 // TODO: update cache meta 62 io.dcacheReq.bits.id := DontCare 63 64 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 65 "b00".U -> true.B, //b 66 "b01".U -> (s0_vaddr(0) === 0.U), //h 67 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 68 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 69 )) 70 71 io.out.valid := io.in.valid && io.dcacheReq.ready 72 73 io.out.bits := DontCare 74 io.out.bits.vaddr := s0_vaddr 75 io.out.bits.mask := s0_mask 76 io.out.bits.uop := s0_uop 77 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 78 io.out.bits.rsIdx := io.rsIdx 79 80 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 81 82 XSDebug(io.dcacheReq.fire(), 83 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 84 ) 85} 86 87 88// Load Pipeline Stage 1 89// TLB resp (send paddr to dcache) 90class LoadUnit_S1 extends XSModule { 91 val io = IO(new Bundle() { 92 val in = Flipped(Decoupled(new LsPipelineBundle)) 93 val out = Decoupled(new LsPipelineBundle) 94 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 95 val dcachePAddr = Output(UInt(PAddrBits.W)) 96 val dcacheKill = Output(Bool()) 97 val sbuffer = new LoadForwardQueryIO 98 val lsq = new MaskedLoadForwardQueryIO 99 }) 100 101 val s1_uop = io.in.bits.uop 102 val s1_paddr = io.dtlbResp.bits.paddr 103 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 104 val s1_tlb_miss = io.dtlbResp.bits.miss 105 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 106 val s1_mask = io.in.bits.mask 107 108 io.out.bits := io.in.bits // forwardXX field will be updated in s1 109 110 io.dtlbResp.ready := true.B 111 112 // TOOD: PMA check 113 io.dcachePAddr := s1_paddr 114 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 115 116 // load forward query datapath 117 io.sbuffer.valid := io.in.valid 118 io.sbuffer.paddr := s1_paddr 119 io.sbuffer.uop := s1_uop 120 io.sbuffer.sqIdx := s1_uop.sqIdx 121 io.sbuffer.mask := s1_mask 122 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 123 124 io.lsq.valid := io.in.valid 125 io.lsq.paddr := s1_paddr 126 io.lsq.uop := s1_uop 127 io.lsq.sqIdx := s1_uop.sqIdx 128 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 129 io.lsq.mask := s1_mask 130 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 131 132 io.out.valid := io.in.valid// && !s1_tlb_miss 133 io.out.bits.paddr := s1_paddr 134 io.out.bits.mmio := s1_mmio && !s1_exception 135 io.out.bits.tlbMiss := s1_tlb_miss 136 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 137 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 138 io.out.bits.rsIdx := io.in.bits.rsIdx 139 140 io.in.ready := !io.in.valid || io.out.ready 141 142} 143 144 145// Load Pipeline Stage 2 146// DCache resp 147class LoadUnit_S2 extends XSModule with HasLoadHelper { 148 val io = IO(new Bundle() { 149 val in = Flipped(Decoupled(new LsPipelineBundle)) 150 val out = Decoupled(new LsPipelineBundle) 151 val tlbFeedback = ValidIO(new TlbFeedback) 152 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 153 val lsq = new LoadForwardQueryIO 154 val sbuffer = new LoadForwardQueryIO 155 val dataForwarded = Output(Bool()) 156 val needReplayFromRS = Output(Bool()) 157 }) 158 159 val s2_uop = io.in.bits.uop 160 val s2_mask = io.in.bits.mask 161 val s2_paddr = io.in.bits.paddr 162 val s2_tlb_miss = io.in.bits.tlbMiss 163 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 164 val s2_mmio = io.in.bits.mmio && !s2_exception 165 val s2_cache_miss = io.dcacheResp.bits.miss 166 val s2_cache_replay = io.dcacheResp.bits.replay 167 168 io.dcacheResp.ready := true.B 169 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 170 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 171 172 // feedback tlb result to RS 173 io.tlbFeedback.valid := io.in.valid 174 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 175 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 176 io.needReplayFromRS := s2_cache_replay 177 178 // merge forward result 179 // lsq has higher priority than sbuffer 180 val forwardMask = Wire(Vec(8, Bool())) 181 val forwardData = Wire(Vec(8, UInt(8.W))) 182 183 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 184 io.lsq := DontCare 185 io.sbuffer := DontCare 186 187 // generate XLEN/8 Muxs 188 for (i <- 0 until XLEN / 8) { 189 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 190 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 191 } 192 193 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 194 s2_uop.cf.pc, 195 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 196 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 197 ) 198 199 // data merge 200 val rdataVec = VecInit((0 until XLEN / 8).map(j => 201 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 202 val rdata = rdataVec.asUInt 203 val rdataSel = LookupTree(s2_paddr(2, 0), List( 204 "b000".U -> rdata(63, 0), 205 "b001".U -> rdata(63, 8), 206 "b010".U -> rdata(63, 16), 207 "b011".U -> rdata(63, 24), 208 "b100".U -> rdata(63, 32), 209 "b101".U -> rdata(63, 40), 210 "b110".U -> rdata(63, 48), 211 "b111".U -> rdata(63, 56) 212 )) 213 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 214 215 io.out.valid := io.in.valid && !s2_tlb_miss 216 // Inst will be canceled in store queue / lsq, 217 // so we do not need to care about flush in load / store unit's out.valid 218 io.out.bits := io.in.bits 219 io.out.bits.data := rdataPartialLoad 220 // when exception occurs, set it to not miss and let it write back to roq (via int port) 221 io.out.bits.miss := s2_cache_miss && !s2_exception 222 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 223 io.out.bits.mmio := s2_mmio 224 225 // For timing reasons, we can not let 226 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 227 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 228 // and dcache query is no longer needed. 229 // Such inst will be writebacked from load queue. 230 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception 231 // io.out.bits.forwardX will be send to lq 232 io.out.bits.forwardMask := forwardMask 233 // data retbrived from dcache is also included in io.out.bits.forwardData 234 io.out.bits.forwardData := rdataVec 235 236 io.in.ready := io.out.ready || !io.in.valid 237 238 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 239 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 240 forwardData.asUInt, forwardMask.asUInt 241 ) 242} 243 244class LoadUnit extends XSModule with HasLoadHelper { 245 val io = IO(new Bundle() { 246 val ldin = Flipped(Decoupled(new ExuInput)) 247 val ldout = Decoupled(new ExuOutput) 248 val fpout = Decoupled(new ExuOutput) 249 val redirect = Flipped(ValidIO(new Redirect)) 250 val flush = Input(Bool()) 251 val tlbFeedback = ValidIO(new TlbFeedback) 252 val needReplayFromRS = Output(Bool()) 253 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 254 val dcache = new DCacheLoadIO 255 val dtlb = new TlbRequestIO() 256 val sbuffer = new LoadForwardQueryIO 257 val lsq = new LoadToLsqIO 258 }) 259 260 val load_s0 = Module(new LoadUnit_S0) 261 val load_s1 = Module(new LoadUnit_S1) 262 val load_s2 = Module(new LoadUnit_S2) 263 264 load_s0.io.in <> io.ldin 265 load_s0.io.dtlbReq <> io.dtlb.req 266 load_s0.io.dcacheReq <> io.dcache.req 267 load_s0.io.rsIdx := io.rsIdx 268 269 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 270 271 load_s1.io.dtlbResp <> io.dtlb.resp 272 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 273 io.dcache.s1_kill <> load_s1.io.dcacheKill 274 load_s1.io.sbuffer <> io.sbuffer 275 load_s1.io.lsq <> io.lsq.forward 276 277 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 278 279 load_s2.io.dcacheResp <> io.dcache.resp 280 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 281 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 282 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 283 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 284 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 285 io.tlbFeedback.bits := RegNext(load_s2.io.tlbFeedback.bits) 286 io.tlbFeedback.valid := RegNext(load_s2.io.tlbFeedback.valid && !load_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 287 io.needReplayFromRS := load_s2.io.needReplayFromRS 288 289 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 290 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 291 io.lsq.forward.sqIdxMask := sqIdxMaskReg 292 293 // use s2_hit_way to select data received in s1 294 load_s2.io.dcacheResp.bits.data := Mux1H(io.dcache.s2_hit_way, RegNext(io.dcache.s1_data)) 295 assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 296 297 XSDebug(load_s0.io.out.valid, 298 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 299 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 300 XSDebug(load_s1.io.out.valid, 301 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 302 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 303 304 // writeback to LSQ 305 // Current dcache use MSHR 306 // Load queue will be updated at s2 for both hit/miss int/fp load 307 io.lsq.loadIn.valid := load_s2.io.out.valid 308 io.lsq.loadIn.bits := load_s2.io.out.bits 309 310 // write to rob and writeback bus 311 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 312 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 313 314 // Int load, if hit, will be writebacked at s2 315 val intHitLoadOut = Wire(Valid(new ExuOutput)) 316 intHitLoadOut.valid := s2_wb_valid && !load_s2.io.out.bits.uop.ctrl.fpWen 317 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 318 intHitLoadOut.bits.data := load_s2.io.out.bits.data 319 intHitLoadOut.bits.redirectValid := false.B 320 intHitLoadOut.bits.redirect := DontCare 321 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 322 intHitLoadOut.bits.debug.isPerfCnt := false.B 323 intHitLoadOut.bits.fflags := DontCare 324 325 load_s2.io.out.ready := true.B 326 327 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 328 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 329 330 // Fp load, if hit, will be stored to reg at s2, then it will be recoded at s3, writebacked at s4 331 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 332 fpHitLoadOut.valid := s2_wb_valid && load_s2.io.out.bits.uop.ctrl.fpWen 333 fpHitLoadOut.bits := intHitLoadOut.bits 334 335 val fpLoadUnRecodedReg = Reg(Valid(new ExuOutput)) 336 fpLoadUnRecodedReg.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 337 when(fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad){ 338 fpLoadUnRecodedReg.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 339 } 340 341 val fpLoadRecodedReg = Reg(Valid(new ExuOutput)) 342 when(fpLoadUnRecodedReg.valid){ 343 fpLoadRecodedReg := fpLoadUnRecodedReg 344 fpLoadRecodedReg.bits.data := fpRdataHelper(fpLoadUnRecodedReg.bits.uop, fpLoadUnRecodedReg.bits.data) // recode 345 } 346 fpLoadRecodedReg.valid := fpLoadUnRecodedReg.valid 347 348 io.fpout.bits := fpLoadRecodedReg.bits 349 io.fpout.valid := fpLoadRecodedReg.valid 350 351 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 352 353 when(io.ldout.fire()){ 354 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 355 } 356 357 when(io.fpout.fire()){ 358 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 359 } 360} 361