1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache._ 27import xiangshan.cache.mmu.{TLB, TlbCmd, TlbPtwIO, TlbReq, TlbRequestIO, TlbResp} 28 29class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 30 val loadIn = ValidIO(new LsPipelineBundle) 31 val ldout = Flipped(DecoupledIO(new ExuOutput)) 32 val loadDataForwarded = Output(Bool()) 33 val needReplayFromRS = Output(Bool()) 34 val forward = new PipeLoadForwardQueryIO 35 val loadViolationQuery = new LoadViolationQueryIO 36} 37 38class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 39 // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 40 val data = UInt(XLEN.W) 41 val valid = Bool() 42} 43 44// Load Pipeline Stage 0 45// Generate addr, use addr to query DCache and DTLB 46class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParameters{ 47 val io = IO(new Bundle() { 48 val in = Flipped(Decoupled(new ExuInput)) 49 val out = Decoupled(new LsPipelineBundle) 50 val fastpath = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 51 val dtlbReq = DecoupledIO(new TlbReq) 52 val dcacheReq = DecoupledIO(new DCacheWordReq) 53 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 54 val isFirstIssue = Input(Bool()) 55 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 56 }) 57 require(LoadPipelineWidth == exuParameters.LduCnt) 58 59 val s0_uop = io.in.bits.uop 60 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 61 62 val s0_vaddr = WireInit(io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits)) 63 val s0_mask = WireInit(genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0))) 64 65 if (EnableLoadToLoadForward) { 66 // slow vaddr from non-load insts 67 val slowpath_vaddr = io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 68 val slowpath_mask = genWmask(slowpath_vaddr, s0_uop.ctrl.fuOpType(1,0)) 69 70 // fast vaddr from load insts 71 val fastpath_vaddrs = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 72 io.fastpath(i).data + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 73 }))) 74 val fastpath_masks = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 75 genWmask(fastpath_vaddrs(i), s0_uop.ctrl.fuOpType(1,0)) 76 }))) 77 val fastpath_vaddr = Mux1H(io.loadFastMatch, fastpath_vaddrs) 78 val fastpath_mask = Mux1H(io.loadFastMatch, fastpath_masks) 79 80 // select vaddr from 2 alus 81 s0_vaddr := Mux(io.loadFastMatch.orR, fastpath_vaddr, slowpath_vaddr) 82 s0_mask := Mux(io.loadFastMatch.orR, fastpath_mask, slowpath_mask) 83 XSPerfAccumulate("load_to_load_forward", io.loadFastMatch.orR && io.in.fire()) 84 } 85 86 val isSoftPrefetch = LSUOpType.isPrefetch(s0_uop.ctrl.fuOpType) 87 val isSoftPrefetchRead = s0_uop.ctrl.fuOpType === LSUOpType.prefetch_r 88 val isSoftPrefetchWrite = s0_uop.ctrl.fuOpType === LSUOpType.prefetch_w 89 90 // query DTLB 91 io.dtlbReq.valid := io.in.valid 92 io.dtlbReq.bits.vaddr := s0_vaddr 93 io.dtlbReq.bits.cmd := TlbCmd.read 94 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 95 io.dtlbReq.bits.robIdx := s0_uop.robIdx 96 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 97 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 98 99 // query DCache 100 io.dcacheReq.valid := io.in.valid 101 when (isSoftPrefetchRead) { 102 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFR 103 }.elsewhen (isSoftPrefetchWrite) { 104 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFW 105 }.otherwise { 106 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 107 } 108 io.dcacheReq.bits.addr := s0_vaddr 109 io.dcacheReq.bits.mask := s0_mask 110 io.dcacheReq.bits.data := DontCare 111 when(isSoftPrefetch) { 112 io.dcacheReq.bits.instrtype := SOFT_PREFETCH.U 113 }.otherwise { 114 io.dcacheReq.bits.instrtype := LOAD_SOURCE.U 115 } 116 117 // TODO: update cache meta 118 io.dcacheReq.bits.id := DontCare 119 120 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 121 "b00".U -> true.B, //b 122 "b01".U -> (s0_vaddr(0) === 0.U), //h 123 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 124 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 125 )) 126 127 io.out.valid := io.in.valid && io.dcacheReq.ready 128 129 io.out.bits := DontCare 130 io.out.bits.vaddr := s0_vaddr 131 io.out.bits.mask := s0_mask 132 io.out.bits.uop := s0_uop 133 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 134 io.out.bits.rsIdx := io.rsIdx 135 io.out.bits.isFirstIssue := io.isFirstIssue 136 io.out.bits.isSoftPrefetch := isSoftPrefetch 137 138 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 139 140 XSDebug(io.dcacheReq.fire(), 141 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 142 ) 143 XSPerfAccumulate("in_valid", io.in.valid) 144 XSPerfAccumulate("in_fire", io.in.fire) 145 XSPerfAccumulate("in_fire_first_issue", io.in.valid && io.isFirstIssue) 146 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 147 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 148 XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 149 XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 150 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 151 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 152} 153 154 155// Load Pipeline Stage 1 156// TLB resp (send paddr to dcache) 157class LoadUnit_S1(implicit p: Parameters) extends XSModule { 158 val io = IO(new Bundle() { 159 val in = Flipped(Decoupled(new LsPipelineBundle)) 160 val out = Decoupled(new LsPipelineBundle) 161 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 162 val dcachePAddr = Output(UInt(PAddrBits.W)) 163 val dcacheKill = Output(Bool()) 164 val dcacheBankConflict = Input(Bool()) 165 val fullForwardFast = Output(Bool()) 166 val sbuffer = new LoadForwardQueryIO 167 val lsq = new PipeLoadForwardQueryIO 168 val loadViolationQueryReq = Decoupled(new LoadViolationQueryReq) 169 val rsFeedback = ValidIO(new RSFeedback) 170 val csrCtrl = Flipped(new CustomCSRCtrlIO) 171 val needLdVioCheckRedo = Output(Bool()) 172 }) 173 174 val s1_uop = io.in.bits.uop 175 val s1_paddr = io.dtlbResp.bits.paddr 176 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR // af & pf exception were modified below. 177 val s1_tlb_miss = io.dtlbResp.bits.miss 178 val s1_mask = io.in.bits.mask 179 val s1_bank_conflict = io.dcacheBankConflict 180 181 io.out.bits := io.in.bits // forwardXX field will be updated in s1 182 183 io.dtlbResp.ready := true.B 184 185 // TOOD: PMA check 186 io.dcachePAddr := s1_paddr 187 //io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 188 io.dcacheKill := s1_tlb_miss || s1_exception 189 190 // load forward query datapath 191 io.sbuffer.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 192 io.sbuffer.vaddr := io.in.bits.vaddr 193 io.sbuffer.paddr := s1_paddr 194 io.sbuffer.uop := s1_uop 195 io.sbuffer.sqIdx := s1_uop.sqIdx 196 io.sbuffer.mask := s1_mask 197 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 198 199 io.lsq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 200 io.lsq.vaddr := io.in.bits.vaddr 201 io.lsq.paddr := s1_paddr 202 io.lsq.uop := s1_uop 203 io.lsq.sqIdx := s1_uop.sqIdx 204 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 205 io.lsq.mask := s1_mask 206 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 207 208 // ld-ld violation query 209 io.loadViolationQueryReq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 210 io.loadViolationQueryReq.bits.paddr := s1_paddr 211 io.loadViolationQueryReq.bits.uop := s1_uop 212 213 // Generate forwardMaskFast to wake up insts earlier 214 val forwardMaskFast = io.lsq.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt 215 io.fullForwardFast := (~forwardMaskFast & s1_mask) === 0.U 216 217 // Generate feedback signal caused by: 218 // * dcache bank conflict 219 // * need redo ld-ld violation check 220 val needLdVioCheckRedo = io.loadViolationQueryReq.valid && 221 !io.loadViolationQueryReq.ready && 222 RegNext(io.csrCtrl.ldld_vio_check) 223 io.needLdVioCheckRedo := needLdVioCheckRedo 224 io.rsFeedback.valid := io.in.valid && (s1_bank_conflict || needLdVioCheckRedo) 225 io.rsFeedback.bits.hit := false.B // we have found s1_bank_conflict / re do ld-ld violation check 226 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 227 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 228 io.rsFeedback.bits.sourceType := Mux(s1_bank_conflict, RSFeedbackType.bankConflict, RSFeedbackType.ldVioCheckRedo) 229 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 230 231 // if replay is detected in load_s1, 232 // load inst will be canceled immediately 233 io.out.valid := io.in.valid && !io.rsFeedback.valid 234 io.out.bits.paddr := s1_paddr 235 io.out.bits.tlbMiss := s1_tlb_miss 236 237 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 238 // af & pf exception were modified 239 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 240 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 241 242 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 243 io.out.bits.rsIdx := io.in.bits.rsIdx 244 245 io.out.bits.isSoftPrefetch := io.in.bits.isSoftPrefetch 246 247 io.in.ready := !io.in.valid || io.out.ready 248 249 XSPerfAccumulate("in_valid", io.in.valid) 250 XSPerfAccumulate("in_fire", io.in.fire) 251 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 252 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 253 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 254 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 255} 256 257// Load Pipeline Stage 2 258// DCache resp 259class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper { 260 val io = IO(new Bundle() { 261 val in = Flipped(Decoupled(new LsPipelineBundle)) 262 val out = Decoupled(new LsPipelineBundle) 263 val rsFeedback = ValidIO(new RSFeedback) 264 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 265 val pmpResp = Flipped(new PMPRespBundle()) 266 val lsq = new LoadForwardQueryIO 267 val dataInvalidSqIdx = Input(UInt()) 268 val sbuffer = new LoadForwardQueryIO 269 val dataForwarded = Output(Bool()) 270 val needReplayFromRS = Output(Bool()) 271 val fullForward = Output(Bool()) 272 val fastpath = Output(new LoadToLoadIO) 273 val dcache_kill = Output(Bool()) 274 val loadViolationQueryResp = Flipped(Valid(new LoadViolationQueryResp)) 275 val csrCtrl = Flipped(new CustomCSRCtrlIO) 276 val sentFastUop = Input(Bool()) 277 }) 278 val isSoftPrefetch = io.in.bits.isSoftPrefetch 279 val excep = WireInit(io.in.bits.uop.cf.exceptionVec) 280 excep(loadAccessFault) := io.in.bits.uop.cf.exceptionVec(loadAccessFault) || io.pmpResp.ld 281 when (isSoftPrefetch) { 282 excep := 0.U.asTypeOf(excep.cloneType) 283 } 284 val s2_exception = selectLoad(excep, false).asUInt.orR 285 286 val actually_mmio = io.pmpResp.mmio 287 val s2_uop = io.in.bits.uop 288 val s2_mask = io.in.bits.mask 289 val s2_paddr = io.in.bits.paddr 290 val s2_tlb_miss = io.in.bits.tlbMiss 291 val s2_data_invalid = io.lsq.dataInvalid 292 val s2_mmio = !isSoftPrefetch && actually_mmio && !s2_exception 293 val s2_cache_miss = io.dcacheResp.bits.miss 294 val s2_cache_replay = io.dcacheResp.bits.replay 295 val s2_is_prefetch = io.in.bits.isSoftPrefetch 296 297 // val cnt = RegInit(127.U) 298 // cnt := cnt + io.in.valid.asUInt 299 // val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid || cnt === 0.U 300 301 val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid 302 // assert(!s2_forward_fail) 303 io.dcache_kill := false.B // move pmp resp kill to outside 304 io.dcacheResp.ready := true.B 305 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio || s2_is_prefetch) 306 assert(!(io.in.valid && (dcacheShouldResp && !io.dcacheResp.valid)), "DCache response got lost") 307 308 // merge forward result 309 // lsq has higher priority than sbuffer 310 val forwardMask = Wire(Vec(8, Bool())) 311 val forwardData = Wire(Vec(8, UInt(8.W))) 312 313 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U && !io.lsq.dataInvalid 314 io.lsq := DontCare 315 io.sbuffer := DontCare 316 io.fullForward := fullForward 317 318 // generate XLEN/8 Muxs 319 for (i <- 0 until XLEN / 8) { 320 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 321 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 322 } 323 324 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 325 s2_uop.cf.pc, 326 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 327 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 328 ) 329 330 // data merge 331 val rdataVec = VecInit((0 until XLEN / 8).map(j => 332 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 333 val rdata = rdataVec.asUInt 334 val rdataSel = LookupTree(s2_paddr(2, 0), List( 335 "b000".U -> rdata(63, 0), 336 "b001".U -> rdata(63, 8), 337 "b010".U -> rdata(63, 16), 338 "b011".U -> rdata(63, 24), 339 "b100".U -> rdata(63, 32), 340 "b101".U -> rdata(63, 40), 341 "b110".U -> rdata(63, 48), 342 "b111".U -> rdata(63, 56) 343 )) 344 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 345 346 io.out.valid := io.in.valid && !s2_tlb_miss && !s2_data_invalid 347 // Inst will be canceled in store queue / lsq, 348 // so we do not need to care about flush in load / store unit's out.valid 349 io.out.bits := io.in.bits 350 io.out.bits.data := rdataPartialLoad 351 // when exception occurs, set it to not miss and let it write back to rob (via int port) 352 if (EnableFastForward) { 353 io.out.bits.miss := s2_cache_miss && 354 !s2_exception && 355 !s2_forward_fail && 356 !fullForward && 357 !s2_is_prefetch 358 } else { 359 io.out.bits.miss := s2_cache_miss && 360 !s2_exception && 361 !s2_forward_fail && 362 !s2_is_prefetch 363 } 364 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 365 // if forward fail, replay this inst from fetch 366 val forwardFailReplay = s2_forward_fail && !s2_mmio 367 // if ld-ld violation is detected, replay from this inst from fetch 368 val ldldVioReplay = io.loadViolationQueryResp.valid && 369 io.loadViolationQueryResp.bits.have_violation && 370 RegNext(io.csrCtrl.ldld_vio_check) 371 io.out.bits.uop.ctrl.replayInst := forwardFailReplay || ldldVioReplay 372 io.out.bits.mmio := s2_mmio 373 io.out.bits.uop.ctrl.flushPipe := io.in.bits.uop.ctrl.flushPipe || (s2_mmio && io.sentFastUop) 374 io.out.bits.uop.cf.exceptionVec := excep 375 376 // For timing reasons, sometimes we can not let 377 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 378 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 379 // and dcache query is no longer needed. 380 // Such inst will be writebacked from load queue. 381 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception && !s2_forward_fail 382 // io.out.bits.forwardX will be send to lq 383 io.out.bits.forwardMask := forwardMask 384 // data retbrived from dcache is also included in io.out.bits.forwardData 385 io.out.bits.forwardData := rdataVec 386 387 io.in.ready := io.out.ready || !io.in.valid 388 389 // feedback tlb result to RS 390 io.rsFeedback.valid := io.in.valid 391 when (io.in.bits.isSoftPrefetch) { 392 io.rsFeedback.bits.hit := (!s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception)) 393 }.otherwise { 394 if (EnableFastForward) { 395 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid 396 } else { 397 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception) && !s2_data_invalid 398 } 399 } 400 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 401 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 402 io.rsFeedback.bits.sourceType := Mux(s2_tlb_miss, RSFeedbackType.tlbMiss, 403 Mux(s2_cache_replay, 404 RSFeedbackType.mshrFull, 405 RSFeedbackType.dataInvalid 406 ) 407 ) 408 io.rsFeedback.bits.dataInvalidSqIdx.value := io.dataInvalidSqIdx 409 io.rsFeedback.bits.dataInvalidSqIdx.flag := DontCare 410 411 // s2_cache_replay is quite slow to generate, send it separately to LQ 412 if (EnableFastForward) { 413 io.needReplayFromRS := s2_cache_replay && !fullForward 414 } else { 415 io.needReplayFromRS := s2_cache_replay 416 } 417 418 // fast load to load forward 419 io.fastpath.valid := io.in.valid // for debug only 420 io.fastpath.data := rdata // raw data 421 422 423 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 424 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 425 forwardData.asUInt, forwardMask.asUInt 426 ) 427 428 XSPerfAccumulate("in_valid", io.in.valid) 429 XSPerfAccumulate("in_fire", io.in.fire) 430 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 431 XSPerfAccumulate("dcache_miss", io.in.fire && s2_cache_miss) 432 XSPerfAccumulate("dcache_miss_first_issue", io.in.fire && s2_cache_miss && io.in.bits.isFirstIssue) 433 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 434 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 435 XSPerfAccumulate("replay", io.rsFeedback.valid && !io.rsFeedback.bits.hit) 436 XSPerfAccumulate("replay_tlb_miss", io.rsFeedback.valid && !io.rsFeedback.bits.hit && s2_tlb_miss) 437 XSPerfAccumulate("replay_cache", io.rsFeedback.valid && !io.rsFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 438 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 439 XSPerfAccumulate("replay_from_fetch_forward", io.out.valid && forwardFailReplay) 440 XSPerfAccumulate("replay_from_fetch_load_vio", io.out.valid && ldldVioReplay) 441} 442 443class LoadUnit(implicit p: Parameters) extends XSModule with HasLoadHelper { 444 val io = IO(new Bundle() { 445 val ldin = Flipped(Decoupled(new ExuInput)) 446 val ldout = Decoupled(new ExuOutput) 447 val redirect = Flipped(ValidIO(new Redirect)) 448 val feedbackSlow = ValidIO(new RSFeedback) 449 val feedbackFast = ValidIO(new RSFeedback) 450 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 451 val isFirstIssue = Input(Bool()) 452 val dcache = new DCacheLoadIO 453 val sbuffer = new LoadForwardQueryIO 454 val lsq = new LoadToLsqIO 455 val fastUop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1 456 457 val tlb = new TlbRequestIO 458 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 459 460 val fastpathOut = Output(new LoadToLoadIO) 461 val fastpathIn = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 462 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 463 464 val csrCtrl = Flipped(new CustomCSRCtrlIO) 465 }) 466 467 val load_s0 = Module(new LoadUnit_S0) 468 val load_s1 = Module(new LoadUnit_S1) 469 val load_s2 = Module(new LoadUnit_S2) 470 471 load_s0.io.in <> io.ldin 472 load_s0.io.dtlbReq <> io.tlb.req 473 load_s0.io.dcacheReq <> io.dcache.req 474 load_s0.io.rsIdx := io.rsIdx 475 load_s0.io.isFirstIssue := io.isFirstIssue 476 load_s0.io.fastpath := io.fastpathIn 477 load_s0.io.loadFastMatch := io.loadFastMatch 478 479 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 480 481 load_s1.io.dtlbResp <> io.tlb.resp 482 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 483 io.dcache.s1_kill <> load_s1.io.dcacheKill 484 load_s1.io.sbuffer <> io.sbuffer 485 load_s1.io.lsq <> io.lsq.forward 486 load_s1.io.loadViolationQueryReq <> io.lsq.loadViolationQuery.req 487 load_s1.io.dcacheBankConflict <> io.dcache.s1_bank_conflict 488 load_s1.io.csrCtrl <> io.csrCtrl 489 490 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 491 492 io.dcache.s2_kill := load_s2.io.dcache_kill || (io.pmp.ld || io.pmp.mmio) // to kill mmio resp which are redirected 493 load_s2.io.dcacheResp <> io.dcache.resp 494 load_s2.io.pmpResp <> io.pmp 495 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 496 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 497 load_s2.io.lsq.forwardMaskFast <> io.lsq.forward.forwardMaskFast // should not be used in load_s2 498 load_s2.io.lsq.dataInvalid <> io.lsq.forward.dataInvalid 499 load_s2.io.lsq.matchInvalid <> io.lsq.forward.matchInvalid 500 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 501 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 502 load_s2.io.sbuffer.forwardMaskFast <> io.sbuffer.forwardMaskFast // should not be used in load_s2 503 load_s2.io.sbuffer.dataInvalid <> io.sbuffer.dataInvalid // always false 504 load_s2.io.sbuffer.matchInvalid <> io.sbuffer.matchInvalid 505 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 506 load_s2.io.fastpath <> io.fastpathOut 507 load_s2.io.dataInvalidSqIdx := io.lsq.forward.dataInvalidSqIdx // provide dataInvalidSqIdx to make wakeup faster 508 load_s2.io.loadViolationQueryResp <> io.lsq.loadViolationQuery.resp 509 load_s2.io.csrCtrl <> io.csrCtrl 510 load_s2.io.sentFastUop := RegEnable(io.fastUop.valid, load_s1.io.out.fire()) // RegNext is also ok 511 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 512 513 // feedback tlb miss / dcache miss queue full 514 io.feedbackSlow.bits := RegNext(load_s2.io.rsFeedback.bits) 515 io.feedbackSlow.valid := RegNext(load_s2.io.rsFeedback.valid && !load_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 516 517 // feedback bank conflict to rs 518 io.feedbackFast.bits := load_s1.io.rsFeedback.bits 519 io.feedbackFast.valid := load_s1.io.rsFeedback.valid 520 // If replay is reported at load_s1, inst will be canceled (will not enter load_s2), 521 // in that case: 522 // * replay should not be reported twice 523 assert(!(RegNext(RegNext(io.feedbackFast.valid)) && io.feedbackSlow.valid)) 524 // * io.fastUop.valid should not be reported 525 assert(!RegNext(io.feedbackFast.valid && io.fastUop.valid)) 526 527 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 528 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 529 io.lsq.forward.sqIdxMask := sqIdxMaskReg 530 531 // // use s2_hit_way to select data received in s1 532 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 533 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 534 535 io.fastUop.valid := io.dcache.s1_hit_way.orR && // dcache hit 536 !io.dcache.s1_disable_fast_wakeup && // load fast wakeup should be disabled when dcache data read is not ready 537 load_s1.io.in.valid && // valid laod request 538 !load_s1.io.dcacheKill && // not mmio or tlb miss 539 !io.lsq.forward.dataInvalidFast && // forward failed 540 !load_s1.io.needLdVioCheckRedo // load-load violation check: load paddr cam struct hazard 541 io.fastUop.bits := load_s1.io.out.bits.uop 542 543 XSDebug(load_s0.io.out.valid, 544 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 545 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 546 XSDebug(load_s1.io.out.valid, 547 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 548 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 549 550 // writeback to LSQ 551 // Current dcache use MSHR 552 // Load queue will be updated at s2 for both hit/miss int/fp load 553 io.lsq.loadIn.valid := load_s2.io.out.valid 554 io.lsq.loadIn.bits := load_s2.io.out.bits 555 556 // write to rob and writeback bus 557 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss && !load_s2.io.out.bits.mmio 558 559 // Int load, if hit, will be writebacked at s2 560 val hitLoadOut = Wire(Valid(new ExuOutput)) 561 hitLoadOut.valid := s2_wb_valid 562 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 563 hitLoadOut.bits.data := load_s2.io.out.bits.data 564 hitLoadOut.bits.redirectValid := false.B 565 hitLoadOut.bits.redirect := DontCare 566 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 567 hitLoadOut.bits.debug.isPerfCnt := false.B 568 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 569 hitLoadOut.bits.debug.vaddr := load_s2.io.out.bits.vaddr 570 hitLoadOut.bits.fflags := DontCare 571 572 load_s2.io.out.ready := true.B 573 574 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 575 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 576 577 io.lsq.ldout.ready := !hitLoadOut.valid 578 579 val perfinfo = IO(new Bundle(){ 580 val perfEvents = Output(new PerfEventsBundle(12)) 581 }) 582 583 val perfEvents = Seq( 584 ("load_s0_in_fire ", load_s0.io.in.fire() ), 585 ("load_to_load_forward ", load_s0.io.loadFastMatch.orR && load_s0.io.in.fire() ), 586 ("stall_dcache ", load_s0.io.out.valid && load_s0.io.out.ready && !load_s0.io.dcacheReq.ready ), 587 ("addr_spec_success ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) === load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 588 ("addr_spec_failed ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) =/= load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 589 ("load_s1_in_fire ", load_s1.io.in.fire ), 590 ("load_s1_tlb_miss ", load_s1.io.in.fire && load_s1.io.dtlbResp.bits.miss ), 591 ("load_s2_in_fire ", load_s2.io.in.fire ), 592 ("load_s2_dcache_miss ", load_s2.io.in.fire && load_s2.io.dcacheResp.bits.miss ), 593 ("load_s2_replay ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit ), 594 ("load_s2_replay_tlb_miss ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && load_s2.io.in.bits.tlbMiss ), 595 ("load_s2_replay_cache ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && !load_s2.io.in.bits.tlbMiss && load_s2.io.dcacheResp.bits.miss), 596 ) 597 598 for (((perf_out,(perf_name,perf)),i) <- perfinfo.perfEvents.perf_events.zip(perfEvents).zipWithIndex) { 599 perf_out.incr_step := RegNext(perf) 600 } 601 602 when(io.ldout.fire()){ 603 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 604 } 605} 606