1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants} 8import xiangshan.backend.LSUOpType 9 10class LoadToLsroqIO extends XSBundle { 11 val loadIn = ValidIO(new LsPipelineBundle) 12 val ldout = Flipped(DecoupledIO(new ExuOutput)) 13 val forward = new LoadForwardQueryIO 14} 15 16// Load Pipeline Stage 0 17// Generate addr, use addr to query DCache and DTLB 18class LoadUnit_S0 extends XSModule { 19 val io = IO(new Bundle() { 20 val in = Flipped(Decoupled(new ExuInput)) 21 val out = Decoupled(new LsPipelineBundle) 22 val redirect = Flipped(ValidIO(new Redirect)) 23 val dtlb = Valid(new TlbReq) 24 val dcache = DecoupledIO(new DCacheLoadReq) 25 }) 26 27 val s0_uop = io.in.bits.uop 28 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 29 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 30 31 // query DTLB 32 io.dtlb.valid := io.out.valid 33 io.dtlb.bits.vaddr := s0_vaddr 34 io.dtlb.bits.cmd := TlbCmd.read 35 io.dtlb.bits.roqIdx := s0_uop.roqIdx 36 io.dtlb.bits.debug.pc := s0_uop.cf.pc 37 io.dtlb.bits.debug.lsroqIdx := s0_uop.lsroqIdx 38 39 // query DCache 40 io.dcache.valid := io.out.valid 41 io.dcache.bits.cmd := MemoryOpConstants.M_XRD 42 io.dcache.bits.addr := s0_vaddr 43 io.dcache.bits.mask := s0_mask 44 45 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 46 "b00".U -> true.B, //b 47 "b01".U -> (s0_vaddr(0) === 0.U), //h 48 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 49 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 50 )) 51 52 io.out.valid := io.in.valid && !s0_uop.needFlush(io.redirect) 53 io.out.bits := DontCare 54 io.out.bits.vaddr := s0_vaddr 55 io.out.bits.mask := s0_mask 56 io.out.bits.uop := s0_uop 57 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 58 59 io.in.ready := io.out.ready 60} 61 62 63// Load Pipeline Stage 1 64// TLB resp (send paddr to dcache) 65class LoadUnit_S1 extends XSModule { 66 val io = IO(new Bundle() { 67 val in = Flipped(Decoupled(new LsPipelineBundle)) 68 val out = Decoupled(new LsPipelineBundle) 69 val redirect = Flipped(ValidIO(new Redirect)) 70 val tlbFeedback = ValidIO(new TlbFeedback) 71 val dtlb = Valid(new TlbResp) 72 val forward = new LoadForwardQueryIO 73 val s1_kill = Output(Bool()) 74 val s1_paddr = Output(UInt(PAddBits.W)) 75 }) 76 77 val s1_uop = io.in.bits.uop 78 val s1_tlb_miss = io.dtlb.resp.bits.miss 79 val s1_paddr = io.dtlb.resp.bits.paddr 80 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) 81 82 io.dtlb.ready := io.out.ready 83 84 io.tlbFeedback.valid := io.out.valid 85 io.tlbFeedback.bits.hit := !s1_tlb_miss 86 io.tlbFeedback.bits.roqIdx := s1_uop.roqIdx 87 88 // if tlb misses or mmio, kill prvious cycles dcache request 89 // TODO: kill dcache request when flushed 90 io.s1_kill := s1_tlb_miss || s1_mmio 91 io.s1_paddr := s1_paddr 92 93 io.forward.valid := io.out.valid 94 io.forward.paddr := s1_paddr 95 io.forward.mask := io.in.bits.mask 96 io.forward.lsroqIdx := s1_uop.lsroqIdx 97 io.forward.sqIdx := s1_uop.sqIdx 98 io.forward.uop := s1_uop 99 io.forward.pc := s1_uop.cf.pc 100 101 io.out.valid := io.in.valid && !s1_uop.needFlush(io.redirect) 102 io.out.bits := io.in.bits 103 io.out.bits.paddr := s1_paddr 104 io.out.bits.mmio := s1_mmio 105 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 106 107 io.in.ready := io.out.ready || !io.in.valid 108 109} 110 111 112// Load Pipeline Stage 2 113// DCache resp 114class LoadUnit_S2 extends XSModule { 115 val io = IO(new Bundle() { 116 val in = Flipped(Decoupled(new LsPipelineBundle)) 117 val out = Decoupled(new LsPipelineBundle) 118 val redirect = Flipped(ValidIO(new Redirect)) 119 val dcache = Flipped(DecoupledIO(new DCacheWordResp)) 120 val sbuffer = new LoadForwardQueryIO 121 val lsroq = new LoadForwardQueryIO 122 }) 123 124 val s2_uop = io.in.bits.uop 125 val s2_mask = io.in.bits.mask 126 val s2_paddr = io.in.bits.paddr 127 val s2_cache_miss = io.dcache.resp.miss 128 129 io.dcache.ready := true.B 130 assert(!(io.in.valid && !io.dcache.resp.valid), "DCache response got lost") 131 132 val forwardMask = WireInit(io.sbuffer.forwardMask) 133 val forwardData = WireInit(io.sbuffer.forwardData) 134 // generate XLEN/8 Muxs 135 for (i <- 0 until XLEN / 8) { 136 when(io.lsroq.forwardMask(i)) { 137 forwardMask(i) := true.B 138 forwardData(i) := io.lsroq.forwardData(i) 139 } 140 } 141 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 142 143 // data merge 144 val rdata = VecInit((0 until XLEN / 8).map(j => 145 Mux(forwardMask(j), forwardData(j), io.dcache.resp.data(8*(j+1)-1, 8*j)))).asUInt 146 val rdataSel = LookupTree(s2_paddr(2, 0), List( 147 "b000".U -> rdata(63, 0), 148 "b001".U -> rdata(63, 8), 149 "b010".U -> rdata(63, 16), 150 "b011".U -> rdata(63, 24), 151 "b100".U -> rdata(63, 32), 152 "b101".U -> rdata(63, 40), 153 "b110".U -> rdata(63, 48), 154 "b111".U -> rdata(63, 56) 155 )) 156 val rdataPartialLoad = LookupTree(s2_uop.ctrl.fuOpType, List( 157 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 158 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 159 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 160 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 161 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 162 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 163 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN) 164 )) 165 166 // TODO: ECC check 167 168 io.out.valid := io.in.valid && !s2_uop.needFlush(io.redirect) 169 io.out.bits := io.in.bits 170 io.out.bits.data := rdataPartialLoad 171 io.out.bits.miss := s2_cache_miss && !fullForward 172 173 io.in.ready := io.out.ready || !io.in.valid 174 175} 176 177 178class LoadUnit extends XSModule { 179 val io = IO(new Bundle() { 180 val ldin = Flipped(Decoupled(new ExuInput)) 181 val ldout = Decoupled(new ExuOutput) 182 val redirect = Flipped(ValidIO(new Redirect)) 183 val tlbFeedback = ValidIO(new TlbFeedback) 184 val dcache = new DCacheWordIO 185 val dtlb = new TlbRequestIO() 186 val sbuffer = new LoadForwardQueryIO 187 val lsroq = new LoadToLsroqIO 188 }) 189 190 val load_s0 = Module(new LoadUnit_S0) 191 val load_s1 = Module(new LoadUnit_S1) 192 val load_s2 = Module(new LoadUnit_S2) 193 194 load_s0.io.in <> io.ldin 195 load_s0.io.redirect <> io.redirect 196 load_s0.io.dtlb <> io.dtlb.req 197 load_s0.io.dcache <> io.dcache.req 198 199 PipelineConnect(load_s0.io.out, load_s1.io.in, load_s1.io.out.fire(), false.B) 200 201 io.dcache.req.bits.paddr := load_s1.io.out.bits.paddr 202 load_s1.io.redirect <> io.redirect 203 load_s1.io.tlbFeedback <> io.tlbFeedback 204 load_s1.io.dtlb <> io.dtlb.resp 205 io.sbuffer <> load_s1.io.forward 206 io.lsroq.forward <> load_s1.io.forward 207 208 PipelineConnect(load_s1.io.out, load_s2.io.in, load_s2.io.out.fire(), false.B) 209 210 load_s2.io.redirect <> io.redirect 211 load_s2.io.dcache <> io.dcache.resp 212 load_s2.io.sbuffer.forwardMask := io.sbuffer.forwardMask 213 load_s2.io.sbuffer.forwardData := io.sbuffer.forwardData 214 load_s2.io.lsroq.forwardMask := io.lsroq.forward.forwardMask 215 load_s2.io.lsroq.forwardData := io.lsroq.forward.forwardData 216 217 XSDebug(load_s0.io.out.valid, 218 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, " + 219 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 220 XSDebug(load_s1.io.out.valid, 221 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 222 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}") 223 224 // writeback to LSROQ 225 // Current dcache use MSHR 226 io.lsroq.loadIn.valid := load_s2.io.out.valid 227 io.lsroq.loadIn.bits := load_s2.io.out.bits 228 229 val hitLoadOut = Wire(Valid(new ExuOutput)) 230 hitLoadOut.valid := load_s2.io.out.valid && !load_s2.io.out.bits.miss 231 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 232 hitLoadOut.bits.data := load_s2.io.out.bits.data 233 hitLoadOut.bits.redirectValid := false.B 234 hitLoadOut.bits.redirect := DontCare 235 hitLoadOut.bits.brUpdate := DontCare 236 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 237 238 // TODO: arbiter 239 // if hit, writeback result to CDB 240 // val ldout = Vec(2, Decoupled(new ExuOutput)) 241 // when io.loadIn(i).fire() && !io.io.loadIn(i).miss, commit load to cdb 242 // val cdbArb = Module(new Arbiter(new ExuOutput, 2)) 243 // io.ldout <> cdbArb.io.out 244 // hitLoadOut <> cdbArb.io.in(0) 245 // io.lsroq.ldout <> cdbArb.io.in(1) // missLoadOut 246 load_s2.io.out.ready := true.B 247 io.lsroq.ldout.ready := !hitLoadOut.valid 248 io.ldout.bits := Mux(load_s2.io.out.ready, hitLoadOut.bits, io.lsroq.ldout.bits) 249 250 when(io.ldout.fire()){ 251 XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen) 252 } 253} 254