1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val forward = new LoadForwardQueryIO 16} 17 18// Load Pipeline Stage 0 19// Generate addr, use addr to query DCache and DTLB 20class LoadUnit_S0 extends XSModule { 21 val io = IO(new Bundle() { 22 val in = Flipped(Decoupled(new ExuInput)) 23 val out = Decoupled(new LsPipelineBundle) 24 val dtlbReq = DecoupledIO(new TlbReq) 25 val dcacheReq = DecoupledIO(new DCacheWordReq) 26 }) 27 28 val s0_uop = io.in.bits.uop 29 val s0_vaddr = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN) 30 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 31 32 // query DTLB 33 io.dtlbReq.valid := io.in.valid 34 io.dtlbReq.bits.vaddr := s0_vaddr 35 io.dtlbReq.bits.cmd := TlbCmd.read 36 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 37 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 38 39 // query DCache 40 io.dcacheReq.valid := io.in.valid 41 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 42 io.dcacheReq.bits.addr := s0_vaddr 43 io.dcacheReq.bits.mask := s0_mask 44 io.dcacheReq.bits.data := DontCare 45 46 // TODO: update cache meta 47 io.dcacheReq.bits.meta.id := DontCare 48 io.dcacheReq.bits.meta.vaddr := s0_vaddr 49 io.dcacheReq.bits.meta.paddr := DontCare 50 io.dcacheReq.bits.meta.uop := s0_uop 51 io.dcacheReq.bits.meta.mmio := false.B 52 io.dcacheReq.bits.meta.tlb_miss := false.B 53 io.dcacheReq.bits.meta.mask := s0_mask 54 io.dcacheReq.bits.meta.replay := false.B 55 56 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 57 "b00".U -> true.B, //b 58 "b01".U -> (s0_vaddr(0) === 0.U), //h 59 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 60 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 61 )) 62 63 io.out.valid := io.in.valid && io.dcacheReq.ready 64 65 io.out.bits := DontCare 66 io.out.bits.vaddr := s0_vaddr 67 io.out.bits.mask := s0_mask 68 io.out.bits.uop := s0_uop 69 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 70 71 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 72 73 XSDebug(io.dcacheReq.fire(), 74 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 75 ) 76} 77 78 79// Load Pipeline Stage 1 80// TLB resp (send paddr to dcache) 81class LoadUnit_S1 extends XSModule { 82 val io = IO(new Bundle() { 83 val in = Flipped(Decoupled(new LsPipelineBundle)) 84 val out = Decoupled(new LsPipelineBundle) 85 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 86 val dcachePAddr = Output(UInt(PAddrBits.W)) 87 val dcacheKill = Output(Bool()) 88 val sbuffer = new LoadForwardQueryIO 89 val lsq = new LoadForwardQueryIO 90 }) 91 92 val s1_uop = io.in.bits.uop 93 val s1_paddr = io.dtlbResp.bits.paddr 94 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 95 val s1_tlb_miss = io.dtlbResp.bits.miss 96 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) 97 val s1_mask = io.in.bits.mask 98 99 io.out.bits := io.in.bits // forwardXX field will be updated in s1 100 101 io.dtlbResp.ready := true.B 102 103 // TOOD: PMA check 104 io.dcachePAddr := s1_paddr 105 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 106 107 // load forward query datapath 108 io.sbuffer.valid := io.in.valid 109 io.sbuffer.paddr := s1_paddr 110 io.sbuffer.uop := s1_uop 111 io.sbuffer.sqIdx := s1_uop.sqIdx 112 io.sbuffer.mask := s1_mask 113 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 114 115 io.lsq.valid := io.in.valid 116 io.lsq.paddr := s1_paddr 117 io.lsq.uop := s1_uop 118 io.lsq.sqIdx := s1_uop.sqIdx 119 io.lsq.mask := s1_mask 120 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 121 122 io.out.valid := io.in.valid// && !s1_tlb_miss 123 io.out.bits.paddr := s1_paddr 124 io.out.bits.mmio := s1_mmio && !s1_exception 125 io.out.bits.tlbMiss := s1_tlb_miss 126 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 127 128 io.in.ready := !io.in.valid || io.out.ready 129 130} 131 132 133// Load Pipeline Stage 2 134// DCache resp 135class LoadUnit_S2 extends XSModule with HasLoadHelper { 136 val io = IO(new Bundle() { 137 val in = Flipped(Decoupled(new LsPipelineBundle)) 138 val out = Decoupled(new LsPipelineBundle) 139 val tlbFeedback = ValidIO(new TlbFeedback) 140 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 141 val lsq = new LoadForwardQueryIO 142 val sbuffer = new LoadForwardQueryIO 143 }) 144 145 val s2_uop = io.in.bits.uop 146 val s2_mask = io.in.bits.mask 147 val s2_paddr = io.in.bits.paddr 148 val s2_tlb_miss = io.in.bits.tlbMiss 149 val s2_mmio = io.in.bits.mmio 150 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 151 val s2_cache_miss = io.dcacheResp.bits.miss 152 val s2_cache_replay = io.dcacheResp.bits.replay 153 154 io.dcacheResp.ready := true.B 155 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 156 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 157 158 // feedback tlb result to RS 159 io.tlbFeedback.valid := io.in.valid 160 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 161 io.tlbFeedback.bits.roqIdx := s2_uop.roqIdx 162 163 val forwardMask = io.out.bits.forwardMask 164 val forwardData = io.out.bits.forwardData 165 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 166 167 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 168 s2_uop.cf.pc, 169 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 170 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 171 ) 172 173 // data merge 174 val rdata = VecInit((0 until XLEN / 8).map(j => 175 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 176 val rdataSel = LookupTree(s2_paddr(2, 0), List( 177 "b000".U -> rdata(63, 0), 178 "b001".U -> rdata(63, 8), 179 "b010".U -> rdata(63, 16), 180 "b011".U -> rdata(63, 24), 181 "b100".U -> rdata(63, 32), 182 "b101".U -> rdata(63, 40), 183 "b110".U -> rdata(63, 48), 184 "b111".U -> rdata(63, 56) 185 )) 186 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 187 188 // TODO: ECC check 189 190 io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 191 // Inst will be canceled in store queue / lsq, 192 // so we do not need to care about flush in load / store unit's out.valid 193 io.out.bits := io.in.bits 194 io.out.bits.data := rdataPartialLoad 195 // when exception occurs, set it to not miss and let it write back to roq (via int port) 196 io.out.bits.miss := s2_cache_miss && !fullForward && !s2_exception 197 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 198 io.out.bits.mmio := s2_mmio 199 200 io.in.ready := io.out.ready || !io.in.valid 201 202 // merge forward result 203 // lsq has higher priority than sbuffer 204 io.lsq := DontCare 205 io.sbuffer := DontCare 206 // generate XLEN/8 Muxs 207 for (i <- 0 until XLEN / 8) { 208 when (io.sbuffer.forwardMask(i)) { 209 io.out.bits.forwardMask(i) := true.B 210 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 211 } 212 when (io.lsq.forwardMask(i)) { 213 io.out.bits.forwardMask(i) := true.B 214 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 215 } 216 } 217 218 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 219 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 220 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 221 ) 222} 223 224class LoadUnit extends XSModule with HasLoadHelper { 225 val io = IO(new Bundle() { 226 val ldin = Flipped(Decoupled(new ExuInput)) 227 val ldout = Decoupled(new ExuOutput) 228 val fpout = Decoupled(new ExuOutput) 229 val redirect = Flipped(ValidIO(new Redirect)) 230 val tlbFeedback = ValidIO(new TlbFeedback) 231 val dcache = new DCacheLoadIO 232 val dtlb = new TlbRequestIO() 233 val sbuffer = new LoadForwardQueryIO 234 val lsq = new LoadToLsqIO 235 }) 236 237 val load_s0 = Module(new LoadUnit_S0) 238 val load_s1 = Module(new LoadUnit_S1) 239 val load_s2 = Module(new LoadUnit_S2) 240 241 load_s0.io.in <> io.ldin 242 load_s0.io.dtlbReq <> io.dtlb.req 243 load_s0.io.dcacheReq <> io.dcache.req 244 245 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 246 247 load_s1.io.dtlbResp <> io.dtlb.resp 248 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 249 io.dcache.s1_kill <> load_s1.io.dcacheKill 250 load_s1.io.sbuffer <> io.sbuffer 251 load_s1.io.lsq <> io.lsq.forward 252 253 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 254 255 load_s2.io.tlbFeedback <> io.tlbFeedback 256 load_s2.io.dcacheResp <> io.dcache.resp 257 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 258 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 259 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 260 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 261 262 XSDebug(load_s0.io.out.valid, 263 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 264 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 265 XSDebug(load_s1.io.out.valid, 266 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 267 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 268 269 // writeback to LSQ 270 // Current dcache use MSHR 271 // Load queue will be updated at s2 for both hit/miss int/fp load 272 io.lsq.loadIn.valid := load_s2.io.out.valid 273 io.lsq.loadIn.bits := load_s2.io.out.bits 274 275 // write to rob and writeback bus 276 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 277 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 278 279 // Int load, if hit, will be writebacked at s2 280 val intHitLoadOut = Wire(Valid(new ExuOutput)) 281 intHitLoadOut.valid := s2_wb_valid && !load_s2.io.out.bits.uop.ctrl.fpWen 282 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 283 intHitLoadOut.bits.data := load_s2.io.out.bits.data 284 intHitLoadOut.bits.redirectValid := false.B 285 intHitLoadOut.bits.redirect := DontCare 286 intHitLoadOut.bits.brUpdate := DontCare 287 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 288 intHitLoadOut.bits.debug.isPerfCnt := false.B 289 intHitLoadOut.bits.fflags := DontCare 290 291 load_s2.io.out.ready := true.B 292 293 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 294 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 295 296 // Fp load, if hit, will be send to recoder at s2, then it will be recoded & writebacked at s3 297 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 298 fpHitLoadOut.valid := s2_wb_valid && load_s2.io.out.bits.uop.ctrl.fpWen 299 fpHitLoadOut.bits := intHitLoadOut.bits 300 301 val fpLoadOut = Wire(Valid(new ExuOutput)) 302 fpLoadOut.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 303 fpLoadOut.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 304 305 val fpLoadOutReg = RegNext(fpLoadOut) 306 io.fpout.bits := fpLoadOutReg.bits 307 io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode 308 io.fpout.valid := RegNext(fpLoadOut.valid) 309 310 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 311 312 when(io.ldout.fire()){ 313 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 314 } 315 316 when(io.fpout.fire()){ 317 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 318 } 319} 320