1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val loadDataForwarded = Output(Bool()) 16 val needReplayFromRS = Output(Bool()) 17 val forward = new MaskedLoadForwardQueryIO 18} 19 20// Load Pipeline Stage 0 21// Generate addr, use addr to query DCache and DTLB 22class LoadUnit_S0 extends XSModule { 23 val io = IO(new Bundle() { 24 val in = Flipped(Decoupled(new ExuInput)) 25 val out = Decoupled(new LsPipelineBundle) 26 val dtlbReq = DecoupledIO(new TlbReq) 27 val dcacheReq = DecoupledIO(new DCacheWordReq) 28 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 29 }) 30 31 val s0_uop = io.in.bits.uop 32 // val s0_vaddr = io.in.bits.src1 + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 33 // val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 34 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 35 val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 36 val s0_vaddr_hi = Mux(s0_vaddr_lo(12), 37 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+1.U), 38 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src1(VAddrBits-1, 12)), 39 ) 40 val s0_vaddr = Cat(s0_vaddr_hi, s0_vaddr_lo(11,0)) 41 val s0_mask = genWmask(s0_vaddr_lo, s0_uop.ctrl.fuOpType(1,0)) 42 43 // query DTLB 44 io.dtlbReq.valid := io.in.valid 45 io.dtlbReq.bits.vaddr := s0_vaddr 46 io.dtlbReq.bits.cmd := TlbCmd.read 47 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 48 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 49 50 // query DCache 51 io.dcacheReq.valid := io.in.valid 52 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 53 io.dcacheReq.bits.addr := s0_vaddr 54 io.dcacheReq.bits.mask := s0_mask 55 io.dcacheReq.bits.data := DontCare 56 57 // TODO: update cache meta 58 io.dcacheReq.bits.id := DontCare 59 60 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 61 "b00".U -> true.B, //b 62 "b01".U -> (s0_vaddr(0) === 0.U), //h 63 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 64 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 65 )) 66 67 io.out.valid := io.in.valid && io.dcacheReq.ready 68 69 io.out.bits := DontCare 70 io.out.bits.vaddr := s0_vaddr 71 io.out.bits.mask := s0_mask 72 io.out.bits.uop := s0_uop 73 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 74 io.out.bits.rsIdx := io.rsIdx 75 76 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 77 78 XSDebug(io.dcacheReq.fire(), 79 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 80 ) 81} 82 83 84// Load Pipeline Stage 1 85// TLB resp (send paddr to dcache) 86class LoadUnit_S1 extends XSModule { 87 val io = IO(new Bundle() { 88 val in = Flipped(Decoupled(new LsPipelineBundle)) 89 val out = Decoupled(new LsPipelineBundle) 90 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 91 val dcachePAddr = Output(UInt(PAddrBits.W)) 92 val dcacheKill = Output(Bool()) 93 val sbuffer = new LoadForwardQueryIO 94 val lsq = new MaskedLoadForwardQueryIO 95 }) 96 97 val s1_uop = io.in.bits.uop 98 val s1_paddr = io.dtlbResp.bits.paddr 99 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 100 val s1_tlb_miss = io.dtlbResp.bits.miss 101 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 102 val s1_mask = io.in.bits.mask 103 104 io.out.bits := io.in.bits // forwardXX field will be updated in s1 105 106 io.dtlbResp.ready := true.B 107 108 // TOOD: PMA check 109 io.dcachePAddr := s1_paddr 110 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 111 112 // load forward query datapath 113 io.sbuffer.valid := io.in.valid 114 io.sbuffer.paddr := s1_paddr 115 io.sbuffer.uop := s1_uop 116 io.sbuffer.sqIdx := s1_uop.sqIdx 117 io.sbuffer.mask := s1_mask 118 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 119 120 io.lsq.valid := io.in.valid 121 io.lsq.paddr := s1_paddr 122 io.lsq.uop := s1_uop 123 io.lsq.sqIdx := s1_uop.sqIdx 124 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 125 io.lsq.mask := s1_mask 126 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 127 128 io.out.valid := io.in.valid// && !s1_tlb_miss 129 io.out.bits.paddr := s1_paddr 130 io.out.bits.mmio := s1_mmio && !s1_exception 131 io.out.bits.tlbMiss := s1_tlb_miss 132 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 133 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 134 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 135 io.out.bits.rsIdx := io.in.bits.rsIdx 136 137 io.in.ready := !io.in.valid || io.out.ready 138 139} 140 141 142// Load Pipeline Stage 2 143// DCache resp 144class LoadUnit_S2 extends XSModule with HasLoadHelper { 145 val io = IO(new Bundle() { 146 val in = Flipped(Decoupled(new LsPipelineBundle)) 147 val out = Decoupled(new LsPipelineBundle) 148 val tlbFeedback = ValidIO(new TlbFeedback) 149 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 150 val lsq = new LoadForwardQueryIO 151 val sbuffer = new LoadForwardQueryIO 152 val dataForwarded = Output(Bool()) 153 val needReplayFromRS = Output(Bool()) 154 }) 155 156 val s2_uop = io.in.bits.uop 157 val s2_mask = io.in.bits.mask 158 val s2_paddr = io.in.bits.paddr 159 val s2_tlb_miss = io.in.bits.tlbMiss 160 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 161 val s2_mmio = io.in.bits.mmio && !s2_exception 162 val s2_cache_miss = io.dcacheResp.bits.miss 163 val s2_cache_replay = io.dcacheResp.bits.replay 164 165 io.dcacheResp.ready := true.B 166 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 167 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 168 169 // feedback tlb result to RS 170 io.tlbFeedback.valid := io.in.valid 171 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception) 172 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 173 io.tlbFeedback.bits.flushState := io.in.bits.ptwBack 174 io.needReplayFromRS := s2_cache_replay 175 176 // merge forward result 177 // lsq has higher priority than sbuffer 178 val forwardMask = Wire(Vec(8, Bool())) 179 val forwardData = Wire(Vec(8, UInt(8.W))) 180 181 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 182 io.lsq := DontCare 183 io.sbuffer := DontCare 184 185 // generate XLEN/8 Muxs 186 for (i <- 0 until XLEN / 8) { 187 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 188 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 189 } 190 191 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 192 s2_uop.cf.pc, 193 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 194 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 195 ) 196 197 // data merge 198 val rdataVec = VecInit((0 until XLEN / 8).map(j => 199 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 200 val rdata = rdataVec.asUInt 201 val rdataSel = LookupTree(s2_paddr(2, 0), List( 202 "b000".U -> rdata(63, 0), 203 "b001".U -> rdata(63, 8), 204 "b010".U -> rdata(63, 16), 205 "b011".U -> rdata(63, 24), 206 "b100".U -> rdata(63, 32), 207 "b101".U -> rdata(63, 40), 208 "b110".U -> rdata(63, 48), 209 "b111".U -> rdata(63, 56) 210 )) 211 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 212 213 io.out.valid := io.in.valid && !s2_tlb_miss 214 // Inst will be canceled in store queue / lsq, 215 // so we do not need to care about flush in load / store unit's out.valid 216 io.out.bits := io.in.bits 217 io.out.bits.data := rdataPartialLoad 218 // when exception occurs, set it to not miss and let it write back to roq (via int port) 219 io.out.bits.miss := s2_cache_miss && !s2_exception 220 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 221 io.out.bits.mmio := s2_mmio 222 223 // For timing reasons, we can not let 224 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 225 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 226 // and dcache query is no longer needed. 227 // Such inst will be writebacked from load queue. 228 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception 229 // io.out.bits.forwardX will be send to lq 230 io.out.bits.forwardMask := forwardMask 231 // data retbrived from dcache is also included in io.out.bits.forwardData 232 io.out.bits.forwardData := rdataVec 233 234 io.in.ready := io.out.ready || !io.in.valid 235 236 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 237 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 238 forwardData.asUInt, forwardMask.asUInt 239 ) 240} 241 242class LoadUnit extends XSModule with HasLoadHelper { 243 val io = IO(new Bundle() { 244 val ldin = Flipped(Decoupled(new ExuInput)) 245 val ldout = Decoupled(new ExuOutput) 246 val redirect = Flipped(ValidIO(new Redirect)) 247 val flush = Input(Bool()) 248 val tlbFeedback = ValidIO(new TlbFeedback) 249 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 250 val dcache = new DCacheLoadIO 251 val dtlb = new TlbRequestIO() 252 val sbuffer = new LoadForwardQueryIO 253 val lsq = new LoadToLsqIO 254 }) 255 256 val load_s0 = Module(new LoadUnit_S0) 257 val load_s1 = Module(new LoadUnit_S1) 258 val load_s2 = Module(new LoadUnit_S2) 259 260 load_s0.io.in <> io.ldin 261 load_s0.io.dtlbReq <> io.dtlb.req 262 load_s0.io.dcacheReq <> io.dcache.req 263 load_s0.io.rsIdx := io.rsIdx 264 265 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 266 267 load_s1.io.dtlbResp <> io.dtlb.resp 268 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 269 io.dcache.s1_kill <> load_s1.io.dcacheKill 270 load_s1.io.sbuffer <> io.sbuffer 271 load_s1.io.lsq <> io.lsq.forward 272 273 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 274 275 load_s2.io.dcacheResp <> io.dcache.resp 276 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 277 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 278 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 279 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 280 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 281 io.tlbFeedback.bits := RegNext(load_s2.io.tlbFeedback.bits) 282 io.tlbFeedback.valid := RegNext(load_s2.io.tlbFeedback.valid && !load_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 283 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 284 285 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 286 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 287 io.lsq.forward.sqIdxMask := sqIdxMaskReg 288 289 XSDebug(load_s0.io.out.valid, 290 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 291 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 292 XSDebug(load_s1.io.out.valid, 293 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 294 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 295 296 // writeback to LSQ 297 // Current dcache use MSHR 298 // Load queue will be updated at s2 for both hit/miss int/fp load 299 io.lsq.loadIn.valid := load_s2.io.out.valid 300 io.lsq.loadIn.bits := load_s2.io.out.bits 301 302 // write to rob and writeback bus 303 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 304 305 // Int load, if hit, will be writebacked at s2 306 val hitLoadOut = Wire(Valid(new ExuOutput)) 307 hitLoadOut.valid := s2_wb_valid 308 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 309 hitLoadOut.bits.data := load_s2.io.out.bits.data 310 hitLoadOut.bits.redirectValid := false.B 311 hitLoadOut.bits.redirect := DontCare 312 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 313 hitLoadOut.bits.debug.isPerfCnt := false.B 314 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 315 hitLoadOut.bits.fflags := DontCare 316 317 load_s2.io.out.ready := true.B 318 319 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 320 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 321 322 io.lsq.ldout.ready := !hitLoadOut.valid 323 324 when(io.ldout.fire()){ 325 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 326 } 327} 328