1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val loadDataForwarded = Output(Bool()) 16 val needReplayFromRS = Output(Bool()) 17 val forward = new MaskedLoadForwardQueryIO 18} 19 20// Load Pipeline Stage 0 21// Generate addr, use addr to query DCache and DTLB 22class LoadUnit_S0 extends XSModule { 23 val io = IO(new Bundle() { 24 val in = Flipped(Decoupled(new ExuInput)) 25 val out = Decoupled(new LsPipelineBundle) 26 val dtlbReq = DecoupledIO(new TlbReq) 27 val dcacheReq = DecoupledIO(new DCacheWordReq) 28 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 29 val isFirstIssue = Input(Bool()) 30 }) 31 32 val s0_uop = io.in.bits.uop 33 // val s0_vaddr = io.in.bits.src1 + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 34 // val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 35 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 36 val s0_vaddr_lo = io.in.bits.src1(11,0) + Cat(0.U(1.W), imm12) 37 val s0_vaddr_hi = Mux(s0_vaddr_lo(12), 38 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12), io.in.bits.src1(VAddrBits-1, 12)+1.U), 39 Mux(imm12(11), io.in.bits.src1(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src1(VAddrBits-1, 12)), 40 ) 41 val s0_vaddr = Cat(s0_vaddr_hi, s0_vaddr_lo(11,0)) 42 val s0_mask = genWmask(s0_vaddr_lo, s0_uop.ctrl.fuOpType(1,0)) 43 44 // query DTLB 45 io.dtlbReq.valid := io.in.valid 46 io.dtlbReq.bits.vaddr := s0_vaddr 47 io.dtlbReq.bits.cmd := TlbCmd.read 48 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 49 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 50 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 51 52 // query DCache 53 io.dcacheReq.valid := io.in.valid 54 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 55 io.dcacheReq.bits.addr := s0_vaddr 56 io.dcacheReq.bits.mask := s0_mask 57 io.dcacheReq.bits.data := DontCare 58 59 // TODO: update cache meta 60 io.dcacheReq.bits.id := DontCare 61 62 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 63 "b00".U -> true.B, //b 64 "b01".U -> (s0_vaddr(0) === 0.U), //h 65 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 66 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 67 )) 68 69 io.out.valid := io.in.valid && io.dcacheReq.ready 70 71 io.out.bits := DontCare 72 io.out.bits.vaddr := s0_vaddr 73 io.out.bits.mask := s0_mask 74 io.out.bits.uop := s0_uop 75 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 76 io.out.bits.rsIdx := io.rsIdx 77 78 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 79 80 XSDebug(io.dcacheReq.fire(), 81 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 82 ) 83 XSPerfAccumulate("in", io.in.valid) 84 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 85 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 86} 87 88 89// Load Pipeline Stage 1 90// TLB resp (send paddr to dcache) 91class LoadUnit_S1 extends XSModule { 92 val io = IO(new Bundle() { 93 val in = Flipped(Decoupled(new LsPipelineBundle)) 94 val out = Decoupled(new LsPipelineBundle) 95 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 96 val dcachePAddr = Output(UInt(PAddrBits.W)) 97 val dcacheKill = Output(Bool()) 98 val sbuffer = new LoadForwardQueryIO 99 val lsq = new MaskedLoadForwardQueryIO 100 }) 101 102 val s1_uop = io.in.bits.uop 103 val s1_paddr = io.dtlbResp.bits.paddr 104 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 105 val s1_tlb_miss = io.dtlbResp.bits.miss 106 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 107 val s1_mask = io.in.bits.mask 108 109 io.out.bits := io.in.bits // forwardXX field will be updated in s1 110 111 io.dtlbResp.ready := true.B 112 113 // TOOD: PMA check 114 io.dcachePAddr := s1_paddr 115 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 116 117 // load forward query datapath 118 io.sbuffer.valid := io.in.valid 119 io.sbuffer.paddr := s1_paddr 120 io.sbuffer.uop := s1_uop 121 io.sbuffer.sqIdx := s1_uop.sqIdx 122 io.sbuffer.mask := s1_mask 123 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 124 125 io.lsq.valid := io.in.valid 126 io.lsq.paddr := s1_paddr 127 io.lsq.uop := s1_uop 128 io.lsq.sqIdx := s1_uop.sqIdx 129 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 130 io.lsq.mask := s1_mask 131 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 132 133 io.out.valid := io.in.valid// && !s1_tlb_miss 134 io.out.bits.paddr := s1_paddr 135 io.out.bits.mmio := s1_mmio && !s1_exception 136 io.out.bits.tlbMiss := s1_tlb_miss 137 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 138 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 139 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 140 io.out.bits.rsIdx := io.in.bits.rsIdx 141 142 io.in.ready := !io.in.valid || io.out.ready 143 144 XSPerfAccumulate("in", io.in.valid) 145 XSPerfAccumulate("tlb_miss", io.in.valid && s1_tlb_miss) 146 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 147} 148 149 150// Load Pipeline Stage 2 151// DCache resp 152class LoadUnit_S2 extends XSModule with HasLoadHelper { 153 val io = IO(new Bundle() { 154 val in = Flipped(Decoupled(new LsPipelineBundle)) 155 val out = Decoupled(new LsPipelineBundle) 156 val tlbFeedback = ValidIO(new TlbFeedback) 157 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 158 val lsq = new LoadForwardQueryIO 159 val sbuffer = new LoadForwardQueryIO 160 val dataForwarded = Output(Bool()) 161 val needReplayFromRS = Output(Bool()) 162 }) 163 164 val s2_uop = io.in.bits.uop 165 val s2_mask = io.in.bits.mask 166 val s2_paddr = io.in.bits.paddr 167 val s2_tlb_miss = io.in.bits.tlbMiss 168 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 169 val s2_mmio = io.in.bits.mmio && !s2_exception 170 val s2_cache_miss = io.dcacheResp.bits.miss 171 val s2_cache_replay = io.dcacheResp.bits.replay 172 173 io.dcacheResp.ready := true.B 174 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 175 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 176 177 // feedback tlb result to RS 178 io.tlbFeedback.valid := io.in.valid 179 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception) 180 io.tlbFeedback.bits.rsIdx := io.in.bits.rsIdx 181 io.tlbFeedback.bits.flushState := io.in.bits.ptwBack 182 io.needReplayFromRS := s2_cache_replay 183 184 // merge forward result 185 // lsq has higher priority than sbuffer 186 val forwardMask = Wire(Vec(8, Bool())) 187 val forwardData = Wire(Vec(8, UInt(8.W))) 188 189 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 190 io.lsq := DontCare 191 io.sbuffer := DontCare 192 193 // generate XLEN/8 Muxs 194 for (i <- 0 until XLEN / 8) { 195 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 196 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 197 } 198 199 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 200 s2_uop.cf.pc, 201 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 202 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 203 ) 204 205 // data merge 206 val rdataVec = VecInit((0 until XLEN / 8).map(j => 207 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 208 val rdata = rdataVec.asUInt 209 val rdataSel = LookupTree(s2_paddr(2, 0), List( 210 "b000".U -> rdata(63, 0), 211 "b001".U -> rdata(63, 8), 212 "b010".U -> rdata(63, 16), 213 "b011".U -> rdata(63, 24), 214 "b100".U -> rdata(63, 32), 215 "b101".U -> rdata(63, 40), 216 "b110".U -> rdata(63, 48), 217 "b111".U -> rdata(63, 56) 218 )) 219 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 220 221 io.out.valid := io.in.valid && !s2_tlb_miss 222 // Inst will be canceled in store queue / lsq, 223 // so we do not need to care about flush in load / store unit's out.valid 224 io.out.bits := io.in.bits 225 io.out.bits.data := rdataPartialLoad 226 // when exception occurs, set it to not miss and let it write back to roq (via int port) 227 io.out.bits.miss := s2_cache_miss && !s2_exception 228 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 229 io.out.bits.mmio := s2_mmio 230 231 // For timing reasons, we can not let 232 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 233 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 234 // and dcache query is no longer needed. 235 // Such inst will be writebacked from load queue. 236 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception 237 // io.out.bits.forwardX will be send to lq 238 io.out.bits.forwardMask := forwardMask 239 // data retbrived from dcache is also included in io.out.bits.forwardData 240 io.out.bits.forwardData := rdataVec 241 242 io.in.ready := io.out.ready || !io.in.valid 243 244 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 245 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 246 forwardData.asUInt, forwardMask.asUInt 247 ) 248 249 XSPerfAccumulate("in", io.in.valid) 250 XSPerfAccumulate("dcache_miss", io.in.valid && s2_cache_miss) 251 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 252 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 253 XSPerfAccumulate("replay", io.tlbFeedback.valid && !io.tlbFeedback.bits.hit) 254 XSPerfAccumulate("replay_tlb_miss", io.tlbFeedback.valid && !io.tlbFeedback.bits.hit && s2_tlb_miss) 255 XSPerfAccumulate("replay_cache", io.tlbFeedback.valid && !io.tlbFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 256 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 257} 258 259class LoadUnit extends XSModule with HasLoadHelper { 260 val io = IO(new Bundle() { 261 val ldin = Flipped(Decoupled(new ExuInput)) 262 val ldout = Decoupled(new ExuOutput) 263 val redirect = Flipped(ValidIO(new Redirect)) 264 val flush = Input(Bool()) 265 val tlbFeedback = ValidIO(new TlbFeedback) 266 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 267 val isFirstIssue = Input(Bool()) 268 val dcache = new DCacheLoadIO 269 val dtlb = new TlbRequestIO() 270 val sbuffer = new LoadForwardQueryIO 271 val lsq = new LoadToLsqIO 272 val fastUop = ValidIO(new MicroOp) // early wakup signal generated in load_s1 273 }) 274 275 val load_s0 = Module(new LoadUnit_S0) 276 val load_s1 = Module(new LoadUnit_S1) 277 val load_s2 = Module(new LoadUnit_S2) 278 279 load_s0.io.in <> io.ldin 280 load_s0.io.dtlbReq <> io.dtlb.req 281 load_s0.io.dcacheReq <> io.dcache.req 282 load_s0.io.rsIdx := io.rsIdx 283 load_s0.io.isFirstIssue := io.isFirstIssue 284 285 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 286 287 load_s1.io.dtlbResp <> io.dtlb.resp 288 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 289 io.dcache.s1_kill <> load_s1.io.dcacheKill 290 load_s1.io.sbuffer <> io.sbuffer 291 load_s1.io.lsq <> io.lsq.forward 292 293 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 294 295 load_s2.io.dcacheResp <> io.dcache.resp 296 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 297 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 298 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 299 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 300 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 301 io.tlbFeedback.bits := RegNext(load_s2.io.tlbFeedback.bits) 302 io.tlbFeedback.valid := RegNext(load_s2.io.tlbFeedback.valid && !load_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 303 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 304 305 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 306 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 307 io.lsq.forward.sqIdxMask := sqIdxMaskReg 308 309 // // use s2_hit_way to select data received in s1 310 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 311 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 312 313 io.fastUop.valid := io.dcache.s1_hit_way.orR && !io.dcache.s1_disable_fast_wakeup && load_s1.io.in.valid 314 io.fastUop.bits := load_s1.io.out.bits.uop 315 316 XSDebug(load_s0.io.out.valid, 317 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 318 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 319 XSDebug(load_s1.io.out.valid, 320 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 321 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 322 323 // writeback to LSQ 324 // Current dcache use MSHR 325 // Load queue will be updated at s2 for both hit/miss int/fp load 326 io.lsq.loadIn.valid := load_s2.io.out.valid 327 io.lsq.loadIn.bits := load_s2.io.out.bits 328 329 // write to rob and writeback bus 330 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 331 332 // Int load, if hit, will be writebacked at s2 333 val hitLoadOut = Wire(Valid(new ExuOutput)) 334 hitLoadOut.valid := s2_wb_valid 335 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 336 hitLoadOut.bits.data := load_s2.io.out.bits.data 337 hitLoadOut.bits.redirectValid := false.B 338 hitLoadOut.bits.redirect := DontCare 339 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 340 hitLoadOut.bits.debug.isPerfCnt := false.B 341 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 342 hitLoadOut.bits.fflags := DontCare 343 344 load_s2.io.out.ready := true.B 345 346 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 347 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 348 349 io.lsq.ldout.ready := !hitLoadOut.valid 350 351 when(io.ldout.fire()){ 352 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 353 } 354} 355