1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10import xiangshan.backend.fu.fpu.boxF32ToF64 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val forward = new LoadForwardQueryIO 16} 17 18// Load Pipeline Stage 0 19// Generate addr, use addr to query DCache and DTLB 20class LoadUnit_S0 extends XSModule { 21 val io = IO(new Bundle() { 22 val in = Flipped(Decoupled(new ExuInput)) 23 val out = Decoupled(new LsPipelineBundle) 24 val redirect = Flipped(ValidIO(new Redirect)) 25 val dtlbReq = DecoupledIO(new TlbReq) 26 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 27 val tlbFeedback = ValidIO(new TlbFeedback) 28 val dcacheReq = DecoupledIO(new DCacheLoadReq) 29 }) 30 31 val s0_uop = io.in.bits.uop 32 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 33 val s0_paddr = io.dtlbResp.bits.paddr 34 val s0_tlb_miss = io.dtlbResp.bits.miss 35 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 36 37 // query DTLB 38 io.dtlbReq.valid := io.out.valid 39 io.dtlbReq.bits.vaddr := s0_vaddr 40 io.dtlbReq.bits.cmd := TlbCmd.read 41 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 42 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 43 io.dtlbResp.ready := io.out.ready // TODO: check it: io.out.fire()? 44 45 // feedback tlb result to RS 46 // Note: can be moved to s1 47 io.tlbFeedback.valid := io.out.valid 48 io.tlbFeedback.bits.hit := !s0_tlb_miss 49 io.tlbFeedback.bits.roqIdx := s0_uop.roqIdx 50 51 // query DCache 52 io.dcacheReq.valid := io.in.valid && !s0_uop.roqIdx.needFlush(io.redirect) 53 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 54 io.dcacheReq.bits.addr := s0_vaddr 55 io.dcacheReq.bits.mask := s0_mask 56 io.dcacheReq.bits.data := DontCare 57 58 // TODO: update cache meta 59 io.dcacheReq.bits.meta.id := DontCare 60 io.dcacheReq.bits.meta.vaddr := s0_vaddr 61 io.dcacheReq.bits.meta.paddr := DontCare 62 io.dcacheReq.bits.meta.uop := s0_uop 63 io.dcacheReq.bits.meta.mmio := false.B 64 io.dcacheReq.bits.meta.tlb_miss := false.B 65 io.dcacheReq.bits.meta.mask := s0_mask 66 io.dcacheReq.bits.meta.replay := false.B 67 68 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 69 "b00".U -> true.B, //b 70 "b01".U -> (s0_vaddr(0) === 0.U), //h 71 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 72 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 73 )) 74 75 io.out.valid := io.dcacheReq.fire() && // dcache may not accept load request 76 !io.in.bits.uop.roqIdx.needFlush(io.redirect) 77 io.out.bits := DontCare 78 io.out.bits.vaddr := s0_vaddr 79 io.out.bits.paddr := s0_paddr 80 io.out.bits.tlbMiss := io.dtlbResp.bits.miss 81 io.out.bits.mask := s0_mask 82 io.out.bits.uop := s0_uop 83 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 84 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 85 86 io.in.ready := io.out.fire() 87 88 XSDebug(io.dcacheReq.fire(), "[DCACHE LOAD REQ] pc %x vaddr %x paddr will be %x\n", 89 s0_uop.cf.pc, s0_vaddr, s0_paddr 90 ) 91} 92 93 94// Load Pipeline Stage 1 95// TLB resp (send paddr to dcache) 96class LoadUnit_S1 extends XSModule { 97 val io = IO(new Bundle() { 98 val in = Flipped(Decoupled(new LsPipelineBundle)) 99 val out = Decoupled(new LsPipelineBundle) 100 val redirect = Flipped(ValidIO(new Redirect)) 101 val s1_paddr = Output(UInt(PAddrBits.W)) 102 val sbuffer = new LoadForwardQueryIO 103 val lsq = new LoadForwardQueryIO 104 }) 105 106 val s1_uop = io.in.bits.uop 107 val s1_paddr = io.in.bits.paddr 108 val s1_tlb_miss = io.in.bits.tlbMiss 109 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) && !io.out.bits.uop.cf.exceptionVec.asUInt.orR 110 val s1_mask = io.in.bits.mask 111 112 io.out.bits := io.in.bits // forwardXX field will be updated in s1 113 io.s1_paddr := s1_paddr 114 115 // load forward query datapath 116 io.sbuffer.valid := io.in.valid 117 io.sbuffer.paddr := s1_paddr 118 io.sbuffer.uop := s1_uop 119 io.sbuffer.sqIdx := s1_uop.sqIdx 120 io.sbuffer.mask := s1_mask 121 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 122 123 io.lsq.valid := io.in.valid 124 io.lsq.paddr := s1_paddr 125 io.lsq.uop := s1_uop 126 io.lsq.sqIdx := s1_uop.sqIdx 127 io.lsq.mask := s1_mask 128 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 129 130 io.out.bits.forwardMask := io.sbuffer.forwardMask 131 io.out.bits.forwardData := io.sbuffer.forwardData 132 133 io.out.valid := io.in.valid && !s1_tlb_miss && !s1_uop.roqIdx.needFlush(io.redirect) 134 io.out.bits.paddr := s1_paddr 135 io.out.bits.mmio := s1_mmio 136 io.out.bits.tlbMiss := s1_tlb_miss 137 138 io.in.ready := io.out.ready || !io.in.valid 139 140} 141 142 143// Load Pipeline Stage 2 144// DCache resp 145class LoadUnit_S2 extends XSModule with HasLoadHelper { 146 val io = IO(new Bundle() { 147 val in = Flipped(Decoupled(new LsPipelineBundle)) 148 val out = Decoupled(new LsPipelineBundle) 149 val redirect = Flipped(ValidIO(new Redirect)) 150 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 151 val lsq = new LoadForwardQueryIO 152 }) 153 154 val s2_uop = io.in.bits.uop 155 val s2_mask = io.in.bits.mask 156 val s2_paddr = io.in.bits.paddr 157 val s2_cache_miss = io.dcacheResp.bits.miss 158 val s2_cache_nack = io.dcacheResp.bits.nack 159 160 161 io.dcacheResp.ready := true.B 162 assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost") 163 164 val forwardMask = io.out.bits.forwardMask 165 val forwardData = io.out.bits.forwardData 166 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 167 168 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 169 s2_uop.cf.pc, 170 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 171 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 172 ) 173 174 // data merge 175 val rdata = VecInit((0 until XLEN / 8).map(j => 176 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 177 val rdataSel = LookupTree(s2_paddr(2, 0), List( 178 "b000".U -> rdata(63, 0), 179 "b001".U -> rdata(63, 8), 180 "b010".U -> rdata(63, 16), 181 "b011".U -> rdata(63, 24), 182 "b100".U -> rdata(63, 32), 183 "b101".U -> rdata(63, 40), 184 "b110".U -> rdata(63, 48), 185 "b111".U -> rdata(63, 56) 186 )) 187 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 188 189 // TODO: ECC check 190 191 io.out.valid := io.in.valid // && !s2_uop.needFlush(io.redirect) will cause comb. loop 192 // Inst will be canceled in store queue / lsq, 193 // so we do not need to care about flush in load / store unit's out.valid 194 io.out.bits := io.in.bits 195 io.out.bits.data := rdataPartialLoad 196 io.out.bits.miss := (s2_cache_miss || s2_cache_nack) && !fullForward 197 io.out.bits.mmio := io.in.bits.mmio 198 199 io.in.ready := io.out.ready || !io.in.valid 200 201 // merge forward result 202 io.lsq := DontCare 203 // generate XLEN/8 Muxs 204 for (i <- 0 until XLEN / 8) { 205 when(io.lsq.forwardMask(i)) { 206 io.out.bits.forwardMask(i) := true.B 207 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 208 } 209 } 210 211 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 212 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 213 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 214 ) 215 216} 217 218// class LoadUnit_S3 extends XSModule { 219// val io = IO(new Bundle() { 220// val in = Flipped(Decoupled(new LsPipelineBundle)) 221// val out = Decoupled(new LsPipelineBundle) 222// val redirect = Flipped(ValidIO(new Redirect)) 223// }) 224 225// io.in.ready := true.B 226// io.out.bits := io.in.bits 227// io.out.valid := io.in.valid && !io.out.bits.uop.roqIdx.needFlush(io.redirect) 228// } 229 230class LoadUnit extends XSModule { 231 val io = IO(new Bundle() { 232 val ldin = Flipped(Decoupled(new ExuInput)) 233 val ldout = Decoupled(new ExuOutput) 234 val redirect = Flipped(ValidIO(new Redirect)) 235 val tlbFeedback = ValidIO(new TlbFeedback) 236 val dcache = new DCacheLoadIO 237 val dtlb = new TlbRequestIO() 238 val sbuffer = new LoadForwardQueryIO 239 val lsq = new LoadToLsqIO 240 }) 241 242 val load_s0 = Module(new LoadUnit_S0) 243 val load_s1 = Module(new LoadUnit_S1) 244 val load_s2 = Module(new LoadUnit_S2) 245 // val load_s3 = Module(new LoadUnit_S3) 246 247 load_s0.io.in <> io.ldin 248 load_s0.io.redirect <> io.redirect 249 load_s0.io.dtlbReq <> io.dtlb.req 250 load_s0.io.dtlbResp <> io.dtlb.resp 251 load_s0.io.dcacheReq <> io.dcache.req 252 load_s0.io.tlbFeedback <> io.tlbFeedback 253 254 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, false.B) 255 256 io.dcache.s1_paddr := load_s1.io.out.bits.paddr 257 load_s1.io.redirect <> io.redirect 258 io.dcache.s1_kill := DontCare // FIXME 259 io.sbuffer <> load_s1.io.sbuffer 260 io.lsq.forward <> load_s1.io.lsq 261 262 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, false.B) 263 264 load_s2.io.redirect <> io.redirect 265 load_s2.io.dcacheResp <> io.dcache.resp 266 load_s2.io.lsq := DontCare 267 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 268 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 269 270 // PipelineConnect(load_s2.io.fp_out, load_s3.io.in, true.B, false.B) 271 // load_s3.io.redirect <> io.redirect 272 273 XSDebug(load_s0.io.out.valid, 274 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 275 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 276 XSDebug(load_s1.io.out.valid, 277 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 278 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 279 280 // writeback to LSQ 281 // Current dcache use MSHR 282 io.lsq.loadIn.valid := load_s2.io.out.valid 283 io.lsq.loadIn.bits := load_s2.io.out.bits 284 285 val hitLoadOut = Wire(Valid(new ExuOutput)) 286 hitLoadOut.valid := load_s2.io.out.valid && (!load_s2.io.out.bits.miss || load_s2.io.out.bits.uop.cf.exceptionVec.asUInt.orR) 287 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 288 hitLoadOut.bits.data := load_s2.io.out.bits.data 289 hitLoadOut.bits.redirectValid := false.B 290 hitLoadOut.bits.redirect := DontCare 291 hitLoadOut.bits.brUpdate := DontCare 292 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 293 hitLoadOut.bits.fflags := DontCare 294 295 // TODO: arbiter 296 // if hit, writeback result to CDB 297 // val ldout = Vec(2, Decoupled(new ExuOutput)) 298 // when io.loadIn(i).fire() && !io.io.loadIn(i).miss, commit load to cdb 299 // val cdbArb = Module(new Arbiter(new ExuOutput, 2)) 300 // io.ldout <> cdbArb.io.out 301 // hitLoadOut <> cdbArb.io.in(0) 302 // io.lsq.ldout <> cdbArb.io.in(1) // missLoadOut 303 load_s2.io.out.ready := true.B 304 io.lsq.ldout.ready := !hitLoadOut.valid 305 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 306 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 307 308 when(io.ldout.fire()){ 309 XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen) 310 } 311}