1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10 11class LoadToLsroqIO extends XSBundle { 12 val loadIn = ValidIO(new LsPipelineBundle) 13 val ldout = Flipped(DecoupledIO(new ExuOutput)) 14 val forward = new LoadForwardQueryIO 15} 16 17// Load Pipeline Stage 0 18// Generate addr, use addr to query DCache and DTLB 19class LoadUnit_S0 extends XSModule { 20 val io = IO(new Bundle() { 21 val in = Flipped(Decoupled(new ExuInput)) 22 val out = Decoupled(new LsPipelineBundle) 23 val redirect = Flipped(ValidIO(new Redirect)) 24 val dtlbReq = DecoupledIO(new TlbReq) 25 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 26 val tlbFeedback = ValidIO(new TlbFeedback) 27 val dcacheReq = DecoupledIO(new DCacheLoadReq) 28 }) 29 30 val s0_uop = io.in.bits.uop 31 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 32 val s0_paddr = io.dtlbResp.bits.paddr 33 val s0_tlb_miss = io.dtlbResp.bits.miss 34 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 35 36 // query DTLB 37 io.dtlbReq.valid := io.out.valid 38 io.dtlbReq.bits.vaddr := s0_vaddr 39 io.dtlbReq.bits.cmd := TlbCmd.read 40 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 41 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 42 io.dtlbReq.bits.debug.lsroqIdx := s0_uop.lsroqIdx 43 io.dtlbResp.ready := io.out.ready 44 // FIXME: tlb change to DecoupledIO, need to fix tlb's usage 45 46 // feedback tlb result to RS 47 // Note: can be moved to s1 48 io.tlbFeedback.valid := io.out.valid 49 io.tlbFeedback.bits.hit := !s0_tlb_miss 50 io.tlbFeedback.bits.roqIdx := s0_uop.roqIdx 51 52 // query DCache 53 io.dcacheReq.valid := io.in.valid && !s0_uop.roqIdx.needFlush(io.redirect) 54 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 55 io.dcacheReq.bits.addr := s0_vaddr 56 io.dcacheReq.bits.mask := s0_mask 57 io.dcacheReq.bits.data := DontCare 58 59 // TODO: update cache meta 60 io.dcacheReq.bits.meta.id := DontCare 61 io.dcacheReq.bits.meta.vaddr := s0_vaddr 62 io.dcacheReq.bits.meta.paddr := DontCare 63 io.dcacheReq.bits.meta.uop := s0_uop 64 io.dcacheReq.bits.meta.mmio := false.B 65 io.dcacheReq.bits.meta.tlb_miss := false.B 66 io.dcacheReq.bits.meta.mask := s0_mask 67 io.dcacheReq.bits.meta.replay := false.B 68 69 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 70 "b00".U -> true.B, //b 71 "b01".U -> (s0_vaddr(0) === 0.U), //h 72 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 73 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 74 )) 75 76 io.out.valid := io.dcacheReq.fire() // dcache may not accept load request 77 io.out.bits := DontCare 78 io.out.bits.vaddr := s0_vaddr 79 io.out.bits.paddr := s0_paddr 80 io.out.bits.tlbMiss := io.dtlbResp.bits.miss 81 io.out.bits.mask := s0_mask 82 io.out.bits.uop := s0_uop 83 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 84 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 85 86 io.in.ready := io.out.fire() 87 88 XSDebug(io.dcacheReq.fire(), "[DCACHE LOAD REQ] pc %x vaddr %x paddr will be %x\n", 89 s0_uop.cf.pc, s0_vaddr, s0_paddr 90 ) 91} 92 93 94// Load Pipeline Stage 1 95// TLB resp (send paddr to dcache) 96class LoadUnit_S1 extends XSModule { 97 val io = IO(new Bundle() { 98 val in = Flipped(Decoupled(new LsPipelineBundle)) 99 val out = Decoupled(new LsPipelineBundle) 100 val redirect = Flipped(ValidIO(new Redirect)) 101 val s1_paddr = Output(UInt(PAddrBits.W)) 102 val sbuffer = new LoadForwardQueryIO 103 val lsroq = new LoadForwardQueryIO 104 }) 105 106 val s1_uop = io.in.bits.uop 107 val s1_paddr = io.in.bits.paddr 108 val s1_tlb_miss = io.in.bits.tlbMiss 109 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) 110 val s1_mask = io.in.bits.mask 111 112 io.out.bits := io.in.bits // forwardXX field will be updated in s1 113 io.s1_paddr := s1_paddr 114 115 // load forward query datapath 116 io.sbuffer.valid := io.in.valid 117 io.sbuffer.paddr := s1_paddr 118 io.sbuffer.uop := s1_uop 119 io.sbuffer.sqIdx := s1_uop.sqIdx 120 io.sbuffer.lsroqIdx := s1_uop.lsroqIdx 121 io.sbuffer.mask := s1_mask 122 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 123 124 io.lsroq.valid := io.in.valid 125 io.lsroq.paddr := s1_paddr 126 io.lsroq.uop := s1_uop 127 io.lsroq.sqIdx := s1_uop.sqIdx 128 io.lsroq.lsroqIdx := s1_uop.lsroqIdx 129 io.lsroq.mask := s1_mask 130 io.lsroq.pc := s1_uop.cf.pc // FIXME: remove it 131 132 io.out.bits.forwardMask := io.sbuffer.forwardMask 133 io.out.bits.forwardData := io.sbuffer.forwardData 134 // generate XLEN/8 Muxs 135 for (i <- 0 until XLEN / 8) { 136 when(io.lsroq.forwardMask(i)) { 137 io.out.bits.forwardMask(i) := true.B 138 io.out.bits.forwardData(i) := io.lsroq.forwardData(i) 139 } 140 } 141 142 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 143 s1_uop.cf.pc, 144 io.lsroq.forwardData.asUInt, io.lsroq.forwardMask.asUInt, 145 io.sbuffer.forwardData.asUInt, io.sbuffer.forwardMask.asUInt 146 ) 147 148 io.out.valid := io.in.valid && !s1_tlb_miss && !s1_uop.roqIdx.needFlush(io.redirect) 149 io.out.bits.paddr := s1_paddr 150 io.out.bits.mmio := s1_mmio 151 io.out.bits.tlbMiss := s1_tlb_miss 152 153 io.in.ready := io.out.ready || !io.in.valid 154 155} 156 157 158// Load Pipeline Stage 2 159// DCache resp 160class LoadUnit_S2 extends XSModule { 161 val io = IO(new Bundle() { 162 val in = Flipped(Decoupled(new LsPipelineBundle)) 163 val out = Decoupled(new LsPipelineBundle) 164 val redirect = Flipped(ValidIO(new Redirect)) 165 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 166 }) 167 168 val s2_uop = io.in.bits.uop 169 val s2_mask = io.in.bits.mask 170 val s2_paddr = io.in.bits.paddr 171 val s2_cache_miss = io.dcacheResp.bits.miss 172 val s2_cache_nack = io.dcacheResp.bits.nack 173 174 175 io.dcacheResp.ready := true.B 176 assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost") 177 178 val forwardMask = io.in.bits.forwardMask 179 val forwardData = io.in.bits.forwardData 180 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 181 182 // data merge 183 val rdata = VecInit((0 until XLEN / 8).map(j => 184 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 185 val rdataSel = LookupTree(s2_paddr(2, 0), List( 186 "b000".U -> rdata(63, 0), 187 "b001".U -> rdata(63, 8), 188 "b010".U -> rdata(63, 16), 189 "b011".U -> rdata(63, 24), 190 "b100".U -> rdata(63, 32), 191 "b101".U -> rdata(63, 40), 192 "b110".U -> rdata(63, 48), 193 "b111".U -> rdata(63, 56) 194 )) 195 val rdataPartialLoad = LookupTree(s2_uop.ctrl.fuOpType, List( 196 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 197 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 198 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 199 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 200 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 201 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 202 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN) 203 )) 204 205 // TODO: ECC check 206 207 io.out.valid := io.in.valid // && !s2_uop.needFlush(io.redirect) will cause comb. loop 208 // Inst will be canceled in store queue / lsroq, 209 // so we do not need to care about flush in load / store unit's out.valid 210 io.out.bits := io.in.bits 211 io.out.bits.data := rdataPartialLoad 212 io.out.bits.miss := (s2_cache_miss || s2_cache_nack) && !fullForward 213 io.out.bits.mmio := io.in.bits.mmio 214 215 io.in.ready := io.out.ready || !io.in.valid 216 217 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 218 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 219 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 220 ) 221 222} 223 224 225class LoadUnit extends XSModule { 226 val io = IO(new Bundle() { 227 val ldin = Flipped(Decoupled(new ExuInput)) 228 val ldout = Decoupled(new ExuOutput) 229 val redirect = Flipped(ValidIO(new Redirect)) 230 val tlbFeedback = ValidIO(new TlbFeedback) 231 val dcache = new DCacheLoadIO 232 val dtlb = new TlbRequestIO() 233 val sbuffer = new LoadForwardQueryIO 234 val lsroq = new LoadToLsroqIO 235 }) 236 237 val load_s0 = Module(new LoadUnit_S0) 238 val load_s1 = Module(new LoadUnit_S1) 239 val load_s2 = Module(new LoadUnit_S2) 240 241 load_s0.io.in <> io.ldin 242 load_s0.io.redirect <> io.redirect 243 load_s0.io.dtlbReq <> io.dtlb.req 244 load_s0.io.dtlbResp <> io.dtlb.resp 245 load_s0.io.dcacheReq <> io.dcache.req 246 load_s0.io.tlbFeedback <> io.tlbFeedback 247 248 PipelineConnect(load_s0.io.out, load_s1.io.in, load_s1.io.out.fire() || load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect), false.B) 249 250 io.dcache.s1_paddr := load_s1.io.out.bits.paddr 251 load_s1.io.redirect <> io.redirect 252 io.dcache.s1_kill := DontCare // FIXME 253 io.sbuffer <> load_s1.io.sbuffer 254 io.lsroq.forward <> load_s1.io.lsroq 255 256 PipelineConnect(load_s1.io.out, load_s2.io.in, load_s2.io.out.fire() || load_s1.io.out.bits.tlbMiss, false.B) 257 258 load_s2.io.redirect <> io.redirect 259 load_s2.io.dcacheResp <> io.dcache.resp 260 261 XSDebug(load_s0.io.out.valid, 262 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 263 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 264 XSDebug(load_s1.io.out.valid, 265 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 266 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 267 268 // writeback to LSROQ 269 // Current dcache use MSHR 270 io.lsroq.loadIn.valid := load_s2.io.out.valid 271 io.lsroq.loadIn.bits := load_s2.io.out.bits 272 273 val hitLoadOut = Wire(Valid(new ExuOutput)) 274 hitLoadOut.valid := load_s2.io.out.valid && !load_s2.io.out.bits.miss 275 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 276 hitLoadOut.bits.data := load_s2.io.out.bits.data 277 hitLoadOut.bits.redirectValid := false.B 278 hitLoadOut.bits.redirect := DontCare 279 hitLoadOut.bits.brUpdate := DontCare 280 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 281 282 // TODO: arbiter 283 // if hit, writeback result to CDB 284 // val ldout = Vec(2, Decoupled(new ExuOutput)) 285 // when io.loadIn(i).fire() && !io.io.loadIn(i).miss, commit load to cdb 286 // val cdbArb = Module(new Arbiter(new ExuOutput, 2)) 287 // io.ldout <> cdbArb.io.out 288 // hitLoadOut <> cdbArb.io.in(0) 289 // io.lsroq.ldout <> cdbArb.io.in(1) // missLoadOut 290 load_s2.io.out.ready := true.B 291 io.lsroq.ldout.ready := !hitLoadOut.valid 292 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsroq.ldout.bits) 293 io.ldout.valid := hitLoadOut.valid || io.lsroq.ldout.valid 294 295 when(io.ldout.fire()){ 296 XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen) 297 } 298} 299