1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.ImmUnion 8import xiangshan.cache._ 9// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 10import xiangshan.backend.LSUOpType 11 12class LoadToLsqIO extends XSBundle { 13 val loadIn = ValidIO(new LsPipelineBundle) 14 val ldout = Flipped(DecoupledIO(new ExuOutput)) 15 val loadDataForwarded = Output(Bool()) 16 val forward = new LoadForwardQueryIO 17} 18 19// Load Pipeline Stage 0 20// Generate addr, use addr to query DCache and DTLB 21class LoadUnit_S0 extends XSModule { 22 val io = IO(new Bundle() { 23 val in = Flipped(Decoupled(new ExuInput)) 24 val out = Decoupled(new LsPipelineBundle) 25 val dtlbReq = DecoupledIO(new TlbReq) 26 val dcacheReq = DecoupledIO(new DCacheWordReq) 27 }) 28 29 val s0_uop = io.in.bits.uop 30 val s0_vaddr = io.in.bits.src1 + SignExt(ImmUnion.I.toImm32(s0_uop.ctrl.imm), XLEN) 31 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 32 33 // query DTLB 34 io.dtlbReq.valid := io.in.valid 35 io.dtlbReq.bits.vaddr := s0_vaddr 36 io.dtlbReq.bits.cmd := TlbCmd.read 37 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 38 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 39 40 // query DCache 41 io.dcacheReq.valid := io.in.valid 42 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 43 io.dcacheReq.bits.addr := s0_vaddr 44 io.dcacheReq.bits.mask := s0_mask 45 io.dcacheReq.bits.data := DontCare 46 47 // TODO: update cache meta 48 io.dcacheReq.bits.id := DontCare 49 50 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 51 "b00".U -> true.B, //b 52 "b01".U -> (s0_vaddr(0) === 0.U), //h 53 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 54 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 55 )) 56 57 io.out.valid := io.in.valid && io.dcacheReq.ready 58 59 io.out.bits := DontCare 60 io.out.bits.vaddr := s0_vaddr 61 io.out.bits.mask := s0_mask 62 io.out.bits.uop := s0_uop 63 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 64 65 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 66 67 XSDebug(io.dcacheReq.fire(), 68 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 69 ) 70} 71 72 73// Load Pipeline Stage 1 74// TLB resp (send paddr to dcache) 75class LoadUnit_S1 extends XSModule { 76 val io = IO(new Bundle() { 77 val in = Flipped(Decoupled(new LsPipelineBundle)) 78 val out = Decoupled(new LsPipelineBundle) 79 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 80 val dcachePAddr = Output(UInt(PAddrBits.W)) 81 val dcacheKill = Output(Bool()) 82 val sbuffer = new LoadForwardQueryIO 83 val lsq = new LoadForwardQueryIO 84 }) 85 86 val s1_uop = io.in.bits.uop 87 val s1_paddr = io.dtlbResp.bits.paddr 88 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 89 val s1_tlb_miss = io.dtlbResp.bits.miss 90 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 91 val s1_mask = io.in.bits.mask 92 93 io.out.bits := io.in.bits // forwardXX field will be updated in s1 94 95 io.dtlbResp.ready := true.B 96 97 // TOOD: PMA check 98 io.dcachePAddr := s1_paddr 99 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 100 101 // load forward query datapath 102 io.sbuffer.valid := io.in.valid 103 io.sbuffer.paddr := s1_paddr 104 io.sbuffer.uop := s1_uop 105 io.sbuffer.sqIdx := s1_uop.sqIdx 106 io.sbuffer.mask := s1_mask 107 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 108 109 io.lsq.valid := io.in.valid 110 io.lsq.paddr := s1_paddr 111 io.lsq.uop := s1_uop 112 io.lsq.sqIdx := s1_uop.sqIdx 113 io.lsq.mask := s1_mask 114 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 115 116 io.out.valid := io.in.valid// && !s1_tlb_miss 117 io.out.bits.paddr := s1_paddr 118 io.out.bits.mmio := s1_mmio && !s1_exception 119 io.out.bits.tlbMiss := s1_tlb_miss 120 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 121 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 122 123 io.in.ready := !io.in.valid || io.out.ready 124 125} 126 127 128// Load Pipeline Stage 2 129// DCache resp 130class LoadUnit_S2 extends XSModule with HasLoadHelper { 131 val io = IO(new Bundle() { 132 val in = Flipped(Decoupled(new LsPipelineBundle)) 133 val out = Decoupled(new LsPipelineBundle) 134 val tlbFeedback = ValidIO(new TlbFeedback) 135 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 136 val lsq = new LoadForwardQueryIO 137 val sbuffer = new LoadForwardQueryIO 138 val dataForwarded = Output(Bool()) 139 }) 140 141 val s2_uop = io.in.bits.uop 142 val s2_mask = io.in.bits.mask 143 val s2_paddr = io.in.bits.paddr 144 val s2_tlb_miss = io.in.bits.tlbMiss 145 val s2_mmio = io.in.bits.mmio 146 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 147 val s2_cache_miss = io.dcacheResp.bits.miss 148 val s2_cache_replay = io.dcacheResp.bits.replay 149 150 io.dcacheResp.ready := true.B 151 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 152 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 153 154 // feedback tlb result to RS 155 io.tlbFeedback.valid := io.in.valid 156 io.tlbFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 157 io.tlbFeedback.bits.roqIdx := s2_uop.roqIdx 158 159 val forwardMask = io.out.bits.forwardMask 160 val forwardData = io.out.bits.forwardData 161 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 162 163 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 164 s2_uop.cf.pc, 165 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 166 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 167 ) 168 169 // data merge 170 val rdata = VecInit((0 until XLEN / 8).map(j => 171 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 172 val rdataSel = LookupTree(s2_paddr(2, 0), List( 173 "b000".U -> rdata(63, 0), 174 "b001".U -> rdata(63, 8), 175 "b010".U -> rdata(63, 16), 176 "b011".U -> rdata(63, 24), 177 "b100".U -> rdata(63, 32), 178 "b101".U -> rdata(63, 40), 179 "b110".U -> rdata(63, 48), 180 "b111".U -> rdata(63, 56) 181 )) 182 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 183 184 // TODO: ECC check 185 186 io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio) 187 // Inst will be canceled in store queue / lsq, 188 // so we do not need to care about flush in load / store unit's out.valid 189 io.out.bits := io.in.bits 190 io.out.bits.data := rdataPartialLoad 191 // when exception occurs, set it to not miss and let it write back to roq (via int port) 192 io.out.bits.miss := s2_cache_miss && !s2_exception 193 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 194 io.out.bits.mmio := s2_mmio 195 196 // For timing reasons, we can not let 197 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 198 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 199 // and dcache query is no longer needed. 200 // Such inst will be writebacked from load queue. 201 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception 202 203 io.in.ready := io.out.ready || !io.in.valid 204 205 // merge forward result 206 // lsq has higher priority than sbuffer 207 io.lsq := DontCare 208 io.sbuffer := DontCare 209 // generate XLEN/8 Muxs 210 for (i <- 0 until XLEN / 8) { 211 when (io.sbuffer.forwardMask(i)) { 212 io.out.bits.forwardMask(i) := true.B 213 io.out.bits.forwardData(i) := io.sbuffer.forwardData(i) 214 } 215 when (io.lsq.forwardMask(i)) { 216 io.out.bits.forwardMask(i) := true.B 217 io.out.bits.forwardData(i) := io.lsq.forwardData(i) 218 } 219 } 220 221 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 222 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 223 io.out.bits.forwardData.asUInt, io.out.bits.forwardMask.asUInt 224 ) 225} 226 227class LoadUnit extends XSModule with HasLoadHelper { 228 val io = IO(new Bundle() { 229 val ldin = Flipped(Decoupled(new ExuInput)) 230 val ldout = Decoupled(new ExuOutput) 231 val fpout = Decoupled(new ExuOutput) 232 val redirect = Flipped(ValidIO(new Redirect)) 233 val tlbFeedback = ValidIO(new TlbFeedback) 234 val dcache = new DCacheLoadIO 235 val dtlb = new TlbRequestIO() 236 val sbuffer = new LoadForwardQueryIO 237 val lsq = new LoadToLsqIO 238 }) 239 240 val load_s0 = Module(new LoadUnit_S0) 241 val load_s1 = Module(new LoadUnit_S1) 242 val load_s2 = Module(new LoadUnit_S2) 243 244 load_s0.io.in <> io.ldin 245 load_s0.io.dtlbReq <> io.dtlb.req 246 load_s0.io.dcacheReq <> io.dcache.req 247 248 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 249 250 load_s1.io.dtlbResp <> io.dtlb.resp 251 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 252 io.dcache.s1_kill <> load_s1.io.dcacheKill 253 load_s1.io.sbuffer <> io.sbuffer 254 load_s1.io.lsq <> io.lsq.forward 255 256 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect)) 257 258 load_s2.io.tlbFeedback <> io.tlbFeedback 259 load_s2.io.dcacheResp <> io.dcache.resp 260 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 261 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 262 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 263 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 264 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 265 266 XSDebug(load_s0.io.out.valid, 267 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 268 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 269 XSDebug(load_s1.io.out.valid, 270 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 271 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 272 273 // writeback to LSQ 274 // Current dcache use MSHR 275 // Load queue will be updated at s2 for both hit/miss int/fp load 276 io.lsq.loadIn.valid := load_s2.io.out.valid 277 io.lsq.loadIn.bits := load_s2.io.out.bits 278 279 // write to rob and writeback bus 280 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss 281 val refillFpLoad = io.lsq.ldout.bits.uop.ctrl.fpWen 282 283 // Int load, if hit, will be writebacked at s2 284 val intHitLoadOut = Wire(Valid(new ExuOutput)) 285 intHitLoadOut.valid := s2_wb_valid && !load_s2.io.out.bits.uop.ctrl.fpWen 286 intHitLoadOut.bits.uop := load_s2.io.out.bits.uop 287 intHitLoadOut.bits.data := load_s2.io.out.bits.data 288 intHitLoadOut.bits.redirectValid := false.B 289 intHitLoadOut.bits.redirect := DontCare 290 intHitLoadOut.bits.brUpdate := DontCare 291 intHitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 292 intHitLoadOut.bits.debug.isPerfCnt := false.B 293 intHitLoadOut.bits.fflags := DontCare 294 295 load_s2.io.out.ready := true.B 296 297 io.ldout.bits := Mux(intHitLoadOut.valid, intHitLoadOut.bits, io.lsq.ldout.bits) 298 io.ldout.valid := intHitLoadOut.valid || io.lsq.ldout.valid && !refillFpLoad 299 300 // Fp load, if hit, will be send to recoder at s2, then it will be recoded & writebacked at s3 301 val fpHitLoadOut = Wire(Valid(new ExuOutput)) 302 fpHitLoadOut.valid := s2_wb_valid && load_s2.io.out.bits.uop.ctrl.fpWen 303 fpHitLoadOut.bits := intHitLoadOut.bits 304 305 val fpLoadOut = Wire(Valid(new ExuOutput)) 306 fpLoadOut.bits := Mux(fpHitLoadOut.valid, fpHitLoadOut.bits, io.lsq.ldout.bits) 307 fpLoadOut.valid := fpHitLoadOut.valid || io.lsq.ldout.valid && refillFpLoad 308 309 val fpLoadOutReg = RegNext(fpLoadOut) 310 io.fpout.bits := fpLoadOutReg.bits 311 io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode 312 io.fpout.valid := RegNext(fpLoadOut.valid) 313 314 io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid) 315 316 when(io.ldout.fire()){ 317 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 318 } 319 320 when(io.fpout.fire()){ 321 XSDebug("fpout %x\n", io.fpout.bits.uop.cf.pc) 322 } 323} 324