1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8// import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants, TlbReq, DCacheLoadReq, DCacheWordResp} 9import xiangshan.backend.LSUOpType 10 11class LoadToLsroqIO extends XSBundle { 12 val loadIn = ValidIO(new LsPipelineBundle) 13 val ldout = Flipped(DecoupledIO(new ExuOutput)) 14 val forward = new LoadForwardQueryIO 15} 16 17// Load Pipeline Stage 0 18// Generate addr, use addr to query DCache and DTLB 19class LoadUnit_S0 extends XSModule { 20 val io = IO(new Bundle() { 21 val in = Flipped(Decoupled(new ExuInput)) 22 val out = Decoupled(new LsPipelineBundle) 23 val redirect = Flipped(ValidIO(new Redirect)) 24 val dtlbReq = Valid(new TlbReq) 25 val dcacheReq = DecoupledIO(new DCacheLoadReq) 26 }) 27 28 val s0_uop = io.in.bits.uop 29 val s0_vaddr = io.in.bits.src1 + s0_uop.ctrl.imm 30 val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 31 32 // query DTLB 33 io.dtlbReq.valid := io.out.valid 34 io.dtlbReq.bits.vaddr := s0_vaddr 35 io.dtlbReq.bits.cmd := TlbCmd.read 36 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 37 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 38 io.dtlbReq.bits.debug.lsroqIdx := s0_uop.lsroqIdx 39 40 // query DCache 41 io.dcacheReq.valid := io.out.valid 42 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 43 io.dcacheReq.bits.addr := s0_vaddr 44 io.dcacheReq.bits.mask := s0_mask 45 46 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 47 "b00".U -> true.B, //b 48 "b01".U -> (s0_vaddr(0) === 0.U), //h 49 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 50 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 51 )) 52 53 io.out.valid := io.in.valid && !s0_uop.needFlush(io.redirect) 54 io.out.bits := DontCare 55 io.out.bits.vaddr := s0_vaddr 56 io.out.bits.mask := s0_mask 57 io.out.bits.uop := s0_uop 58 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 59 60 io.in.ready := io.out.ready 61} 62 63 64// Load Pipeline Stage 1 65// TLB resp (send paddr to dcache) 66class LoadUnit_S1 extends XSModule { 67 val io = IO(new Bundle() { 68 val in = Flipped(Decoupled(new LsPipelineBundle)) 69 val out = Decoupled(new LsPipelineBundle) 70 val redirect = Flipped(ValidIO(new Redirect)) 71 val tlbFeedback = ValidIO(new TlbFeedback) 72 val dtlbResp = Flipped(Valid(new TlbResp)) 73 val forward = new LoadForwardQueryIO 74 val s1_kill = Output(Bool()) 75 val s1_paddr = Output(UInt(PAddrBits.W)) 76 }) 77 78 val s1_uop = io.in.bits.uop 79 val s1_tlb_miss = io.dtlbResp.bits.miss 80 val s1_paddr = io.dtlbResp.bits.paddr 81 val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) 82 83 // io.dtlbResp.ready := io.out.ready 84 85 io.tlbFeedback.valid := io.out.valid 86 io.tlbFeedback.bits.hit := !s1_tlb_miss 87 io.tlbFeedback.bits.roqIdx := s1_uop.roqIdx 88 89 // if tlb misses or mmio, kill prvious cycles dcache request 90 // TODO: kill dcache request when flushed 91 io.s1_kill := s1_tlb_miss || s1_mmio 92 io.s1_paddr := s1_paddr 93 94 io.forward.valid := io.out.valid 95 io.forward.paddr := s1_paddr 96 io.forward.mask := io.in.bits.mask 97 io.forward.lsroqIdx := s1_uop.lsroqIdx 98 io.forward.sqIdx := s1_uop.sqIdx 99 io.forward.uop := s1_uop 100 io.forward.pc := s1_uop.cf.pc 101 102 io.out.valid := io.in.valid && !s1_uop.needFlush(io.redirect) 103 io.out.bits := io.in.bits 104 io.out.bits.paddr := s1_paddr 105 io.out.bits.mmio := s1_mmio 106 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 107 108 io.in.ready := io.out.ready || !io.in.valid 109 110} 111 112 113// Load Pipeline Stage 2 114// DCache resp 115class LoadUnit_S2 extends XSModule { 116 val io = IO(new Bundle() { 117 val in = Flipped(Decoupled(new LsPipelineBundle)) 118 val out = Decoupled(new LsPipelineBundle) 119 val redirect = Flipped(ValidIO(new Redirect)) 120 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 121 val sbuffer = new LoadForwardQueryIO 122 val lsroq = new LoadForwardQueryIO 123 }) 124 125 val s2_uop = io.in.bits.uop 126 val s2_mask = io.in.bits.mask 127 val s2_paddr = io.in.bits.paddr 128 val s2_cache_miss = io.dcacheResp.bits.miss 129 130 io.dcacheResp.ready := true.B 131 assert(!(io.in.valid && !io.dcacheResp.valid), "DCache response got lost") 132 133 val forwardMask = WireInit(io.sbuffer.forwardMask) 134 val forwardData = WireInit(io.sbuffer.forwardData) 135 // generate XLEN/8 Muxs 136 for (i <- 0 until XLEN / 8) { 137 when(io.lsroq.forwardMask(i)) { 138 forwardMask(i) := true.B 139 forwardData(i) := io.lsroq.forwardData(i) 140 } 141 } 142 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U 143 144 // data merge 145 val rdata = VecInit((0 until XLEN / 8).map(j => 146 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))).asUInt 147 val rdataSel = LookupTree(s2_paddr(2, 0), List( 148 "b000".U -> rdata(63, 0), 149 "b001".U -> rdata(63, 8), 150 "b010".U -> rdata(63, 16), 151 "b011".U -> rdata(63, 24), 152 "b100".U -> rdata(63, 32), 153 "b101".U -> rdata(63, 40), 154 "b110".U -> rdata(63, 48), 155 "b111".U -> rdata(63, 56) 156 )) 157 val rdataPartialLoad = LookupTree(s2_uop.ctrl.fuOpType, List( 158 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 159 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 160 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 161 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 162 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 163 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 164 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN) 165 )) 166 167 // TODO: ECC check 168 169 io.out.valid := io.in.valid && !s2_uop.needFlush(io.redirect) 170 io.out.bits := io.in.bits 171 io.out.bits.data := rdataPartialLoad 172 io.out.bits.miss := s2_cache_miss && !fullForward 173 174 io.in.ready := io.out.ready || !io.in.valid 175 176} 177 178 179class LoadUnit extends XSModule { 180 val io = IO(new Bundle() { 181 val ldin = Flipped(Decoupled(new ExuInput)) 182 val ldout = Decoupled(new ExuOutput) 183 val redirect = Flipped(ValidIO(new Redirect)) 184 val tlbFeedback = ValidIO(new TlbFeedback) 185 val dcache = new DCacheLoadIO 186 val dtlb = new TlbRequestIO() 187 val sbuffer = new LoadForwardQueryIO 188 val lsroq = new LoadToLsroqIO 189 }) 190 191 val load_s0 = Module(new LoadUnit_S0) 192 val load_s1 = Module(new LoadUnit_S1) 193 val load_s2 = Module(new LoadUnit_S2) 194 195 load_s0.io.in <> io.ldin 196 load_s0.io.redirect <> io.redirect 197 load_s0.io.dtlbReq <> io.dtlb.req 198 load_s0.io.dcacheReq <> io.dcache.req 199 200 PipelineConnect(load_s0.io.out, load_s1.io.in, load_s1.io.out.fire(), false.B) 201 202 io.dcache.s1_paddr := load_s1.io.out.bits.paddr 203 load_s1.io.redirect <> io.redirect 204 load_s1.io.tlbFeedback <> io.tlbFeedback 205 load_s1.io.dtlbResp <> io.dtlb.resp 206 io.sbuffer <> load_s1.io.forward 207 io.lsroq.forward <> load_s1.io.forward 208 209 PipelineConnect(load_s1.io.out, load_s2.io.in, load_s2.io.out.fire(), false.B) 210 211 load_s2.io.redirect <> io.redirect 212 load_s2.io.dcacheResp <> io.dcache.resp 213 load_s2.io.sbuffer.forwardMask := io.sbuffer.forwardMask 214 load_s2.io.sbuffer.forwardData := io.sbuffer.forwardData 215 load_s2.io.lsroq.forwardMask := io.lsroq.forward.forwardMask 216 load_s2.io.lsroq.forwardData := io.lsroq.forward.forwardData 217 218 XSDebug(load_s0.io.out.valid, 219 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, " + 220 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 221 XSDebug(load_s1.io.out.valid, 222 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 223 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}") 224 225 // writeback to LSROQ 226 // Current dcache use MSHR 227 io.lsroq.loadIn.valid := load_s2.io.out.valid 228 io.lsroq.loadIn.bits := load_s2.io.out.bits 229 230 val hitLoadOut = Wire(Valid(new ExuOutput)) 231 hitLoadOut.valid := load_s2.io.out.valid && !load_s2.io.out.bits.miss 232 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 233 hitLoadOut.bits.data := load_s2.io.out.bits.data 234 hitLoadOut.bits.redirectValid := false.B 235 hitLoadOut.bits.redirect := DontCare 236 hitLoadOut.bits.brUpdate := DontCare 237 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 238 239 // TODO: arbiter 240 // if hit, writeback result to CDB 241 // val ldout = Vec(2, Decoupled(new ExuOutput)) 242 // when io.loadIn(i).fire() && !io.io.loadIn(i).miss, commit load to cdb 243 // val cdbArb = Module(new Arbiter(new ExuOutput, 2)) 244 // io.ldout <> cdbArb.io.out 245 // hitLoadOut <> cdbArb.io.in(0) 246 // io.lsroq.ldout <> cdbArb.io.in(1) // missLoadOut 247 load_s2.io.out.ready := true.B 248 io.lsroq.ldout.ready := !hitLoadOut.valid 249 io.ldout.bits := Mux(load_s2.io.out.ready, hitLoadOut.bits, io.lsroq.ldout.bits) 250 251 when(io.ldout.fire()){ 252 XSDebug("ldout %x iw %x fw %x\n", io.ldout.bits.uop.cf.pc, io.ldout.bits.uop.ctrl.rfWen, io.ldout.bits.uop.ctrl.fpWen) 253 } 254} 255