1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.rob.RobPtr 31import xiangshan.cache._ 32import xiangshan.cache.wpu.ReplayCarry 33import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 34import xiangshan.mem.mdp._ 35 36class LoadToLsqReplayIO(implicit p: Parameters) extends XSBundle with HasDCacheParameters { 37 // mshr refill index 38 val mshr_id = UInt(log2Up(cfg.nMissEntries).W) 39 // get full data from store queue and sbuffer 40 val full_fwd = Bool() 41 // wait for data from store inst's store queue index 42 val data_inv_sq_idx = new SqPtr 43 // wait for address from store queue index 44 val addr_inv_sq_idx = new SqPtr 45 // replay carry 46 val rep_carry = new ReplayCarry(nWays) 47 // data in last beat 48 val last_beat = Bool() 49 // replay cause 50 val cause = Vec(LoadReplayCauses.allCauses, Bool()) 51 // performance debug information 52 val debug = new PerfDebugInfo 53 54 // alias 55 def tlb_miss = cause(LoadReplayCauses.C_TM) 56 def nuke = cause(LoadReplayCauses.C_NK) 57 def mem_amb = cause(LoadReplayCauses.C_MA) 58 def fwd_fail = cause(LoadReplayCauses.C_FF) 59 def dcache_miss = cause(LoadReplayCauses.C_DM) 60 def bank_conflict = cause(LoadReplayCauses.C_BC) 61 def dcache_rep = cause(LoadReplayCauses.C_DR) 62 def rar_nack = cause(LoadReplayCauses.C_RAR) 63 def raw_nack = cause(LoadReplayCauses.C_RAW) 64 def need_rep = cause.asUInt.orR 65} 66 67 68class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 69 val ldin = DecoupledIO(new LqWriteBundle) 70 val uncache = Flipped(DecoupledIO(new MemExuOutput)) 71 val ld_raw_data = Input(new LoadDataFromLQBundle) 72 val forward = new PipeLoadForwardQueryIO 73 val stld_nuke_query = new LoadNukeQueryIO 74 val ldld_nuke_query = new LoadNukeQueryIO 75 val trigger = Flipped(new LqTriggerIO) 76} 77 78class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 79 val valid = Bool() 80 val data = UInt(XLEN.W) // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 81 val dly_ld_err = Bool() 82} 83 84class LoadUnitTriggerIO(implicit p: Parameters) extends XSBundle { 85 val tdata2 = Input(UInt(64.W)) 86 val matchType = Input(UInt(2.W)) 87 val tEnable = Input(Bool()) // timing is calculated before this 88 val addrHit = Output(Bool()) 89 val lastDataHit = Output(Bool()) 90} 91 92class LoadUnit(implicit p: Parameters) extends XSModule 93 with HasLoadHelper 94 with HasPerfEvents 95 with HasDCacheParameters 96 with HasCircularQueuePtrHelper 97{ 98 val io = IO(new Bundle() { 99 // control 100 val redirect = Flipped(ValidIO(new Redirect)) 101 val csrCtrl = Flipped(new CustomCSRCtrlIO) 102 103 // int issue path 104 val ldin = Flipped(Decoupled(new MemExuInput)) 105 val ldout = Decoupled(new MemExuOutput) 106 107 // data path 108 val tlb = new TlbRequestIO(2) 109 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 110 val dcache = new DCacheLoadIO 111 val sbuffer = new LoadForwardQueryIO 112 val lsq = new LoadToLsqIO 113 val tl_d_channel = Input(new DcacheToLduForwardIO) 114 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 115 val refill = Flipped(ValidIO(new Refill)) 116 val l2_hint = Input(Valid(new L2ToL1Hint)) 117 118 // fast wakeup 119 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 120 121 // trigger 122 val trigger = Vec(3, new LoadUnitTriggerIO) 123 124 // prefetch 125 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info 126 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) // hardware prefetch to l1 cache req 127 128 // load to load fast path 129 val l2l_fwd_in = Input(new LoadToLoadIO) 130 val l2l_fwd_out = Output(new LoadToLoadIO) 131 val ld_fast_match = Input(Bool()) 132 val ld_fast_imm = Input(UInt(12.W)) 133 134 // rs feedback 135 val feedback_fast = ValidIO(new RSFeedback) // stage 2 136 val feedback_slow = ValidIO(new RSFeedback) // stage 3 137 138 // load ecc error 139 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 140 141 // schedule error query 142 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 143 144 // queue-based replay 145 val replay = Flipped(Decoupled(new LsPipelineBundle)) 146 val lq_rep_full = Input(Bool()) 147 148 // misc 149 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 150 151 // Load fast replay path 152 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 153 val fast_rep_out = Decoupled(new LqWriteBundle) 154 155 // perf 156 val debug_ls = Output(new DebugLsInfoBundle) 157 val lsTopdownInfo = Output(new LsTopdownInfo) 158 }) 159 160 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 161 162 // Pipeline 163 // -------------------------------------------------------------------------------- 164 // stage 0 165 // -------------------------------------------------------------------------------- 166 // generate addr, use addr to query DCache and DTLB 167 val s0_valid = Wire(Bool()) 168 val s0_kill = Wire(Bool()) 169 val s0_vaddr = Wire(UInt(VAddrBits.W)) 170 val s0_mask = Wire(UInt((VLEN/8).W)) 171 val s0_uop = Wire(new DynInst) 172 val s0_has_rob_entry = Wire(Bool()) 173 val s0_rsIdx = Wire(UInt(log2Up(MemIQSizeMax).W)) 174 val s0_sqIdx = Wire(new SqPtr) 175 val s0_mshrid = Wire(UInt()) 176 val s0_try_l2l = Wire(Bool()) 177 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 178 val s0_isFirstIssue = Wire(Bool()) 179 val s0_fast_rep = Wire(Bool()) 180 val s0_ld_rep = Wire(Bool()) 181 val s0_l2l_fwd = Wire(Bool()) 182 val s0_sched_idx = Wire(UInt()) 183 val s0_deqPortIdx = Wire(UInt(log2Ceil(LoadPipelineWidth).W)) 184 val s0_can_go = s1_ready 185 val s0_fire = s0_valid && s0_can_go 186 val s0_out = Wire(new LqWriteBundle) 187 188 // load flow select/gen 189 // src0: super load replayed by LSQ (cache miss replay) (io.replay) 190 // src1: fast load replay (io.fast_rep_in) 191 // src2: load replayed by LSQ (io.replay) 192 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 193 // src4: int read / software prefetch first issue from RS (io.in) 194 // src5: vec read first issue from RS (TODO) 195 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 196 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 197 // priority: high to low 198 val s0_rep_stall = io.ldin.valid && isAfter(io.replay.bits.uop.robIdx, io.ldin.bits.uop.robIdx) 199 val s0_super_ld_rep_valid = io.replay.valid && io.replay.bits.forward_tlDchannel 200 val s0_ld_fast_rep_valid = io.fast_rep_in.valid 201 val s0_ld_rep_valid = io.replay.valid && !io.replay.bits.forward_tlDchannel && !s0_rep_stall 202 val s0_high_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence > 0.U 203 val s0_int_iss_valid = io.ldin.valid // int flow first issue or software prefetch 204 val s0_vec_iss_valid = WireInit(false.B) // TODO 205 val s0_l2l_fwd_valid = io.l2l_fwd_in.valid 206 val s0_low_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence === 0.U 207 dontTouch(s0_super_ld_rep_valid) 208 dontTouch(s0_ld_fast_rep_valid) 209 dontTouch(s0_ld_rep_valid) 210 dontTouch(s0_high_conf_prf_valid) 211 dontTouch(s0_int_iss_valid) 212 dontTouch(s0_vec_iss_valid) 213 dontTouch(s0_l2l_fwd_valid) 214 dontTouch(s0_low_conf_prf_valid) 215 216 // load flow source ready 217 val s0_super_ld_rep_ready = WireInit(true.B) 218 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 219 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 220 !s0_ld_fast_rep_valid 221 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 222 !s0_ld_fast_rep_valid && 223 !s0_ld_rep_valid 224 225 val s0_int_iss_ready = !s0_super_ld_rep_valid && 226 !s0_ld_fast_rep_valid && 227 !s0_ld_rep_valid && 228 !s0_high_conf_prf_valid 229 230 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 231 !s0_ld_fast_rep_valid && 232 !s0_ld_rep_valid && 233 !s0_high_conf_prf_valid && 234 !s0_int_iss_valid 235 236 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 237 !s0_ld_fast_rep_valid && 238 !s0_ld_rep_valid && 239 !s0_high_conf_prf_valid && 240 !s0_int_iss_valid && 241 !s0_vec_iss_valid 242 243 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 244 !s0_ld_fast_rep_valid && 245 !s0_ld_rep_valid && 246 !s0_high_conf_prf_valid && 247 !s0_int_iss_valid && 248 !s0_vec_iss_valid && 249 !s0_l2l_fwd_valid 250 dontTouch(s0_super_ld_rep_ready) 251 dontTouch(s0_ld_fast_rep_ready) 252 dontTouch(s0_ld_rep_ready) 253 dontTouch(s0_high_conf_prf_ready) 254 dontTouch(s0_int_iss_ready) 255 dontTouch(s0_vec_iss_ready) 256 dontTouch(s0_l2l_fwd_ready) 257 dontTouch(s0_low_conf_prf_ready) 258 259 // load flow source select (OH) 260 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 261 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 262 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 263 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 264 s0_low_conf_prf_ready && s0_low_conf_prf_valid 265 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 266 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 267 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 268 assert(!s0_vec_iss_select) // to be added 269 dontTouch(s0_super_ld_rep_select) 270 dontTouch(s0_ld_fast_rep_select) 271 dontTouch(s0_ld_rep_select) 272 dontTouch(s0_hw_prf_select) 273 dontTouch(s0_int_iss_select) 274 dontTouch(s0_vec_iss_select) 275 dontTouch(s0_l2l_fwd_select) 276 277 s0_valid := (s0_super_ld_rep_valid || 278 s0_ld_fast_rep_valid || 279 s0_ld_rep_valid || 280 s0_high_conf_prf_valid || 281 s0_int_iss_valid || 282 s0_vec_iss_valid || 283 s0_l2l_fwd_valid || 284 s0_low_conf_prf_valid) && io.dcache.req.ready && !s0_kill 285 286 // which is S0's out is ready and dcache is ready 287 val s0_try_ptr_chasing = s0_l2l_fwd_select 288 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.dcache.req.ready 289 val s0_ptr_chasing_vaddr = io.l2l_fwd_in.data(5, 0) +& io.ld_fast_imm(5, 0) 290 val s0_ptr_chasing_canceled = WireInit(false.B) 291 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 292 293 // prefetch related ctrl signal 294 val s0_prf = Wire(Bool()) 295 val s0_prf_rd = Wire(Bool()) 296 val s0_prf_wr = Wire(Bool()) 297 val s0_hw_prf = s0_hw_prf_select 298 299 // query DTLB 300 io.tlb.req.valid := s0_valid 301 io.tlb.req.bits.cmd := Mux(s0_prf, 302 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 303 TlbCmd.read 304 ) 305 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.prefetch_req.bits.paddr, s0_vaddr) 306 io.tlb.req.bits.size := LSUOpType.size(s0_uop.fuOpType) 307 io.tlb.req.bits.kill := s0_kill 308 io.tlb.req.bits.memidx.is_ld := true.B 309 io.tlb.req.bits.memidx.is_st := false.B 310 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 311 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 312 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 313 io.tlb.req.bits.debug.pc := s0_uop.pc 314 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 315 316 // query DCache 317 io.dcache.req.valid := s0_valid 318 io.dcache.req.bits.cmd := Mux(s0_prf_rd, 319 MemoryOpConstants.M_PFR, 320 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD) 321 ) 322 io.dcache.req.bits.vaddr := s0_vaddr 323 io.dcache.req.bits.mask := s0_mask 324 io.dcache.req.bits.data := DontCare 325 io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 326 io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 327 io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 328 io.dcache.req.bits.replayCarry := s0_rep_carry 329 io.dcache.req.bits.id := DontCare // TODO: update cache meta 330 331 // load flow priority mux 332 def fromNullSource() = { 333 s0_vaddr := 0.U 334 s0_mask := 0.U 335 s0_uop := 0.U.asTypeOf(new DynInst) 336 s0_try_l2l := false.B 337 s0_has_rob_entry := false.B 338 s0_sqIdx := 0.U.asTypeOf(new SqPtr) 339 s0_rsIdx := 0.U 340 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 341 s0_mshrid := 0.U 342 s0_isFirstIssue := false.B 343 s0_fast_rep := false.B 344 s0_ld_rep := false.B 345 s0_l2l_fwd := false.B 346 s0_prf := false.B 347 s0_prf_rd := false.B 348 s0_prf_wr := false.B 349 s0_sched_idx := 0.U 350 s0_deqPortIdx := 0.U 351 } 352 353 def fromFastReplaySource(src: LqWriteBundle) = { 354 s0_vaddr := src.vaddr 355 s0_mask := src.mask 356 s0_uop := src.uop 357 s0_try_l2l := false.B 358 s0_has_rob_entry := src.hasROBEntry 359 s0_sqIdx := src.uop.sqIdx 360 s0_rep_carry := src.rep_info.rep_carry 361 s0_mshrid := src.rep_info.mshr_id 362 s0_rsIdx := src.rsIdx 363 s0_isFirstIssue := false.B 364 s0_fast_rep := true.B 365 s0_ld_rep := src.isLoadReplay 366 s0_l2l_fwd := false.B 367 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 368 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 369 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 370 s0_sched_idx := src.schedIndex 371 s0_deqPortIdx := src.deqPortIdx 372 } 373 374 def fromNormalReplaySource(src: LsPipelineBundle) = { 375 s0_vaddr := src.vaddr 376 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 377 s0_uop := src.uop 378 s0_try_l2l := false.B 379 s0_has_rob_entry := true.B 380 s0_sqIdx := src.uop.sqIdx 381 s0_rsIdx := src.rsIdx 382 s0_rep_carry := src.replayCarry 383 s0_mshrid := src.mshrid 384 s0_isFirstIssue := src.isFirstIssue 385 s0_fast_rep := false.B 386 s0_ld_rep := true.B 387 s0_l2l_fwd := false.B 388 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 389 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 390 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 391 s0_sched_idx := src.schedIndex 392 s0_deqPortIdx := src.deqPortIdx 393 } 394 395 def fromPrefetchSource(src: L1PrefetchReq) = { 396 s0_vaddr := src.getVaddr() 397 s0_mask := 0.U 398 s0_uop := DontCare 399 s0_try_l2l := false.B 400 s0_has_rob_entry := false.B 401 s0_sqIdx := DontCare 402 s0_rsIdx := DontCare 403 s0_rep_carry := DontCare 404 s0_mshrid := DontCare 405 s0_isFirstIssue := false.B 406 s0_fast_rep := false.B 407 s0_ld_rep := false.B 408 s0_l2l_fwd := false.B 409 s0_prf := true.B 410 s0_prf_rd := !src.is_store 411 s0_prf_wr := src.is_store 412 s0_sched_idx := 0.U 413 s0_deqPortIdx := src.deqPortIdx 414 } 415 416 def fromIntIssueSource(src: MemExuInput) = { 417 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 418 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 419 s0_uop := src.uop 420 s0_try_l2l := false.B 421 s0_has_rob_entry := true.B 422 s0_sqIdx := src.uop.sqIdx 423 s0_rsIdx := src.iqIdx 424 s0_rep_carry := DontCare 425 s0_mshrid := DontCare 426 s0_isFirstIssue := true.B 427 s0_fast_rep := false.B 428 s0_ld_rep := false.B 429 s0_l2l_fwd := false.B 430 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 431 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 432 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 433 s0_sched_idx := 0.U 434 s0_deqPortIdx := src.deqPortIdx 435 } 436 437 def fromVecIssueSource() = { 438 s0_vaddr := 0.U 439 s0_mask := 0.U 440 s0_uop := 0.U.asTypeOf(new DynInst) 441 s0_try_l2l := false.B 442 s0_has_rob_entry := false.B 443 s0_sqIdx := 0.U.asTypeOf(new SqPtr) 444 s0_rsIdx := 0.U 445 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 446 s0_mshrid := 0.U 447 s0_isFirstIssue := false.B 448 s0_fast_rep := false.B 449 s0_ld_rep := false.B 450 s0_l2l_fwd := false.B 451 s0_prf := false.B 452 s0_prf_rd := false.B 453 s0_prf_wr := false.B 454 s0_sched_idx := 0.U 455 s0_deqPortIdx := 0.U 456 } 457 458 def fromLoadToLoadSource(src: LoadToLoadIO) = { 459 s0_vaddr := Cat(io.l2l_fwd_in.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 460 s0_mask := genVWmask(Cat(s0_ptr_chasing_vaddr(3), 0.U(3.W)), LSUOpType.ld) 461 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 462 // Assume the pointer chasing is always ld. 463 s0_uop.fuOpType := LSUOpType.ld 464 s0_try_l2l := s0_l2l_fwd_select 465 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 466 // because these signals will be updated in S1 467 s0_has_rob_entry := false.B 468 s0_sqIdx := DontCare 469 s0_rsIdx := DontCare 470 s0_mshrid := DontCare 471 s0_rep_carry := DontCare 472 s0_isFirstIssue := true.B 473 s0_fast_rep := false.B 474 s0_ld_rep := false.B 475 s0_l2l_fwd := true.B 476 s0_prf := false.B 477 s0_prf_rd := false.B 478 s0_prf_wr := false.B 479 s0_sched_idx := 0.U 480 s0_deqPortIdx := src.deqPortIdx 481 } 482 483 // set default 484 s0_uop := DontCare 485 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 486 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.fast_rep_in.bits) } 487 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 488 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.prefetch_req.bits) } 489 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.ldin.bits) } 490 .elsewhen (s0_vec_iss_select) { fromVecIssueSource() } 491 .otherwise { 492 if (EnableLoadToLoadForward) { 493 fromLoadToLoadSource(io.l2l_fwd_in) 494 } else { 495 fromNullSource() 496 } 497 } 498 499 // address align check 500 val s0_addr_aligned = LookupTree(s0_uop.fuOpType(1, 0), List( 501 "b00".U -> true.B, //b 502 "b01".U -> (s0_vaddr(0) === 0.U), //h 503 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 504 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 505 )) 506 507 // accept load flow if dcache ready (tlb is always ready) 508 // TODO: prefetch need writeback to loadQueueFlag 509 s0_out := DontCare 510 s0_out.rsIdx := s0_rsIdx 511 s0_out.vaddr := s0_vaddr 512 s0_out.mask := s0_mask 513 s0_out.uop := s0_uop 514 s0_out.isFirstIssue := s0_isFirstIssue 515 s0_out.hasROBEntry := s0_has_rob_entry 516 s0_out.isPrefetch := s0_prf 517 s0_out.isHWPrefetch := s0_hw_prf 518 s0_out.isFastReplay := s0_fast_rep 519 s0_out.isLoadReplay := s0_ld_rep 520 s0_out.isFastPath := s0_l2l_fwd 521 s0_out.mshrid := s0_mshrid 522 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned 523 s0_out.forward_tlDchannel := s0_super_ld_rep_select 524 when(io.tlb.req.valid && s0_isFirstIssue) { 525 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 526 }.otherwise{ 527 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 528 } 529 s0_out.schedIndex := s0_sched_idx 530 s0_out.deqPortIdx := s0_deqPortIdx 531 532 // load fast replay 533 io.fast_rep_in.ready := (s0_can_go && io.dcache.req.ready && s0_ld_fast_rep_ready) 534 535 // load flow source ready 536 // cache missed load has highest priority 537 // always accept cache missed load flow from load replay queue 538 io.replay.ready := (s0_can_go && io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 539 540 // accept load flow from rs when: 541 // 1) there is no lsq-replayed load 542 // 2) there is no fast replayed load 543 // 3) there is no high confidence prefetch request 544 io.ldin.ready := (s0_can_go && io.dcache.req.ready && s0_int_iss_ready) 545 546 // for hw prefetch load flow feedback, to be added later 547 // io.prefetch_in.ready := s0_hw_prf_select 548 549 // dcache replacement extra info 550 // TODO: should prefetch load update replacement? 551 io.dcache.replacementUpdated := Mux(s0_ld_rep_select, io.replay.bits.replacementUpdated, false.B) 552 553 XSDebug(io.dcache.req.fire, 554 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 555 ) 556 XSDebug(s0_valid, 557 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lId ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 558 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 559 560 // Pipeline 561 // -------------------------------------------------------------------------------- 562 // stage 1 563 // -------------------------------------------------------------------------------- 564 // TLB resp (send paddr to dcache) 565 val s1_valid = RegInit(false.B) 566 val s1_in = Wire(new LqWriteBundle) 567 val s1_out = Wire(new LqWriteBundle) 568 val s1_kill = Wire(Bool()) 569 val s1_can_go = s2_ready 570 val s1_fire = s1_valid && !s1_kill && s1_can_go 571 572 s1_ready := !s1_valid || s1_kill || s2_ready 573 when (s0_fire) { s1_valid := true.B } 574 .elsewhen (s1_fire) { s1_valid := false.B } 575 .elsewhen (s1_kill) { s1_valid := false.B } 576 s1_in := RegEnable(s0_out, s0_fire) 577 578 val s1_fast_rep_kill = RegEnable(io.fast_rep_in.bits.delayedLoadError, s0_fire) && s1_in.isFastReplay 579 val s1_l2l_fwd_kill = RegEnable(io.l2l_fwd_in.dly_ld_err, s0_fire) && s1_in.isFastPath 580 s1_kill := s1_l2l_fwd_kill || 581 s1_in.uop.robIdx.needFlush(io.redirect) || 582 RegEnable(s0_kill, false.B, io.ldin.valid || io.replay.valid || io.l2l_fwd_in.valid || io.fast_rep_in.valid) 583 584 val s1_vaddr_hi = Wire(UInt()) 585 val s1_vaddr_lo = Wire(UInt()) 586 val s1_vaddr = Wire(UInt()) 587 val s1_paddr_dup_lsu = Wire(UInt()) 588 val s1_paddr_dup_dcache = Wire(UInt()) 589 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 590 val s1_tlb_miss = io.tlb.resp.bits.miss 591 val s1_prf = s1_in.isPrefetch 592 val s1_hw_prf = s1_in.isHWPrefetch 593 val s1_sw_prf = s1_prf && !s1_hw_prf 594 val s1_tlb_memidx = io.tlb.resp.bits.memidx 595 596 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 597 s1_vaddr_lo := s1_in.vaddr(5, 0) 598 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 599 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 600 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 601 602 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_in.uop.lqIdx.value) { 603 // printf("load idx = %d\n", s1_tlb_memidx.idx) 604 s1_out.uop.debugInfo.tlbRespTime := GTimer() 605 } 606 607 io.tlb.req_kill := s1_kill || s1_fast_rep_kill 608 io.tlb.resp.ready := true.B 609 610 io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 611 io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 612 io.dcache.s1_kill := s1_kill || s1_fast_rep_kill || s1_tlb_miss || s1_exception 613 614 // store to load forwarding 615 io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf) 616 io.sbuffer.vaddr := s1_vaddr 617 io.sbuffer.paddr := s1_paddr_dup_lsu 618 io.sbuffer.uop := s1_in.uop 619 io.sbuffer.sqIdx := s1_in.uop.sqIdx 620 io.sbuffer.mask := s1_in.mask 621 io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 622 623 io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf) 624 io.lsq.forward.vaddr := s1_vaddr 625 io.lsq.forward.paddr := s1_paddr_dup_lsu 626 io.lsq.forward.uop := s1_in.uop 627 io.lsq.forward.sqIdx := s1_in.uop.sqIdx 628 io.lsq.forward.sqIdxMask := DontCare 629 io.lsq.forward.mask := s1_in.mask 630 io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 631 632 // st-ld violation query 633 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 634 io.stld_nuke_query(w).valid && // query valid 635 isAfter(s1_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 636 // TODO: Fix me when vector instruction 637 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 638 (s1_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 639 })).asUInt.orR && !s1_tlb_miss 640 // Generate forwardMaskFast to wake up insts earlier 641 val s1_fwd_mask_fast = ((~(io.lsq.forward.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt)).asUInt & s1_in.mask) === 0.U 642 643 s1_out := s1_in 644 s1_out.vaddr := s1_vaddr 645 s1_out.paddr := s1_paddr_dup_lsu 646 s1_out.tlbMiss := s1_tlb_miss 647 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 648 s1_out.rsIdx := s1_in.rsIdx 649 s1_out.rep_info.debug := s1_in.uop.debugInfo 650 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 651 s1_out.lateKill := s1_fast_rep_kill 652 s1_out.delayedLoadError := s1_l2l_fwd_kill || s1_fast_rep_kill 653 654 when (!s1_fast_rep_kill) { 655 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 656 // af & pf exception were modified 657 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 658 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 659 } .otherwise { 660 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B 661 s1_out.uop.exceptionVec(loadAccessFault) := s1_fast_rep_kill 662 } 663 664 // pointer chasing 665 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 666 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 667 val s1_fu_op_type_not_ld = WireInit(false.B) 668 val s1_not_fast_match = WireInit(false.B) 669 val s1_addr_mismatch = WireInit(false.B) 670 val s1_addr_misaligned = WireInit(false.B) 671 val s1_ptr_chasing_canceled = WireInit(false.B) 672 val s1_cancel_ptr_chasing = WireInit(false.B) 673 674 if (EnableLoadToLoadForward) { 675 // Sometimes, we need to cancel the load-load forwarding. 676 // These can be put at S0 if timing is bad at S1. 677 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 678 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 679 // Case 1: the address is not 64-bit aligned or the fuOpType is not LD 680 s1_addr_misaligned := s1_ptr_chasing_vaddr(2, 0).orR 681 s1_fu_op_type_not_ld := io.ldin.bits.uop.fuOpType =/= LSUOpType.ld 682 // Case 2: this is not a valid load-load pair 683 s1_not_fast_match := RegEnable(!io.ld_fast_match, s0_try_ptr_chasing) 684 // Case 3: this load-load uop is cancelled 685 s1_ptr_chasing_canceled := !io.ldin.valid 686 687 when (s1_try_ptr_chasing) { 688 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_fu_op_type_not_ld || s1_not_fast_match || s1_ptr_chasing_canceled 689 690 s1_in.uop := io.ldin.bits.uop 691 s1_in.rsIdx := io.ldin.bits.iqIdx 692 s1_in.isFirstIssue := io.ldin.bits.isFirstIssue 693 s1_vaddr_lo := Cat(s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 694 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 695 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 696 697 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 698 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 699 s1_in.uop.debugInfo.tlbRespTime := GTimer() 700 } 701 when (s1_cancel_ptr_chasing) { 702 s1_kill := true.B 703 }.otherwise { 704 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.replay.fire && !io.fast_rep_in.fire 705 when (s1_try_ptr_chasing) { 706 io.ldin.ready := true.B 707 } 708 } 709 } 710 711 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 712 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 713 // to enable load-load, sqIdxMask must be calculated based on ldin.uop 714 // If the timing here is not OK, load-load forwarding has to be disabled. 715 // Or we calculate sqIdxMask at RS?? 716 io.lsq.forward.sqIdxMask := s1_sqIdx_mask 717 if (EnableLoadToLoadForward) { 718 when (s1_try_ptr_chasing) { 719 io.lsq.forward.sqIdxMask := UIntToMask(io.ldin.bits.uop.sqIdx.value, StoreQueueSize) 720 } 721 } 722 723 io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel 724 io.forward_mshr.mshrid := s1_out.mshrid 725 io.forward_mshr.paddr := s1_out.paddr 726 727 XSDebug(s1_valid, 728 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 729 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 730 731 // Pipeline 732 // -------------------------------------------------------------------------------- 733 // stage 2 734 // -------------------------------------------------------------------------------- 735 // s2: DCache resp 736 val s2_valid = RegInit(false.B) 737 val s2_in = Wire(new LqWriteBundle) 738 val s2_out = Wire(new LqWriteBundle) 739 val s2_kill = Wire(Bool()) 740 val s2_can_go = s3_ready 741 val s2_fire = s2_valid && !s2_kill && s2_can_go 742 743 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 744 s2_ready := !s2_valid || s2_kill || s3_ready 745 when (s1_fire) { s2_valid := true.B } 746 .elsewhen (s2_fire) { s2_valid := false.B } 747 .elsewhen (s2_kill) { s2_valid := false.B } 748 s2_in := RegEnable(s1_out, s1_fire) 749 750 val s2_pmp = WireInit(io.pmp) 751 val s2_static_pm = RegNext(io.tlb.resp.bits.static_pm) 752 when (s2_static_pm.valid) { 753 s2_pmp.ld := false.B 754 s2_pmp.st := false.B 755 s2_pmp.instr := false.B 756 s2_pmp.mmio := s2_static_pm.bits 757 } 758 val s2_prf = s2_in.isPrefetch 759 val s2_hw_prf = s2_in.isHWPrefetch 760 761 // exception that may cause load addr to be invalid / illegal 762 // if such exception happen, that inst and its exception info 763 // will be force writebacked to rob 764 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 765 when (!s2_in.lateKill) { 766 s2_exception_vec(loadAccessFault) := s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld 767 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 768 when (s2_prf || s2_in.tlbMiss) { 769 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 770 } 771 } 772 val s2_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR 773 774 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 775 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.forward_mshr.forward() 776 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 777 val s2_cache_hit = io.dcache.s2_hit || s2_fwd_frm_d_chan_or_mshr 778 779 // writeback access fault caused by ecc error / bus error 780 // * ecc data error is slow to generate, so we will not use it until load stage 3 781 // * in load stage 3, an extra signal io.load_error will be used to 782 val s2_actually_mmio = s2_pmp.mmio 783 val s2_mmio = !s2_prf && s2_actually_mmio && !s2_exception && !s2_in.tlbMiss 784 val s2_full_fwd = Wire(Bool()) 785 val s2_cache_miss = io.dcache.resp.bits.miss && !s2_fwd_frm_d_chan_or_mshr 786 val s2_mq_nack = io.dcache.s2_mq_nack 787 val s2_bank_conflict = io.dcache.s2_bank_conflict && !io.dcache.resp.bits.miss && !s2_full_fwd 788 val s2_wpu_pred_fail = io.dcache.s2_wpu_pred_fail 789 val s2_cache_rep = s2_bank_conflict || s2_wpu_pred_fail 790 val s2_cache_handled = io.dcache.resp.bits.handled 791 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && io.dcache.resp.bits.tag_error 792 val s2_fwd_fail = io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid 793 val s2_mem_amb = s2_in.uop.storeSetHit && io.lsq.forward.addrInvalid && !s2_mmio && !s2_prf 794 val s2_data_inv = io.lsq.forward.dataInvalid && !s2_exception 795 val s2_dcache_kill = s2_pmp.ld || s2_pmp.mmio 796 val s2_troublem = !s2_exception && !s2_mmio && !s2_prf && !s2_in.lateKill 797 798 io.dcache.resp.ready := true.B 799 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_mmio || s2_prf) 800 assert(!(s2_valid && (s2_dcache_should_resp && !io.dcache.resp.valid)), "DCache response got lost") 801 802 // st-ld violation query 803 // NeedFastRecovery Valid when 804 // 1. Fast recovery query request Valid. 805 // 2. Load instruction is younger than requestors(store instructions). 806 // 3. Physical address match. 807 // 4. Data contains. 808 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 809 io.stld_nuke_query(w).valid && // query valid 810 isAfter(s2_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 811 // TODO: Fix me when vector instruction 812 (s2_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 813 (s2_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 814 })).asUInt.orR || s2_in.rep_info.nuke 815 816 // fast replay require 817 val s2_fast_rep = (s2_nuke || (!s2_mem_amb && !s2_in.tlbMiss && s2_cache_rep)) && s2_troublem 818 819 // need allocate new entry 820 val s2_can_query = !s2_in.tlbMiss && 821 !s2_mem_amb && 822 !s2_fast_rep && 823 !s2_in.rep_info.mem_amb && 824 s2_troublem 825 826 val s2_data_fwded = s2_cache_miss && (s2_full_fwd || s2_cache_tag_error) 827 828 // ld-ld violation require 829 io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 830 io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 831 io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 832 io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 833 io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd, true.B, !s2_cache_miss) && !s2_cache_rep 834 835 // st-ld violation require 836 io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 837 io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 838 io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 839 io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 840 io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd, true.B, !s2_cache_miss) && !s2_cache_rep 841 842 val s2_rar_nack = io.lsq.ldld_nuke_query.req.valid && !io.lsq.ldld_nuke_query.req.ready 843 val s2_raw_nack = io.lsq.stld_nuke_query.req.valid && !io.lsq.stld_nuke_query.req.ready 844 845 // merge forward result 846 // lsq has higher priority than sbuffer 847 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 848 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 849 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.lsq.forward.dataInvalid 850 // generate XLEN/8 Muxs 851 for (i <- 0 until VLEN / 8) { 852 s2_fwd_mask(i) := io.lsq.forward.forwardMask(i) || io.sbuffer.forwardMask(i) 853 s2_fwd_data(i) := Mux(io.lsq.forward.forwardMask(i), io.lsq.forward.forwardData(i), io.sbuffer.forwardData(i)) 854 } 855 856 XSDebug(s2_fire, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 857 s2_in.uop.pc, 858 io.lsq.forward.forwardData.asUInt, io.lsq.forward.forwardMask.asUInt, 859 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 860 ) 861 862 // 863 s2_out := s2_in 864 s2_out.data := 0.U // data will be generated in load s3 865 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception 866 s2_out.mmio := s2_mmio 867 s2_out.uop.flushPipe := false.B // io.fast_uop.valid && s2_mmio 868 s2_out.uop.exceptionVec := s2_exception_vec 869 s2_out.forwardMask := s2_fwd_mask 870 s2_out.forwardData := s2_fwd_data 871 s2_out.handledByMSHR := s2_cache_handled 872 s2_out.miss := s2_cache_miss && !s2_full_fwd && s2_troublem 873 s2_out.feedbacked := io.feedback_fast.valid 874 875 // Generate replay signal caused by: 876 // * st-ld violation check 877 // * tlb miss 878 // * dcache replay 879 // * forward data invalid 880 // * dcache miss 881 s2_out.rep_info.tlb_miss := s2_in.tlbMiss 882 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 883 s2_out.rep_info.nuke := s2_nuke && s2_troublem 884 s2_out.rep_info.fwd_fail := s2_data_inv && s2_troublem 885 s2_out.rep_info.dcache_rep := s2_cache_rep && s2_troublem 886 s2_out.rep_info.dcache_miss := s2_out.miss 887 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 888 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 889 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 890 s2_out.rep_info.full_fwd := s2_data_fwded 891 s2_out.rep_info.data_inv_sq_idx := io.lsq.forward.dataInvalidSqIdx 892 s2_out.rep_info.addr_inv_sq_idx := io.lsq.forward.addrInvalidSqIdx 893 s2_out.rep_info.rep_carry := io.dcache.resp.bits.replayCarry 894 s2_out.rep_info.mshr_id := io.dcache.resp.bits.mshr_id 895 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 896 s2_out.rep_info.debug := s2_in.uop.debugInfo 897 898 // if forward fail, replay this inst from fetch 899 val debug_fwd_fail_rep = s2_fwd_fail && !s2_mmio && !s2_prf && !s2_in.tlbMiss 900 // if ld-ld violation is detected, replay from this inst from fetch 901 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_mmio && !s2_is_prefetch && !s2_in.tlbMiss 902 // io.out.bits.uop.replayInst := false.B 903 904 // to be removed 905 io.feedback_fast.valid := s2_valid && // inst is valid 906 !s2_in.isLoadReplay && // already feedbacked 907 io.lq_rep_full && // LoadQueueReplay is full 908 s2_out.rep_info.need_rep && // need replay 909 !s2_exception && // no exception is triggered 910 !s2_hw_prf // not hardware prefetch 911 io.feedback_fast.bits.hit := false.B 912 io.feedback_fast.bits.flushState := s2_in.ptwBack 913 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 914 io.feedback_fast.bits.sourceType := RSFeedbackType.lrqFull 915 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 916 917 // fast wakeup 918 io.fast_uop.valid := RegNext( 919 !io.dcache.s1_disable_fast_wakeup && 920 s1_valid && 921 !s1_kill && 922 !s1_fast_rep_kill && 923 !io.tlb.resp.bits.fast_miss && 924 !io.lsq.forward.dataInvalidFast 925 ) && (s2_valid && !io.feedback_fast.valid && !s2_out.rep_info.need_rep && !s2_mmio) 926 io.fast_uop.bits := RegNext(s1_out.uop) 927 928 // 929 io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, s1_fire) 930 io.prefetch_train.valid := s2_valid && !s2_in.mmio && !s2_in.tlbMiss 931 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 932 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss 933 io.prefetch_train.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 934 io.prefetch_train.bits.meta_access := io.dcache.resp.bits.meta_access 935 if (env.FPGAPlatform){ 936 io.dcache.s0_pc := DontCare 937 io.dcache.s1_pc := DontCare 938 io.dcache.s2_pc := DontCare 939 }else{ 940 io.dcache.s0_pc := s0_out.uop.pc 941 io.dcache.s1_pc := s1_out.uop.pc 942 io.dcache.s2_pc := s2_out.uop.pc 943 } 944 io.dcache.s2_kill := s2_pmp.ld || s2_pmp.mmio || s2_kill 945 946 val s1_ld_left_fire = s1_valid && !s1_kill && !s1_fast_rep_kill && s2_ready 947 val s2_ld_valid_dup = RegInit(0.U(6.W)) 948 s2_ld_valid_dup := 0x0.U(6.W) 949 when (s1_ld_left_fire && !s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x3f.U(6.W) } 950 when (s1_kill || s1_fast_rep_kill || s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x0.U(6.W) } 951 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch))) 952 953 // Pipeline 954 // -------------------------------------------------------------------------------- 955 // stage 3 956 // -------------------------------------------------------------------------------- 957 // writeback and update load queue 958 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 959 val s3_in = RegEnable(s2_out, s2_fire) 960 val s3_out = Wire(Valid(new MemExuOutput)) 961 val s3_cache_rep = RegEnable(s2_cache_rep && s2_troublem, s2_fire) 962 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 963 val s3_fast_rep = Wire(Bool()) 964 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 965 s3_ready := !s3_valid || s3_kill || io.ldout.ready 966 967 // s3 load fast replay 968 io.fast_rep_out.valid := s3_valid && s3_fast_rep && !s3_in.uop.robIdx.needFlush(io.redirect) 969 io.fast_rep_out.bits := s3_in 970 971 io.lsq.ldin.valid := s3_valid && (!s3_fast_rep || !io.fast_rep_out.ready) && !s3_in.feedbacked && !s3_in.lateKill 972 io.lsq.ldin.bits := s3_in 973 974 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 975 io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 976 io.lsq.ldin.bits.replacementUpdated := io.dcache.resp.bits.replacementUpdated 977 978 val s3_dly_ld_err = 979 if (EnableAccurateLoadError) { 980 (s3_in.delayedLoadError || io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 981 } else { 982 WireInit(false.B) 983 } 984 io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 985 io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 986 io.lsq.ldin.bits.dcacheRequireReplay := s3_cache_rep 987 988 val s3_vp_match_fail = RegNext(io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid) 989 val s3_ldld_rep_inst = 990 io.lsq.ldld_nuke_query.resp.valid && 991 io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 992 RegNext(io.csrCtrl.ldld_vio_check_enable) 993 994 val s3_rep_info = s3_in.rep_info 995 val s3_rep_frm_fetch = s3_vp_match_fail || s3_ldld_rep_inst 996 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 997 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_MA) || 998 s3_sel_rep_cause(LoadReplayCauses.C_TM) || 999 s3_sel_rep_cause(LoadReplayCauses.C_NK) 1000 1001 val s3_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR 1002 when ((s3_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1003 io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1004 } .otherwise { 1005 io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1006 } 1007 1008 // Int load, if hit, will be writebacked at s2 1009 s3_out.valid := s3_valid && !io.lsq.ldin.bits.rep_info.need_rep && !s3_in.mmio && !s3_in.lateKill 1010 s3_out.bits.uop := s3_in.uop 1011 s3_out.bits.uop.exceptionVec(loadAccessFault) := s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault) 1012 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1013 s3_out.bits.data := s3_in.data 1014 s3_out.bits.debug.isMMIO := s3_in.mmio 1015 s3_out.bits.debug.isPerfCnt := false.B 1016 s3_out.bits.debug.paddr := s3_in.paddr 1017 s3_out.bits.debug.vaddr := s3_in.vaddr 1018 1019 when (s3_force_rep) { 1020 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1021 } 1022 1023 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1024 1025 io.lsq.ldin.bits.uop := s3_out.bits.uop 1026 1027 val s3_revoke = s3_exception || io.lsq.ldin.bits.rep_info.need_rep 1028 io.lsq.ldld_nuke_query.revoke := s3_revoke 1029 io.lsq.stld_nuke_query.revoke := s3_revoke 1030 1031 // feedback slow 1032 s3_fast_rep := (RegNext(s2_fast_rep) || 1033 (s3_in.rep_info.dcache_miss && io.l2_hint.valid && io.l2_hint.bits.sourceId === s3_in.rep_info.mshr_id)) && 1034 !s3_in.feedbacked && 1035 !s3_in.lateKill && 1036 !s3_rep_frm_fetch && 1037 !s3_exception 1038 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.fast_rep_out.ready) && !s3_in.feedbacked 1039 1040 // 1041 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting 1042 io.feedback_slow.bits.hit := !io.lsq.ldin.bits.rep_info.need_rep || io.lsq.ldin.ready 1043 io.feedback_slow.bits.flushState := s3_in.ptwBack 1044 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1045 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1046 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1047 1048 io.ldCancel.ld2Cancel.valid := s3_loadOutValid && !s3_loadOutBits.uop.robIdx.needFlush(io.redirect) && !s3_loadOutBits.isLoadReplay && !io.feedbackSlow.bits.hit 1049 io.ldCancel.ld2Cancel.bits := s3_loadOutBits.deqPortIdx 1050 1051 val s3_ld_wb_meta = Mux(s3_out.valid, s3_out.bits, io.lsq.uncache.bits) 1052 // data from load queue refill 1053 val s3_ld_raw_data_frm_uncache = io.lsq.ld_raw_data 1054 val s3_merged_data_frm_uncache = s3_ld_raw_data_frm_uncache.mergedData() 1055 val s3_picked_data_frm_uncache = LookupTree(s3_ld_raw_data_frm_uncache.addrOffset, List( 1056 "b000".U -> s3_merged_data_frm_uncache(63, 0), 1057 "b001".U -> s3_merged_data_frm_uncache(63, 8), 1058 "b010".U -> s3_merged_data_frm_uncache(63, 16), 1059 "b011".U -> s3_merged_data_frm_uncache(63, 24), 1060 "b100".U -> s3_merged_data_frm_uncache(63, 32), 1061 "b101".U -> s3_merged_data_frm_uncache(63, 40), 1062 "b110".U -> s3_merged_data_frm_uncache(63, 48), 1063 "b111".U -> s3_merged_data_frm_uncache(63, 56) 1064 )) 1065 val s3_ld_data_frm_uncache = rdataHelper(s3_ld_raw_data_frm_uncache.uop, s3_picked_data_frm_uncache) 1066 1067 // data from dcache hit 1068 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1069 s3_ld_raw_data_frm_cache.respDcacheData := io.dcache.resp.bits.data_delayed 1070 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1071 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1072 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1073 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1074 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, s2_valid) 1075 s3_ld_raw_data_frm_cache.forwardData_D := RegEnable(s2_fwd_data_frm_d_chan, s2_valid) 1076 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, s2_valid) 1077 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1078 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, s2_valid) 1079 1080 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1081 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1082 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1083 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1084 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1085 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1086 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1087 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1088 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1089 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1090 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1091 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1092 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1093 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1094 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1095 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1096 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1097 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1098 )) 1099 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1100 1101 // FIXME: add 1 cycle delay ? 1102 io.lsq.uncache.ready := !s3_out.valid 1103 io.ldout.bits := s3_ld_wb_meta 1104 io.ldout.bits.data := Mux(s3_out.valid, s3_ld_data_frm_cache, s3_ld_data_frm_uncache) 1105 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) || 1106 io.lsq.uncache.valid && !io.lsq.uncache.bits.uop.robIdx.needFlush(io.redirect) && !s3_out.valid 1107 1108 1109 // fast load to load forward 1110 io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill // for debug only 1111 io.l2l_fwd_out.data := Mux(s3_ld_raw_data_frm_cache.addrOffset(3), s3_merged_data_frm_cache(127, 64), s3_merged_data_frm_cache(63, 0)) // load to load is for ld only 1112 io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1113 1114 // trigger 1115 val last_valid_data = RegNext(RegEnable(io.ldout.bits.data, io.ldout.fire)) 1116 val hit_ld_addr_trig_hit_vec = Wire(Vec(3, Bool())) 1117 val lq_ld_addr_trig_hit_vec = io.lsq.trigger.lqLoadAddrTriggerHitVec 1118 (0 until 3).map{i => { 1119 val tdata2 = RegNext(io.trigger(i).tdata2) 1120 val matchType = RegNext(io.trigger(i).matchType) 1121 val tEnable = RegNext(io.trigger(i).tEnable) 1122 1123 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s2_out.vaddr), tdata2, matchType, tEnable) 1124 io.trigger(i).addrHit := Mux(s3_out.valid, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1125 io.trigger(i).lastDataHit := TriggerCmp(last_valid_data, tdata2, matchType, tEnable) 1126 }} 1127 io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1128 1129 // FIXME: please move this part to LoadQueueReplay 1130 io.debug_ls := DontCare 1131 1132 // Topdown 1133 io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1134 io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1135 io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1136 io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1137 io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1138 io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1139 1140 // perf cnt 1141 XSPerfAccumulate("s0_in_valid", io.ldin.valid) 1142 XSPerfAccumulate("s0_in_block", io.ldin.valid && !io.ldin.fire) 1143 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1144 XSPerfAccumulate("s0_lsq_fire_first_issue", io.replay.fire) 1145 XSPerfAccumulate("s0_ldu_fire_first_issue", io.ldin.fire && s0_isFirstIssue) 1146 XSPerfAccumulate("s0_fast_replay_issue", io.fast_rep_in.fire) 1147 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1148 XSPerfAccumulate("s0_stall_dcache", s0_valid && !io.dcache.req.ready) 1149 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12)) 1150 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12)) 1151 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1152 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1153 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1154 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1155 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1156 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.prefetch_req.valid && !s0_hw_prf_select) 1157 XSPerfAccumulate("s0_hardware_prefetch_total", io.prefetch_req.valid) 1158 1159 XSPerfAccumulate("s1_in_valid", s1_valid) 1160 XSPerfAccumulate("s1_in_fire", s1_fire) 1161 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1162 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1163 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1164 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1165 1166 XSPerfAccumulate("s2_in_valid", s2_valid) 1167 XSPerfAccumulate("s2_in_fire", s2_fire) 1168 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1169 XSPerfAccumulate("s2_dcache_miss", s2_fire && s2_cache_miss) 1170 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && s2_cache_miss && s2_in.isFirstIssue) 1171 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1172 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_cache_miss && s2_full_fwd) 1173 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1174 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1175 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && s2_cache_rep) // ignore prefetch for mshr full / miss req port conflict 1176 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && s2_cache_miss) // prefetch req miss in l1 1177 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !s2_cache_miss) // prefetch req hit in l1 1178 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && s2_cache_miss && !s2_cache_rep) // prefetch a missed line in l1, and l1 accepted it 1179 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fwd_frm_d_chan && s2_fwd_data_valid) 1180 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fwd_frm_mshr && s2_fwd_data_valid) 1181 1182 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1183 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1184 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1185 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1186 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1187 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1188 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1189 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1190 1191 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1192 // hardware performance counter 1193 val perfEvents = Seq( 1194 ("load_s0_in_fire ", s0_fire ), 1195 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1196 ("stall_dcache ", s0_valid && s0_can_go && !io.dcache.req.ready ), 1197 ("load_s1_in_fire ", s0_fire ), 1198 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1199 ("load_s2_in_fire ", s1_fire ), 1200 ("load_s2_dcache_miss ", s2_fire && io.dcache.resp.bits.miss ), 1201 ) 1202 generatePerfEvent() 1203 1204 when(io.ldout.fire){ 1205 XSDebug("ldout %x\n", io.ldout.bits.uop.pc) 1206 } 1207 // end 1208}