1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.fu.PMPRespBundle 27import xiangshan.backend.rob.{DebugLsInfoBundle, LsTopdownInfo, RobPtr} 28import xiangshan.cache._ 29import xiangshan.cache.wpu.ReplayCarry 30import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 31import xiangshan.mem.mdp._ 32 33class LoadToLsqReplayIO(implicit p: Parameters) extends XSBundle with HasDCacheParameters { 34 // mshr refill index 35 val mshr_id = UInt(log2Up(cfg.nMissEntries).W) 36 // get full data from store queue and sbuffer 37 val full_fwd = Bool() 38 // wait for data from store inst's store queue index 39 val data_inv_sq_idx = new SqPtr 40 // wait for address from store queue index 41 val addr_inv_sq_idx = new SqPtr 42 // replay carry 43 val rep_carry = new ReplayCarry(nWays) 44 // data in last beat 45 val last_beat = Bool() 46 // replay cause 47 val cause = Vec(LoadReplayCauses.allCauses, Bool()) 48 // performance debug information 49 val debug = new PerfDebugInfo 50 51 // alias 52 def tlb_miss = cause(LoadReplayCauses.C_TM) 53 def nuke = cause(LoadReplayCauses.C_NK) 54 def mem_amb = cause(LoadReplayCauses.C_MA) 55 def fwd_fail = cause(LoadReplayCauses.C_FF) 56 def dcache_miss = cause(LoadReplayCauses.C_DM) 57 def bank_conflict = cause(LoadReplayCauses.C_BC) 58 def dcache_rep = cause(LoadReplayCauses.C_DR) 59 def rar_nack = cause(LoadReplayCauses.C_RAR) 60 def raw_nack = cause(LoadReplayCauses.C_RAW) 61 def need_rep = cause.asUInt.orR 62} 63 64 65class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 66 val ldin = DecoupledIO(new LqWriteBundle) 67 val uncache = Flipped(DecoupledIO(new ExuOutput)) 68 val ld_raw_data = Input(new LoadDataFromLQBundle) 69 val forward = new PipeLoadForwardQueryIO 70 val stld_nuke_query = new LoadNukeQueryIO 71 val ldld_nuke_query = new LoadNukeQueryIO 72 val trigger = Flipped(new LqTriggerIO) 73} 74 75class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 76 val valid = Bool() 77 val data = UInt(XLEN.W) // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 78 val dly_ld_err = Bool() 79} 80 81class LoadUnitTriggerIO(implicit p: Parameters) extends XSBundle { 82 val tdata2 = Input(UInt(64.W)) 83 val matchType = Input(UInt(2.W)) 84 val tEnable = Input(Bool()) // timing is calculated before this 85 val addrHit = Output(Bool()) 86 val lastDataHit = Output(Bool()) 87} 88 89class LoadUnit(implicit p: Parameters) extends XSModule 90 with HasLoadHelper 91 with HasPerfEvents 92 with HasDCacheParameters 93 with HasCircularQueuePtrHelper 94{ 95 val io = IO(new Bundle() { 96 // control 97 val redirect = Flipped(ValidIO(new Redirect)) 98 val csrCtrl = Flipped(new CustomCSRCtrlIO) 99 100 // int issue path 101 val ldin = Flipped(Decoupled(new ExuInput)) 102 val ldout = Decoupled(new ExuOutput) 103 val rsIdx = Input(UInt()) 104 val isFirstIssue = Input(Bool()) 105 106 // data path 107 val tlb = new TlbRequestIO(2) 108 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 109 val dcache = new DCacheLoadIO 110 val sbuffer = new LoadForwardQueryIO 111 val lsq = new LoadToLsqIO 112 val tl_d_channel = Input(new DcacheToLduForwardIO) 113 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 114 val refill = Flipped(ValidIO(new Refill)) 115 val l2_hint = Input(Valid(new L2ToL1Hint)) 116 117 // fast wakeup 118 val fast_uop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1, send to RS in load_s2 119 120 // trigger 121 val trigger = Vec(3, new LoadUnitTriggerIO) 122 123 // prefetch 124 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info 125 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) // hardware prefetch to l1 cache req 126 127 // load to load fast path 128 val l2l_fwd_in = Input(new LoadToLoadIO) 129 val l2l_fwd_out = Output(new LoadToLoadIO) 130 val ld_fast_match = Input(Bool()) 131 val ld_fast_imm = Input(UInt(12.W)) 132 133 // rs feedback 134 val feedback_fast = ValidIO(new RSFeedback) // stage 2 135 val feedback_slow = ValidIO(new RSFeedback) // stage 3 136 137 // load ecc error 138 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 139 140 // schedule error query 141 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 142 143 // queue-based replay 144 val replay = Flipped(Decoupled(new LsPipelineBundle)) 145 val lq_rep_full = Input(Bool()) 146 147 // misc 148 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 149 150 // Load fast replay path 151 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 152 val fast_rep_out = Decoupled(new LqWriteBundle) 153 154 // perf 155 val debug_ls = Output(new DebugLsInfoBundle) 156 val lsTopdownInfo = Output(new LsTopdownInfo) 157 }) 158 159 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 160 161 // Pipeline 162 // -------------------------------------------------------------------------------- 163 // stage 0 164 // -------------------------------------------------------------------------------- 165 // generate addr, use addr to query DCache and DTLB 166 val s0_valid = Wire(Bool()) 167 val s0_kill = Wire(Bool()) 168 val s0_vaddr = Wire(UInt(VAddrBits.W)) 169 val s0_mask = Wire(UInt((VLEN/8).W)) 170 val s0_uop = Wire(new MicroOp) 171 val s0_has_rob_entry = Wire(Bool()) 172 val s0_rsIdx = Wire(UInt(log2Up(IssQueSize).W)) 173 val s0_sqIdx = Wire(new SqPtr) 174 val s0_mshrid = Wire(UInt()) 175 val s0_try_l2l = Wire(Bool()) 176 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 177 val s0_isFirstIssue = Wire(Bool()) 178 val s0_fast_rep = Wire(Bool()) 179 val s0_ld_rep = Wire(Bool()) 180 val s0_l2l_fwd = Wire(Bool()) 181 val s0_sched_idx = Wire(UInt()) 182 val s0_can_go = s1_ready 183 val s0_fire = s0_valid && s0_can_go 184 val s0_out = Wire(new LqWriteBundle) 185 186 // load flow select/gen 187 // src0: super load replayed by LSQ (cache miss replay) (io.replay) 188 // src1: fast load replay (io.fast_rep_in) 189 // src2: load replayed by LSQ (io.replay) 190 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 191 // src4: int read / software prefetch first issue from RS (io.in) 192 // src5: vec read first issue from RS (TODO) 193 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 194 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 195 // priority: high to low 196 val s0_rep_stall = io.ldin.valid && isAfter(io.replay.bits.uop.robIdx, io.ldin.bits.uop.robIdx) 197 val s0_super_ld_rep_valid = io.replay.valid && io.replay.bits.forward_tlDchannel 198 val s0_ld_fast_rep_valid = io.fast_rep_in.valid 199 val s0_ld_rep_valid = io.replay.valid && !io.replay.bits.forward_tlDchannel && !s0_rep_stall 200 val s0_high_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence > 0.U 201 val s0_int_iss_valid = io.ldin.valid // int flow first issue or software prefetch 202 val s0_vec_iss_valid = WireInit(false.B) // TODO 203 val s0_l2l_fwd_valid = io.l2l_fwd_in.valid 204 val s0_low_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence === 0.U 205 dontTouch(s0_super_ld_rep_valid) 206 dontTouch(s0_ld_fast_rep_valid) 207 dontTouch(s0_ld_rep_valid) 208 dontTouch(s0_high_conf_prf_valid) 209 dontTouch(s0_int_iss_valid) 210 dontTouch(s0_vec_iss_valid) 211 dontTouch(s0_l2l_fwd_valid) 212 dontTouch(s0_low_conf_prf_valid) 213 214 // load flow source ready 215 val s0_super_ld_rep_ready = WireInit(true.B) 216 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 217 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 218 !s0_ld_fast_rep_valid 219 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 220 !s0_ld_fast_rep_valid && 221 !s0_ld_rep_valid 222 223 val s0_int_iss_ready = !s0_super_ld_rep_valid && 224 !s0_ld_fast_rep_valid && 225 !s0_ld_rep_valid && 226 !s0_high_conf_prf_valid 227 228 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 229 !s0_ld_fast_rep_valid && 230 !s0_ld_rep_valid && 231 !s0_high_conf_prf_valid && 232 !s0_int_iss_valid 233 234 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 235 !s0_ld_fast_rep_valid && 236 !s0_ld_rep_valid && 237 !s0_high_conf_prf_valid && 238 !s0_int_iss_valid && 239 !s0_vec_iss_valid 240 241 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 242 !s0_ld_fast_rep_valid && 243 !s0_ld_rep_valid && 244 !s0_high_conf_prf_valid && 245 !s0_int_iss_valid && 246 !s0_vec_iss_valid && 247 !s0_l2l_fwd_valid 248 dontTouch(s0_super_ld_rep_ready) 249 dontTouch(s0_ld_fast_rep_ready) 250 dontTouch(s0_ld_rep_ready) 251 dontTouch(s0_high_conf_prf_ready) 252 dontTouch(s0_int_iss_ready) 253 dontTouch(s0_vec_iss_ready) 254 dontTouch(s0_l2l_fwd_ready) 255 dontTouch(s0_low_conf_prf_ready) 256 257 // load flow source select (OH) 258 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 259 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 260 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 261 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 262 s0_low_conf_prf_ready && s0_low_conf_prf_valid 263 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 264 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 265 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 266 assert(!s0_vec_iss_select) // to be added 267 dontTouch(s0_super_ld_rep_select) 268 dontTouch(s0_ld_fast_rep_select) 269 dontTouch(s0_ld_rep_select) 270 dontTouch(s0_hw_prf_select) 271 dontTouch(s0_int_iss_select) 272 dontTouch(s0_vec_iss_select) 273 dontTouch(s0_l2l_fwd_select) 274 275 s0_valid := (s0_super_ld_rep_valid || 276 s0_ld_fast_rep_valid || 277 s0_ld_rep_valid || 278 s0_high_conf_prf_valid || 279 s0_int_iss_valid || 280 s0_vec_iss_valid || 281 s0_l2l_fwd_valid || 282 s0_low_conf_prf_valid) && io.dcache.req.ready && !s0_kill 283 284 // which is S0's out is ready and dcache is ready 285 val s0_try_ptr_chasing = s0_l2l_fwd_select 286 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.dcache.req.ready 287 val s0_ptr_chasing_vaddr = io.l2l_fwd_in.data(5, 0) +& io.ld_fast_imm(5, 0) 288 val s0_ptr_chasing_canceled = WireInit(false.B) 289 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 290 291 // prefetch related ctrl signal 292 val s0_prf = Wire(Bool()) 293 val s0_prf_rd = Wire(Bool()) 294 val s0_prf_wr = Wire(Bool()) 295 val s0_hw_prf = s0_hw_prf_select 296 297 // query DTLB 298 io.tlb.req.valid := s0_valid 299 io.tlb.req.bits.cmd := Mux(s0_prf, 300 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 301 TlbCmd.read 302 ) 303 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.prefetch_req.bits.paddr, s0_vaddr) 304 io.tlb.req.bits.size := LSUOpType.size(s0_uop.ctrl.fuOpType) 305 io.tlb.req.bits.kill := s0_kill 306 io.tlb.req.bits.memidx.is_ld := true.B 307 io.tlb.req.bits.memidx.is_st := false.B 308 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 309 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 310 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 311 io.tlb.req.bits.debug.pc := s0_uop.cf.pc 312 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 313 314 // query DCache 315 io.dcache.req.valid := s0_valid 316 io.dcache.req.bits.cmd := Mux(s0_prf_rd, 317 MemoryOpConstants.M_PFR, 318 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD) 319 ) 320 io.dcache.req.bits.vaddr := s0_vaddr 321 io.dcache.req.bits.mask := s0_mask 322 io.dcache.req.bits.data := DontCare 323 io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 324 io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 325 io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 326 io.dcache.req.bits.replayCarry := s0_rep_carry 327 io.dcache.req.bits.id := DontCare // TODO: update cache meta 328 329 // load flow priority mux 330 def fromNullSource() = { 331 s0_vaddr := 0.U 332 s0_mask := 0.U 333 s0_uop := 0.U.asTypeOf(new MicroOp) 334 s0_try_l2l := false.B 335 s0_has_rob_entry := false.B 336 s0_sqIdx := 0.U.asTypeOf(new SqPtr) 337 s0_rsIdx := 0.U 338 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 339 s0_mshrid := 0.U 340 s0_isFirstIssue := false.B 341 s0_fast_rep := false.B 342 s0_ld_rep := false.B 343 s0_l2l_fwd := false.B 344 s0_prf := false.B 345 s0_prf_rd := false.B 346 s0_prf_wr := false.B 347 s0_sched_idx := 0.U 348 } 349 350 def fromFastReplaySource(src: LqWriteBundle) = { 351 s0_vaddr := src.vaddr 352 s0_mask := src.mask 353 s0_uop := src.uop 354 s0_try_l2l := false.B 355 s0_has_rob_entry := src.hasROBEntry 356 s0_sqIdx := src.uop.sqIdx 357 s0_rep_carry := src.rep_info.rep_carry 358 s0_mshrid := src.rep_info.mshr_id 359 s0_rsIdx := src.rsIdx 360 s0_isFirstIssue := false.B 361 s0_fast_rep := true.B 362 s0_ld_rep := src.isLoadReplay 363 s0_l2l_fwd := false.B 364 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 365 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 366 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 367 s0_sched_idx := src.schedIndex 368 } 369 370 def fromNormalReplaySource(src: LsPipelineBundle) = { 371 s0_vaddr := src.vaddr 372 s0_mask := genVWmask(src.vaddr, src.uop.ctrl.fuOpType(1, 0)) 373 s0_uop := src.uop 374 s0_try_l2l := false.B 375 s0_has_rob_entry := true.B 376 s0_sqIdx := src.uop.sqIdx 377 s0_rsIdx := src.rsIdx 378 s0_rep_carry := src.replayCarry 379 s0_mshrid := src.mshrid 380 s0_isFirstIssue := src.isFirstIssue 381 s0_fast_rep := false.B 382 s0_ld_rep := true.B 383 s0_l2l_fwd := false.B 384 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 385 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 386 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 387 s0_sched_idx := src.schedIndex 388 } 389 390 def fromPrefetchSource(src: L1PrefetchReq) = { 391 s0_vaddr := src.getVaddr() 392 s0_mask := 0.U 393 s0_uop := DontCare 394 s0_try_l2l := false.B 395 s0_has_rob_entry := false.B 396 s0_sqIdx := DontCare 397 s0_rsIdx := DontCare 398 s0_rep_carry := DontCare 399 s0_mshrid := DontCare 400 s0_isFirstIssue := false.B 401 s0_fast_rep := false.B 402 s0_ld_rep := false.B 403 s0_l2l_fwd := false.B 404 s0_prf := true.B 405 s0_prf_rd := !src.is_store 406 s0_prf_wr := src.is_store 407 s0_sched_idx := 0.U 408 } 409 410 def fromIntIssueSource(src: ExuInput) = { 411 s0_vaddr := src.src(0) + SignExt(src.uop.ctrl.imm(11, 0), VAddrBits) 412 s0_mask := genVWmask(s0_vaddr, src.uop.ctrl.fuOpType(1,0)) 413 s0_uop := src.uop 414 s0_try_l2l := false.B 415 s0_has_rob_entry := true.B 416 s0_sqIdx := src.uop.sqIdx 417 s0_rsIdx := io.rsIdx 418 s0_rep_carry := DontCare 419 s0_mshrid := DontCare 420 s0_isFirstIssue := true.B 421 s0_fast_rep := false.B 422 s0_ld_rep := false.B 423 s0_l2l_fwd := false.B 424 s0_prf := LSUOpType.isPrefetch(src.uop.ctrl.fuOpType) 425 s0_prf_rd := src.uop.ctrl.fuOpType === LSUOpType.prefetch_r 426 s0_prf_wr := src.uop.ctrl.fuOpType === LSUOpType.prefetch_w 427 s0_sched_idx := 0.U 428 } 429 430 def fromVecIssueSource() = { 431 s0_vaddr := 0.U 432 s0_mask := 0.U 433 s0_uop := 0.U.asTypeOf(new MicroOp) 434 s0_try_l2l := false.B 435 s0_has_rob_entry := false.B 436 s0_sqIdx := 0.U.asTypeOf(new SqPtr) 437 s0_rsIdx := 0.U 438 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 439 s0_mshrid := 0.U 440 s0_isFirstIssue := false.B 441 s0_fast_rep := false.B 442 s0_ld_rep := false.B 443 s0_l2l_fwd := false.B 444 s0_prf := false.B 445 s0_prf_rd := false.B 446 s0_prf_wr := false.B 447 s0_sched_idx := 0.U 448 } 449 450 def fromLoadToLoadSource(src: LoadToLoadIO) = { 451 s0_vaddr := Cat(io.l2l_fwd_in.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 452 s0_mask := genVWmask(Cat(s0_ptr_chasing_vaddr(3), 0.U(3.W)), LSUOpType.ld) 453 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 454 // Assume the pointer chasing is always ld. 455 s0_uop.ctrl.fuOpType := LSUOpType.ld 456 s0_try_l2l := s0_l2l_fwd_select 457 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 458 // because these signals will be updated in S1 459 s0_has_rob_entry := false.B 460 s0_sqIdx := DontCare 461 s0_rsIdx := DontCare 462 s0_mshrid := DontCare 463 s0_rep_carry := DontCare 464 s0_isFirstIssue := true.B 465 s0_fast_rep := false.B 466 s0_ld_rep := false.B 467 s0_l2l_fwd := true.B 468 s0_prf := false.B 469 s0_prf_rd := false.B 470 s0_prf_wr := false.B 471 s0_sched_idx := 0.U 472 } 473 474 // set default 475 s0_uop := DontCare 476 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 477 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.fast_rep_in.bits) } 478 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 479 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.prefetch_req.bits) } 480 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.ldin.bits) } 481 .elsewhen (s0_vec_iss_select) { fromVecIssueSource() } 482 .otherwise { 483 if (EnableLoadToLoadForward) { 484 fromLoadToLoadSource(io.l2l_fwd_in) 485 } else { 486 fromNullSource() 487 } 488 } 489 490 // address align check 491 val s0_addr_aligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 492 "b00".U -> true.B, //b 493 "b01".U -> (s0_vaddr(0) === 0.U), //h 494 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 495 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 496 )) 497 498 // accept load flow if dcache ready (tlb is always ready) 499 // TODO: prefetch need writeback to loadQueueFlag 500 s0_out := DontCare 501 s0_out.rsIdx := s0_rsIdx 502 s0_out.vaddr := s0_vaddr 503 s0_out.mask := s0_mask 504 s0_out.uop := s0_uop 505 s0_out.isFirstIssue := s0_isFirstIssue 506 s0_out.hasROBEntry := s0_has_rob_entry 507 s0_out.isPrefetch := s0_prf 508 s0_out.isHWPrefetch := s0_hw_prf 509 s0_out.isFastReplay := s0_fast_rep 510 s0_out.isLoadReplay := s0_ld_rep 511 s0_out.isFastPath := s0_l2l_fwd 512 s0_out.mshrid := s0_mshrid 513 s0_out.uop.cf.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned 514 s0_out.forward_tlDchannel := s0_super_ld_rep_select 515 when(io.tlb.req.valid && s0_isFirstIssue) { 516 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 517 }.otherwise{ 518 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 519 } 520 s0_out.schedIndex := s0_sched_idx 521 522 // load fast replay 523 io.fast_rep_in.ready := (s0_can_go && io.dcache.req.ready && s0_ld_fast_rep_ready) 524 525 // load flow source ready 526 // cache missed load has highest priority 527 // always accept cache missed load flow from load replay queue 528 io.replay.ready := (s0_can_go && io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 529 530 // accept load flow from rs when: 531 // 1) there is no lsq-replayed load 532 // 2) there is no fast replayed load 533 // 3) there is no high confidence prefetch request 534 io.ldin.ready := (s0_can_go && io.dcache.req.ready && s0_int_iss_ready) 535 536 // for hw prefetch load flow feedback, to be added later 537 // io.prefetch_in.ready := s0_hw_prf_select 538 539 // dcache replacement extra info 540 // TODO: should prefetch load update replacement? 541 io.dcache.replacementUpdated := Mux(s0_ld_rep_select, io.replay.bits.replacementUpdated, false.B) 542 543 XSDebug(io.dcache.req.fire, 544 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 545 ) 546 XSDebug(s0_valid, 547 p"S0: pc ${Hexadecimal(s0_out.uop.cf.pc)}, lId ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 548 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 549 550 // Pipeline 551 // -------------------------------------------------------------------------------- 552 // stage 1 553 // -------------------------------------------------------------------------------- 554 // TLB resp (send paddr to dcache) 555 val s1_valid = RegInit(false.B) 556 val s1_in = Wire(new LqWriteBundle) 557 val s1_out = Wire(new LqWriteBundle) 558 val s1_kill = Wire(Bool()) 559 val s1_can_go = s2_ready 560 val s1_fire = s1_valid && !s1_kill && s1_can_go 561 562 s1_ready := !s1_valid || s1_kill || s2_ready 563 when (s0_fire) { s1_valid := true.B } 564 .elsewhen (s1_fire) { s1_valid := false.B } 565 .elsewhen (s1_kill) { s1_valid := false.B } 566 s1_in := RegEnable(s0_out, s0_fire) 567 568 val s1_fast_rep_kill = RegEnable(io.fast_rep_in.bits.delayedLoadError, s0_fire) && s1_in.isFastReplay 569 val s1_l2l_fwd_kill = RegEnable(io.l2l_fwd_in.dly_ld_err, s0_fire) && s1_in.isFastPath 570 s1_kill := s1_l2l_fwd_kill || 571 s1_in.uop.robIdx.needFlush(io.redirect) || 572 RegEnable(s0_kill, false.B, io.ldin.valid || io.replay.valid || io.l2l_fwd_in.valid || io.fast_rep_in.valid) 573 574 val s1_vaddr_hi = Wire(UInt()) 575 val s1_vaddr_lo = Wire(UInt()) 576 val s1_vaddr = Wire(UInt()) 577 val s1_paddr_dup_lsu = Wire(UInt()) 578 val s1_paddr_dup_dcache = Wire(UInt()) 579 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.cf.exceptionVec, lduCfg).asUInt.orR // af & pf exception were modified below. 580 val s1_tlb_miss = io.tlb.resp.bits.miss 581 val s1_prf = s1_in.isPrefetch 582 val s1_hw_prf = s1_in.isHWPrefetch 583 val s1_sw_prf = s1_prf && !s1_hw_prf 584 val s1_tlb_memidx = io.tlb.resp.bits.memidx 585 586 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 587 s1_vaddr_lo := s1_in.vaddr(5, 0) 588 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 589 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 590 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 591 592 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_in.uop.lqIdx.value) { 593 // printf("load idx = %d\n", s1_tlb_memidx.idx) 594 s1_out.uop.debugInfo.tlbRespTime := GTimer() 595 } 596 597 io.tlb.req_kill := s1_kill || s1_fast_rep_kill 598 io.tlb.resp.ready := true.B 599 600 io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 601 io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 602 io.dcache.s1_kill := s1_kill || s1_fast_rep_kill || s1_tlb_miss || s1_exception 603 604 // store to load forwarding 605 io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf) 606 io.sbuffer.vaddr := s1_vaddr 607 io.sbuffer.paddr := s1_paddr_dup_lsu 608 io.sbuffer.uop := s1_in.uop 609 io.sbuffer.sqIdx := s1_in.uop.sqIdx 610 io.sbuffer.mask := s1_in.mask 611 io.sbuffer.pc := s1_in.uop.cf.pc // FIXME: remove it 612 613 io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf) 614 io.lsq.forward.vaddr := s1_vaddr 615 io.lsq.forward.paddr := s1_paddr_dup_lsu 616 io.lsq.forward.uop := s1_in.uop 617 io.lsq.forward.sqIdx := s1_in.uop.sqIdx 618 io.lsq.forward.sqIdxMask := DontCare 619 io.lsq.forward.mask := s1_in.mask 620 io.lsq.forward.pc := s1_in.uop.cf.pc // FIXME: remove it 621 622 // st-ld violation query 623 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 624 io.stld_nuke_query(w).valid && // query valid 625 isAfter(s1_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 626 // TODO: Fix me when vector instruction 627 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 628 (s1_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 629 })).asUInt.orR && !s1_tlb_miss 630 // Generate forwardMaskFast to wake up insts earlier 631 val s1_fwd_mask_fast = ((~(io.lsq.forward.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt)).asUInt & s1_in.mask) === 0.U 632 633 s1_out := s1_in 634 s1_out.vaddr := s1_vaddr 635 s1_out.paddr := s1_paddr_dup_lsu 636 s1_out.tlbMiss := s1_tlb_miss 637 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 638 s1_out.rsIdx := s1_in.rsIdx 639 s1_out.rep_info.debug := s1_in.uop.debugInfo 640 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 641 s1_out.lateKill := s1_fast_rep_kill 642 s1_out.delayedLoadError := s1_l2l_fwd_kill || s1_fast_rep_kill 643 644 when (!s1_fast_rep_kill) { 645 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 646 // af & pf exception were modified 647 s1_out.uop.cf.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 648 s1_out.uop.cf.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 649 } .otherwise { 650 s1_out.uop.cf.exceptionVec(loadAddrMisaligned) := false.B 651 s1_out.uop.cf.exceptionVec(loadAccessFault) := s1_fast_rep_kill 652 } 653 654 // pointer chasing 655 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 656 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 657 val s1_fu_op_type_not_ld = WireInit(false.B) 658 val s1_not_fast_match = WireInit(false.B) 659 val s1_addr_mismatch = WireInit(false.B) 660 val s1_addr_misaligned = WireInit(false.B) 661 val s1_ptr_chasing_canceled = WireInit(false.B) 662 val s1_cancel_ptr_chasing = WireInit(false.B) 663 664 if (EnableLoadToLoadForward) { 665 // Sometimes, we need to cancel the load-load forwarding. 666 // These can be put at S0 if timing is bad at S1. 667 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 668 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 669 // Case 1: the address is not 64-bit aligned or the fuOpType is not LD 670 s1_addr_misaligned := s1_ptr_chasing_vaddr(2, 0).orR 671 s1_fu_op_type_not_ld := io.ldin.bits.uop.ctrl.fuOpType =/= LSUOpType.ld 672 // Case 2: this is not a valid load-load pair 673 s1_not_fast_match := RegEnable(!io.ld_fast_match, s0_try_ptr_chasing) 674 // Case 3: this load-load uop is cancelled 675 s1_ptr_chasing_canceled := !io.ldin.valid 676 677 when (s1_try_ptr_chasing) { 678 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_fu_op_type_not_ld || s1_not_fast_match || s1_ptr_chasing_canceled 679 680 s1_in.uop := io.ldin.bits.uop 681 s1_in.rsIdx := io.rsIdx 682 s1_in.isFirstIssue := io.isFirstIssue 683 s1_vaddr_lo := Cat(s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 684 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 685 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_ptr_chasing_vaddr(5, 3), 0.U(3.W)) 686 687 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 688 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 689 s1_in.uop.debugInfo.tlbRespTime := GTimer() 690 } 691 when (s1_cancel_ptr_chasing) { 692 s1_kill := true.B 693 }.otherwise { 694 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.replay.fire && !io.fast_rep_in.fire 695 when (s1_try_ptr_chasing) { 696 io.ldin.ready := true.B 697 } 698 } 699 } 700 701 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 702 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 703 // to enable load-load, sqIdxMask must be calculated based on ldin.uop 704 // If the timing here is not OK, load-load forwarding has to be disabled. 705 // Or we calculate sqIdxMask at RS?? 706 io.lsq.forward.sqIdxMask := s1_sqIdx_mask 707 if (EnableLoadToLoadForward) { 708 when (s1_try_ptr_chasing) { 709 io.lsq.forward.sqIdxMask := UIntToMask(io.ldin.bits.uop.sqIdx.value, StoreQueueSize) 710 } 711 } 712 713 io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel 714 io.forward_mshr.mshrid := s1_out.mshrid 715 io.forward_mshr.paddr := s1_out.paddr 716 717 XSDebug(s1_valid, 718 p"S1: pc ${Hexadecimal(s1_out.uop.cf.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 719 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 720 721 // Pipeline 722 // -------------------------------------------------------------------------------- 723 // stage 2 724 // -------------------------------------------------------------------------------- 725 // s2: DCache resp 726 val s2_valid = RegInit(false.B) 727 val s2_in = Wire(new LqWriteBundle) 728 val s2_out = Wire(new LqWriteBundle) 729 val s2_kill = Wire(Bool()) 730 val s2_can_go = s3_ready 731 val s2_fire = s2_valid && !s2_kill && s2_can_go 732 733 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 734 s2_ready := !s2_valid || s2_kill || s3_ready 735 when (s1_fire) { s2_valid := true.B } 736 .elsewhen (s2_fire) { s2_valid := false.B } 737 .elsewhen (s2_kill) { s2_valid := false.B } 738 s2_in := RegEnable(s1_out, s1_fire) 739 740 val s2_pmp = WireInit(io.pmp) 741 val s2_static_pm = RegNext(io.tlb.resp.bits.static_pm) 742 when (s2_static_pm.valid) { 743 s2_pmp.ld := false.B 744 s2_pmp.st := false.B 745 s2_pmp.instr := false.B 746 s2_pmp.mmio := s2_static_pm.bits 747 } 748 val s2_prf = s2_in.isPrefetch 749 val s2_hw_prf = s2_in.isHWPrefetch 750 751 // exception that may cause load addr to be invalid / illegal 752 // if such exception happen, that inst and its exception info 753 // will be force writebacked to rob 754 val s2_exception_vec = WireInit(s2_in.uop.cf.exceptionVec) 755 when (!s2_in.lateKill) { 756 s2_exception_vec(loadAccessFault) := s2_in.uop.cf.exceptionVec(loadAccessFault) || s2_pmp.ld 757 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 758 when (s2_prf || s2_in.tlbMiss) { 759 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 760 } 761 } 762 val s2_exception = ExceptionNO.selectByFu(s2_exception_vec, lduCfg).asUInt.orR 763 764 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 765 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.forward_mshr.forward() 766 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 767 val s2_cache_hit = io.dcache.s2_hit || s2_fwd_frm_d_chan_or_mshr 768 769 // writeback access fault caused by ecc error / bus error 770 // * ecc data error is slow to generate, so we will not use it until load stage 3 771 // * in load stage 3, an extra signal io.load_error will be used to 772 val s2_actually_mmio = s2_pmp.mmio 773 val s2_mmio = !s2_prf && s2_actually_mmio && !s2_exception && !s2_in.tlbMiss 774 val s2_full_fwd = Wire(Bool()) 775 val s2_cache_miss = io.dcache.resp.bits.miss && !s2_fwd_frm_d_chan_or_mshr 776 val s2_mq_nack = io.dcache.s2_mq_nack 777 val s2_bank_conflict = io.dcache.s2_bank_conflict && !io.dcache.resp.bits.miss && !s2_full_fwd 778 val s2_wpu_pred_fail = io.dcache.s2_wpu_pred_fail 779 val s2_cache_rep = s2_bank_conflict || s2_wpu_pred_fail 780 val s2_cache_handled = io.dcache.resp.bits.handled 781 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && io.dcache.resp.bits.tag_error 782 val s2_fwd_fail = io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid 783 val s2_mem_amb = s2_in.uop.cf.storeSetHit && io.lsq.forward.addrInvalid && !s2_mmio && !s2_prf 784 val s2_data_inv = io.lsq.forward.dataInvalid && !s2_exception 785 val s2_dcache_kill = s2_pmp.ld || s2_pmp.mmio 786 val s2_troublem = !s2_exception && !s2_mmio && !s2_prf && !s2_in.lateKill 787 788 io.dcache.resp.ready := true.B 789 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_mmio || s2_prf) 790 assert(!(s2_valid && (s2_dcache_should_resp && !io.dcache.resp.valid)), "DCache response got lost") 791 792 // st-ld violation query 793 // NeedFastRecovery Valid when 794 // 1. Fast recovery query request Valid. 795 // 2. Load instruction is younger than requestors(store instructions). 796 // 3. Physical address match. 797 // 4. Data contains. 798 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 799 io.stld_nuke_query(w).valid && // query valid 800 isAfter(s2_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 801 // TODO: Fix me when vector instruction 802 (s2_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 803 (s2_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 804 })).asUInt.orR || s2_in.rep_info.nuke 805 806 // fast replay require 807 val s2_fast_rep = (s2_nuke || (!s2_mem_amb && !s2_in.tlbMiss && s2_cache_rep)) && s2_troublem 808 809 // need allocate new entry 810 val s2_can_query = !s2_in.tlbMiss && 811 !s2_mem_amb && 812 !s2_fast_rep && 813 !s2_in.rep_info.mem_amb && 814 s2_troublem 815 816 val s2_data_fwded = s2_cache_miss && (s2_full_fwd || s2_cache_tag_error) 817 818 // ld-ld violation require 819 io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 820 io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 821 io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 822 io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 823 io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd, true.B, !s2_cache_miss) && !s2_cache_rep 824 825 // st-ld violation require 826 io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 827 io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 828 io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 829 io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 830 io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd, true.B, !s2_cache_miss) && !s2_cache_rep 831 832 val s2_rar_nack = io.lsq.ldld_nuke_query.req.valid && !io.lsq.ldld_nuke_query.req.ready 833 val s2_raw_nack = io.lsq.stld_nuke_query.req.valid && !io.lsq.stld_nuke_query.req.ready 834 835 // merge forward result 836 // lsq has higher priority than sbuffer 837 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 838 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 839 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.lsq.forward.dataInvalid 840 // generate XLEN/8 Muxs 841 for (i <- 0 until VLEN / 8) { 842 s2_fwd_mask(i) := io.lsq.forward.forwardMask(i) || io.sbuffer.forwardMask(i) 843 s2_fwd_data(i) := Mux(io.lsq.forward.forwardMask(i), io.lsq.forward.forwardData(i), io.sbuffer.forwardData(i)) 844 } 845 846 XSDebug(s2_fire, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 847 s2_in.uop.cf.pc, 848 io.lsq.forward.forwardData.asUInt, io.lsq.forward.forwardMask.asUInt, 849 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 850 ) 851 852 // 853 s2_out := s2_in 854 s2_out.data := 0.U // data will be generated in load s3 855 s2_out.uop.ctrl.fpWen := s2_in.uop.ctrl.fpWen && !s2_exception 856 s2_out.mmio := s2_mmio 857 s2_out.uop.ctrl.flushPipe := false.B // io.fast_uop.valid && s2_mmio 858 s2_out.uop.cf.exceptionVec := s2_exception_vec 859 s2_out.forwardMask := s2_fwd_mask 860 s2_out.forwardData := s2_fwd_data 861 s2_out.handledByMSHR := s2_cache_handled 862 s2_out.miss := s2_cache_miss && !s2_full_fwd && s2_troublem 863 s2_out.feedbacked := io.feedback_fast.valid 864 865 // Generate replay signal caused by: 866 // * st-ld violation check 867 // * tlb miss 868 // * dcache replay 869 // * forward data invalid 870 // * dcache miss 871 s2_out.rep_info.tlb_miss := s2_in.tlbMiss 872 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 873 s2_out.rep_info.nuke := s2_nuke && s2_troublem 874 s2_out.rep_info.fwd_fail := s2_data_inv && s2_troublem 875 s2_out.rep_info.dcache_rep := s2_cache_rep && s2_troublem 876 s2_out.rep_info.dcache_miss := s2_out.miss 877 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 878 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 879 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 880 s2_out.rep_info.full_fwd := s2_data_fwded 881 s2_out.rep_info.data_inv_sq_idx := io.lsq.forward.dataInvalidSqIdx 882 s2_out.rep_info.addr_inv_sq_idx := io.lsq.forward.addrInvalidSqIdx 883 s2_out.rep_info.rep_carry := io.dcache.resp.bits.replayCarry 884 s2_out.rep_info.mshr_id := io.dcache.resp.bits.mshr_id 885 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 886 s2_out.rep_info.debug := s2_in.uop.debugInfo 887 888 // if forward fail, replay this inst from fetch 889 val debug_fwd_fail_rep = s2_fwd_fail && !s2_mmio && !s2_prf && !s2_in.tlbMiss 890 // if ld-ld violation is detected, replay from this inst from fetch 891 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_mmio && !s2_is_prefetch && !s2_in.tlbMiss 892 // io.out.bits.uop.ctrl.replayInst := false.B 893 894 // to be removed 895 io.feedback_fast.valid := s2_valid && // inst is valid 896 !s2_in.isLoadReplay && // already feedbacked 897 io.lq_rep_full && // LoadQueueReplay is full 898 s2_out.rep_info.need_rep && // need replay 899 !s2_exception && // no exception is triggered 900 !s2_hw_prf // not hardware prefetch 901 io.feedback_fast.bits.hit := false.B 902 io.feedback_fast.bits.flushState := s2_in.ptwBack 903 io.feedback_fast.bits.rsIdx := s2_in.rsIdx 904 io.feedback_fast.bits.sourceType := RSFeedbackType.lrqFull 905 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 906 907 // fast wakeup 908 io.fast_uop.valid := RegNext( 909 !io.dcache.s1_disable_fast_wakeup && 910 s1_valid && 911 !s1_kill && 912 !s1_fast_rep_kill && 913 !io.tlb.resp.bits.fast_miss && 914 !io.lsq.forward.dataInvalidFast 915 ) && (s2_valid && !io.feedback_fast.valid && !s2_out.rep_info.need_rep && !s2_mmio) 916 io.fast_uop.bits := RegNext(s1_out.uop) 917 918 // 919 io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, s1_fire) 920 io.prefetch_train.valid := s2_valid && !s2_in.mmio && !s2_in.tlbMiss 921 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 922 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss 923 io.prefetch_train.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 924 io.prefetch_train.bits.meta_access := io.dcache.resp.bits.meta_access 925 if (env.FPGAPlatform){ 926 io.dcache.s0_pc := DontCare 927 io.dcache.s1_pc := DontCare 928 io.dcache.s2_pc := DontCare 929 }else{ 930 io.dcache.s0_pc := s0_out.uop.cf.pc 931 io.dcache.s1_pc := s1_out.uop.cf.pc 932 io.dcache.s2_pc := s2_out.uop.cf.pc 933 } 934 io.dcache.s2_kill := s2_pmp.ld || s2_pmp.mmio || s2_kill 935 936 val s1_ld_left_fire = s1_valid && !s1_kill && !s1_fast_rep_kill && s2_ready 937 val s2_ld_valid_dup = RegInit(0.U(6.W)) 938 s2_ld_valid_dup := 0x0.U(6.W) 939 when (s1_ld_left_fire && !s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x3f.U(6.W) } 940 when (s1_kill || s1_fast_rep_kill || s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x0.U(6.W) } 941 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch))) 942 943 // Pipeline 944 // -------------------------------------------------------------------------------- 945 // stage 3 946 // -------------------------------------------------------------------------------- 947 // writeback and update load queue 948 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 949 val s3_in = RegEnable(s2_out, s2_fire) 950 val s3_out = Wire(Valid(new ExuOutput)) 951 val s3_cache_rep = RegEnable(s2_cache_rep && s2_troublem, s2_fire) 952 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 953 val s3_fast_rep = Wire(Bool()) 954 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 955 s3_ready := !s3_valid || s3_kill || io.ldout.ready 956 957 // s3 load fast replay 958 io.fast_rep_out.valid := s3_valid && s3_fast_rep && !s3_in.uop.robIdx.needFlush(io.redirect) 959 io.fast_rep_out.bits := s3_in 960 961 io.lsq.ldin.valid := s3_valid && (!s3_fast_rep || !io.fast_rep_out.ready) && !s3_in.feedbacked && !s3_in.lateKill 962 io.lsq.ldin.bits := s3_in 963 964 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 965 io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 966 io.lsq.ldin.bits.replacementUpdated := io.dcache.resp.bits.replacementUpdated 967 968 val s3_dly_ld_err = 969 if (EnableAccurateLoadError) { 970 (s3_in.delayedLoadError || io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 971 } else { 972 WireInit(false.B) 973 } 974 io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 975 io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 976 io.lsq.ldin.bits.dcacheRequireReplay := s3_cache_rep 977 978 val s3_vp_match_fail = RegNext(io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid) 979 val s3_ldld_rep_inst = 980 io.lsq.ldld_nuke_query.resp.valid && 981 io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 982 RegNext(io.csrCtrl.ldld_vio_check_enable) 983 984 val s3_rep_info = s3_in.rep_info 985 val s3_rep_frm_fetch = s3_vp_match_fail || s3_ldld_rep_inst 986 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 987 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_MA) || 988 s3_sel_rep_cause(LoadReplayCauses.C_TM) || 989 s3_sel_rep_cause(LoadReplayCauses.C_NK) 990 991 val s3_exception = ExceptionNO.selectByFu(s3_in.uop.cf.exceptionVec, lduCfg).asUInt.orR 992 when ((s3_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 993 io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 994 } .otherwise { 995 io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 996 } 997 998 // Int load, if hit, will be writebacked at s2 999 s3_out.valid := s3_valid && !io.lsq.ldin.bits.rep_info.need_rep && !s3_in.mmio && !s3_in.lateKill 1000 s3_out.bits.uop := s3_in.uop 1001 s3_out.bits.uop.cf.exceptionVec(loadAccessFault) := s3_dly_ld_err || s3_in.uop.cf.exceptionVec(loadAccessFault) 1002 s3_out.bits.uop.ctrl.replayInst := s3_rep_frm_fetch 1003 s3_out.bits.data := s3_in.data 1004 s3_out.bits.redirectValid := false.B 1005 s3_out.bits.redirect := DontCare 1006 s3_out.bits.debug.isMMIO := s3_in.mmio 1007 s3_out.bits.debug.isPerfCnt := false.B 1008 s3_out.bits.debug.paddr := s3_in.paddr 1009 s3_out.bits.debug.vaddr := s3_in.vaddr 1010 s3_out.bits.fflags := DontCare 1011 1012 when (s3_force_rep) { 1013 s3_out.bits.uop.cf.exceptionVec := 0.U.asTypeOf(s3_in.uop.cf.exceptionVec.cloneType) 1014 } 1015 1016 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1017 1018 io.lsq.ldin.bits.uop := s3_out.bits.uop 1019 1020 val s3_revoke = s3_exception || io.lsq.ldin.bits.rep_info.need_rep 1021 io.lsq.ldld_nuke_query.revoke := s3_revoke 1022 io.lsq.stld_nuke_query.revoke := s3_revoke 1023 1024 // feedback slow 1025 s3_fast_rep := (RegNext(s2_fast_rep) || 1026 (s3_in.rep_info.dcache_miss && io.l2_hint.valid && io.l2_hint.bits.sourceId === s3_in.rep_info.mshr_id)) && 1027 !s3_in.feedbacked && 1028 !s3_in.lateKill && 1029 !s3_rep_frm_fetch && 1030 !s3_exception 1031 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.fast_rep_out.ready) && !s3_in.feedbacked 1032 1033 // 1034 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting 1035 io.feedback_slow.bits.hit := !io.lsq.ldin.bits.rep_info.need_rep || io.lsq.ldin.ready 1036 io.feedback_slow.bits.flushState := s3_in.ptwBack 1037 io.feedback_slow.bits.rsIdx := s3_in.rsIdx 1038 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1039 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1040 1041 val s3_ld_wb_meta = Mux(s3_out.valid, s3_out.bits, io.lsq.uncache.bits) 1042 1043 // data from load queue refill 1044 val s3_ld_raw_data_frm_uncache = io.lsq.ld_raw_data 1045 val s3_merged_data_frm_uncache = s3_ld_raw_data_frm_uncache.mergedData() 1046 val s3_picked_data_frm_uncache = LookupTree(s3_ld_raw_data_frm_uncache.addrOffset, List( 1047 "b000".U -> s3_merged_data_frm_uncache(63, 0), 1048 "b001".U -> s3_merged_data_frm_uncache(63, 8), 1049 "b010".U -> s3_merged_data_frm_uncache(63, 16), 1050 "b011".U -> s3_merged_data_frm_uncache(63, 24), 1051 "b100".U -> s3_merged_data_frm_uncache(63, 32), 1052 "b101".U -> s3_merged_data_frm_uncache(63, 40), 1053 "b110".U -> s3_merged_data_frm_uncache(63, 48), 1054 "b111".U -> s3_merged_data_frm_uncache(63, 56) 1055 )) 1056 val s3_ld_data_frm_uncache = rdataHelper(s3_ld_raw_data_frm_uncache.uop, s3_picked_data_frm_uncache) 1057 1058 // data from dcache hit 1059 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1060 s3_ld_raw_data_frm_cache.respDcacheData := io.dcache.resp.bits.data_delayed 1061 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1062 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1063 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1064 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1065 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, s2_valid) 1066 s3_ld_raw_data_frm_cache.forwardData_D := RegEnable(s2_fwd_data_frm_d_chan, s2_valid) 1067 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, s2_valid) 1068 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1069 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, s2_valid) 1070 1071 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1072 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1073 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1074 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1075 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1076 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1077 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1078 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1079 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1080 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1081 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1082 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1083 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1084 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1085 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1086 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1087 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1088 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1089 )) 1090 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1091 1092 // FIXME: add 1 cycle delay ? 1093 io.lsq.uncache.ready := !s3_out.valid 1094 io.ldout.bits := s3_ld_wb_meta 1095 io.ldout.bits.data := Mux(s3_out.valid, s3_ld_data_frm_cache, s3_ld_data_frm_uncache) 1096 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) || 1097 io.lsq.uncache.valid && !io.lsq.uncache.bits.uop.robIdx.needFlush(io.redirect) && !s3_out.valid 1098 1099 1100 // fast load to load forward 1101 io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill // for debug only 1102 io.l2l_fwd_out.data := Mux(s3_ld_raw_data_frm_cache.addrOffset(3), s3_merged_data_frm_cache(127, 64), s3_merged_data_frm_cache(63, 0)) // load to load is for ld only 1103 io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1104 1105 // trigger 1106 val last_valid_data = RegNext(RegEnable(io.ldout.bits.data, io.ldout.fire)) 1107 val hit_ld_addr_trig_hit_vec = Wire(Vec(3, Bool())) 1108 val lq_ld_addr_trig_hit_vec = io.lsq.trigger.lqLoadAddrTriggerHitVec 1109 (0 until 3).map{i => { 1110 val tdata2 = RegNext(io.trigger(i).tdata2) 1111 val matchType = RegNext(io.trigger(i).matchType) 1112 val tEnable = RegNext(io.trigger(i).tEnable) 1113 1114 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s2_out.vaddr), tdata2, matchType, tEnable) 1115 io.trigger(i).addrHit := Mux(s3_out.valid, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1116 io.trigger(i).lastDataHit := TriggerCmp(last_valid_data, tdata2, matchType, tEnable) 1117 }} 1118 io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1119 1120 // FIXME: please move this part to LoadQueueReplay 1121 io.debug_ls := DontCare 1122 1123 // Topdown 1124 io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1125 io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1126 io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1127 io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1128 io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1129 io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1130 1131 // perf cnt 1132 XSPerfAccumulate("s0_in_valid", io.ldin.valid) 1133 XSPerfAccumulate("s0_in_block", io.ldin.valid && !io.ldin.fire) 1134 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1135 XSPerfAccumulate("s0_lsq_fire_first_issue", io.replay.fire) 1136 XSPerfAccumulate("s0_ldu_fire_first_issue", io.ldin.fire && s0_isFirstIssue) 1137 XSPerfAccumulate("s0_fast_replay_issue", io.fast_rep_in.fire) 1138 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1139 XSPerfAccumulate("s0_stall_dcache", s0_valid && !io.dcache.req.ready) 1140 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12)) 1141 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12)) 1142 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1143 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1144 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1145 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1146 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1147 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.prefetch_req.valid && !s0_hw_prf_select) 1148 XSPerfAccumulate("s0_hardware_prefetch_total", io.prefetch_req.valid) 1149 1150 XSPerfAccumulate("s1_in_valid", s1_valid) 1151 XSPerfAccumulate("s1_in_fire", s1_fire) 1152 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1153 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1154 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1155 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1156 1157 XSPerfAccumulate("s2_in_valid", s2_valid) 1158 XSPerfAccumulate("s2_in_fire", s2_fire) 1159 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1160 XSPerfAccumulate("s2_dcache_miss", s2_fire && s2_cache_miss) 1161 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && s2_cache_miss && s2_in.isFirstIssue) 1162 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1163 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_cache_miss && s2_full_fwd) 1164 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1165 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1166 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && s2_cache_rep) // ignore prefetch for mshr full / miss req port conflict 1167 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && s2_cache_miss) // prefetch req miss in l1 1168 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !s2_cache_miss) // prefetch req hit in l1 1169 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && s2_cache_miss && !s2_cache_rep) // prefetch a missed line in l1, and l1 accepted it 1170 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fwd_frm_d_chan && s2_fwd_data_valid) 1171 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fwd_frm_mshr && s2_fwd_data_valid) 1172 1173 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1174 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1175 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1176 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1177 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1178 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1179 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1180 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1181 1182 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1183 // hardware performance counter 1184 val perfEvents = Seq( 1185 ("load_s0_in_fire ", s0_fire ), 1186 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1187 ("stall_dcache ", s0_valid && s0_can_go && !io.dcache.req.ready ), 1188 ("load_s1_in_fire ", s0_fire ), 1189 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1190 ("load_s2_in_fire ", s1_fire ), 1191 ("load_s2_dcache_miss ", s2_fire && io.dcache.resp.bits.miss ), 1192 ) 1193 generatePerfEvent() 1194 1195 when(io.ldout.fire){ 1196 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 1197 } 1198 // end 1199}