1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.rob.RobPtr 31import xiangshan.backend.fu._ 32import xiangshan.cache._ 33import xiangshan.cache.wpu.ReplayCarry 34import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 35import xiangshan.mem.mdp._ 36 37class HybridUnit(implicit p: Parameters) extends XSModule 38 with HasLoadHelper 39 with HasPerfEvents 40 with HasDCacheParameters 41 with HasCircularQueuePtrHelper 42{ 43 val io = IO(new Bundle() { 44 // control 45 val redirect = Flipped(ValidIO(new Redirect)) 46 val csrCtrl = Flipped(new CustomCSRCtrlIO) 47 48 // flow in 49 val lsin = Flipped(Decoupled(new MemExuInput)) 50 51 // flow out 52 val ldout = DecoupledIO(new MemExuOutput) 53 val stout = DecoupledIO(new MemExuOutput) 54 55 val ldu_io = new Bundle() { 56 // data path 57 val sbuffer = new LoadForwardQueryIO 58 val lsq = new LoadToLsqIO 59 val tl_d_channel = Input(new DcacheToLduForwardIO) 60 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 61 val refill = Flipped(ValidIO(new Refill)) 62 val l2_hint = Input(Valid(new L2ToL1Hint)) 63 64 // fast wakeup 65 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 66 67 // trigger 68 val trigger = Vec(3, new LoadUnitTriggerIO) 69 70 // load to load fast path 71 val l2l_fwd_in = Input(new LoadToLoadIO) 72 val l2l_fwd_out = Output(new LoadToLoadIO) 73 74 val ld_fast_match = Input(Bool()) 75 val ld_fast_fuOpType = Input(UInt()) 76 val ld_fast_imm = Input(UInt(12.W)) 77 78 // hardware prefetch to l1 cache req 79 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) 80 81 // iq cancel 82 val ldCancel = Output(new LoadCancelIO()) // use to cancel the uops waked by this load, and cancel load 83 84 // load ecc error 85 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 86 87 // schedule error query 88 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 89 90 // queue-based replay 91 val replay = Flipped(Decoupled(new LsPipelineBundle)) 92 val lq_rep_full = Input(Bool()) 93 94 // misc 95 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 96 97 // Load fast replay path 98 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 99 val fast_rep_out = Decoupled(new LqWriteBundle) 100 101 // perf 102 val debug_ls = Output(new DebugLsInfoBundle) 103 val lsTopdownInfo = Output(new LsTopdownInfo) 104 } 105 106 val stu_io = new Bundle() { 107 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 108 val issue = Valid(new MemExuInput) 109 val lsq = ValidIO(new LsPipelineBundle) 110 val lsq_replenish = Output(new LsPipelineBundle()) 111 val stld_nuke_query = Valid(new StoreNukeQueryIO) 112 val st_mask_out = Valid(new StoreMaskBundle) 113 val debug_ls = Output(new DebugLsInfoBundle) 114 } 115 116 // prefetch 117 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to sms 118 val prefetch_train_l1 = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to stream & stride 119 val canAcceptLowConfPrefetch = Output(Bool()) 120 val canAcceptHighConfPrefetch = Output(Bool()) 121 val correctMissTrain = Input(Bool()) 122 123 // data path 124 val tlb = new TlbRequestIO(2) 125 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 126 val dcache = new DCacheLoadIO 127 128 // rs feedback 129 val feedback_fast = ValidIO(new RSFeedback) // stage 2 130 val feedback_slow = ValidIO(new RSFeedback) // stage 3 131 }) 132 133 val s1_ready, s2_ready, s3_ready, sx_can_go = WireInit(false.B) 134 135 // Pipeline 136 // -------------------------------------------------------------------------------- 137 // stage 0 138 // -------------------------------------------------------------------------------- 139 // generate addr, use addr to query DCache and DTLB 140 val s0_valid = Wire(Bool()) 141 val s0_kill = Wire(Bool()) 142 val s0_vaddr = Wire(UInt(VAddrBits.W)) 143 val s0_mask = Wire(UInt((VLEN/8).W)) 144 val s0_uop = Wire(new DynInst) 145 val s0_has_rob_entry = Wire(Bool()) 146 val s0_rsIdx = Wire(UInt(log2Up(MemIQSizeMax).W)) 147 val s0_mshrid = Wire(UInt()) 148 val s0_try_l2l = Wire(Bool()) 149 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 150 val s0_isFirstIssue = Wire(Bool()) 151 val s0_fast_rep = Wire(Bool()) 152 val s0_ld_rep = Wire(Bool()) 153 val s0_l2l_fwd = Wire(Bool()) 154 val s0_sched_idx = Wire(UInt()) 155 val s0_can_go = s1_ready 156 val s0_fire = s0_valid && s0_can_go 157 val s0_out = Wire(new LqWriteBundle) 158 159 // load flow select/gen 160 // src0: super load replayed by LSQ (cache miss replay) (io.ldu_io.replay) 161 // src1: fast load replay (io.ldu_io.fast_rep_in) 162 // src2: load replayed by LSQ (io.ldu_io.replay) 163 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 164 // src4: int read / software prefetch first issue from RS (io.in) 165 // src5: vec read first issue from RS (TODO) 166 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 167 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 168 // priority: high to low 169 val s0_ld_flow = FuType.isLoad(s0_uop.fuType) 170 val s0_rep_stall = io.lsin.valid && isAfter(io.ldu_io.replay.bits.uop.robIdx, io.lsin.bits.uop.robIdx) 171 val s0_super_ld_rep_valid = io.ldu_io.replay.valid && io.ldu_io.replay.bits.forward_tlDchannel 172 val s0_ld_fast_rep_valid = io.ldu_io.fast_rep_in.valid 173 val s0_ld_rep_valid = io.ldu_io.replay.valid && !io.ldu_io.replay.bits.forward_tlDchannel && !s0_rep_stall 174 val s0_high_conf_prf_valid = io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence > 0.U 175 val s0_int_iss_valid = io.lsin.valid // int flow first issue or software prefetch 176 val s0_vec_iss_valid = WireInit(false.B) // TODO 177 val s0_l2l_fwd_valid = io.ldu_io.l2l_fwd_in.valid && io.ldu_io.ld_fast_match 178 val s0_low_conf_prf_valid = io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence === 0.U 179 dontTouch(s0_super_ld_rep_valid) 180 dontTouch(s0_ld_fast_rep_valid) 181 dontTouch(s0_ld_rep_valid) 182 dontTouch(s0_high_conf_prf_valid) 183 dontTouch(s0_int_iss_valid) 184 dontTouch(s0_vec_iss_valid) 185 dontTouch(s0_l2l_fwd_valid) 186 dontTouch(s0_low_conf_prf_valid) 187 188 // load flow source ready 189 val s0_super_ld_rep_ready = WireInit(true.B) 190 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 191 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 192 !s0_ld_fast_rep_valid 193 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 194 !s0_ld_fast_rep_valid && 195 !s0_ld_rep_valid 196 197 val s0_int_iss_ready = !s0_super_ld_rep_valid && 198 !s0_ld_fast_rep_valid && 199 !s0_ld_rep_valid && 200 !s0_high_conf_prf_valid 201 202 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 203 !s0_ld_fast_rep_valid && 204 !s0_ld_rep_valid && 205 !s0_high_conf_prf_valid && 206 !s0_int_iss_valid 207 208 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 209 !s0_ld_fast_rep_valid && 210 !s0_ld_rep_valid && 211 !s0_high_conf_prf_valid && 212 !s0_int_iss_valid && 213 !s0_vec_iss_valid 214 215 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 216 !s0_ld_fast_rep_valid && 217 !s0_ld_rep_valid && 218 !s0_high_conf_prf_valid && 219 !s0_int_iss_valid && 220 !s0_vec_iss_valid && 221 !s0_l2l_fwd_valid 222 dontTouch(s0_super_ld_rep_ready) 223 dontTouch(s0_ld_fast_rep_ready) 224 dontTouch(s0_ld_rep_ready) 225 dontTouch(s0_high_conf_prf_ready) 226 dontTouch(s0_int_iss_ready) 227 dontTouch(s0_vec_iss_ready) 228 dontTouch(s0_l2l_fwd_ready) 229 dontTouch(s0_low_conf_prf_ready) 230 231 // load flow source select (OH) 232 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 233 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 234 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 235 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 236 s0_low_conf_prf_ready && s0_low_conf_prf_valid 237 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 238 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 239 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 240 assert(!s0_vec_iss_select) // to be added 241 dontTouch(s0_super_ld_rep_select) 242 dontTouch(s0_ld_fast_rep_select) 243 dontTouch(s0_ld_rep_select) 244 dontTouch(s0_hw_prf_select) 245 dontTouch(s0_int_iss_select) 246 dontTouch(s0_vec_iss_select) 247 dontTouch(s0_l2l_fwd_select) 248 249 s0_valid := (s0_super_ld_rep_valid || 250 s0_ld_fast_rep_valid || 251 s0_ld_rep_valid || 252 s0_high_conf_prf_valid || 253 s0_int_iss_valid || 254 s0_vec_iss_valid || 255 s0_l2l_fwd_valid || 256 s0_low_conf_prf_valid) && io.dcache.req.ready && !s0_kill 257 258 // which is S0's out is ready and dcache is ready 259 val s0_try_ptr_chasing = s0_l2l_fwd_select 260 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.dcache.req.ready 261 val s0_ptr_chasing_vaddr = io.ldu_io.l2l_fwd_in.data(5, 0) +& io.ldu_io.ld_fast_imm(5, 0) 262 val s0_ptr_chasing_canceled = WireInit(false.B) 263 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 264 265 // prefetch related ctrl signal 266 val s0_prf = Wire(Bool()) 267 val s0_prf_rd = Wire(Bool()) 268 val s0_prf_wr = Wire(Bool()) 269 val s0_hw_prf = s0_hw_prf_select 270 271 io.canAcceptLowConfPrefetch := s0_low_conf_prf_ready 272 io.canAcceptHighConfPrefetch := s0_high_conf_prf_ready 273 274 // query DTLB 275 io.tlb.req.valid := s0_valid 276 io.tlb.req.bits.cmd := Mux(s0_prf, 277 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 278 Mux(s0_ld_flow, TlbCmd.read, TlbCmd.write) 279 ) 280 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.paddr, s0_vaddr) 281 io.tlb.req.bits.size := LSUOpType.size(s0_uop.fuOpType) 282 io.tlb.req.bits.kill := s0_kill 283 io.tlb.req.bits.memidx.is_ld := s0_ld_flow 284 io.tlb.req.bits.memidx.is_st := !s0_ld_flow 285 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 286 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 287 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 288 io.tlb.req.bits.debug.pc := s0_uop.pc 289 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 290 291 // query DCache 292 io.dcache.req.valid := s0_valid 293 io.dcache.req.bits.cmd := Mux(s0_prf_rd, 294 MemoryOpConstants.M_PFR, 295 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, 296 Mux(s0_ld_flow, MemoryOpConstants.M_XRD, MemoryOpConstants.M_XWR)) 297 ) 298 io.dcache.req.bits.vaddr := s0_vaddr 299 io.dcache.req.bits.mask := s0_mask 300 io.dcache.req.bits.data := DontCare 301 io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 302 io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, 303 Mux(s0_ld_flow, LOAD_SOURCE.U, STORE_SOURCE.U)) 304 io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 305 io.dcache.req.bits.replayCarry := s0_rep_carry 306 io.dcache.req.bits.id := DontCare // TODO: update cache meta 307 io.dcache.pf_source := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.pf_source.value, L1_HW_PREFETCH_NULL) 308 309 // load flow priority mux 310 def fromNullSource() = { 311 s0_vaddr := 0.U 312 s0_mask := 0.U 313 s0_uop := 0.U.asTypeOf(new DynInst) 314 s0_try_l2l := false.B 315 s0_has_rob_entry := false.B 316 s0_rsIdx := 0.U 317 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 318 s0_mshrid := 0.U 319 s0_isFirstIssue := false.B 320 s0_fast_rep := false.B 321 s0_ld_rep := false.B 322 s0_l2l_fwd := false.B 323 s0_prf := false.B 324 s0_prf_rd := false.B 325 s0_prf_wr := false.B 326 s0_sched_idx := 0.U 327 } 328 329 def fromFastReplaySource(src: LqWriteBundle) = { 330 s0_vaddr := src.vaddr 331 s0_mask := src.mask 332 s0_uop := src.uop 333 s0_try_l2l := false.B 334 s0_has_rob_entry := src.hasROBEntry 335 s0_rep_carry := src.rep_info.rep_carry 336 s0_mshrid := src.rep_info.mshr_id 337 s0_rsIdx := src.rsIdx 338 s0_isFirstIssue := false.B 339 s0_fast_rep := true.B 340 s0_ld_rep := src.isLoadReplay 341 s0_l2l_fwd := false.B 342 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 343 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 344 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 345 s0_sched_idx := src.schedIndex 346 } 347 348 def fromNormalReplaySource(src: LsPipelineBundle) = { 349 s0_vaddr := src.vaddr 350 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 351 s0_uop := src.uop 352 s0_try_l2l := false.B 353 s0_has_rob_entry := true.B 354 s0_rsIdx := src.rsIdx 355 s0_rep_carry := src.replayCarry 356 s0_mshrid := src.mshrid 357 s0_isFirstIssue := false.B 358 s0_fast_rep := false.B 359 s0_ld_rep := true.B 360 s0_l2l_fwd := false.B 361 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 362 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 363 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 364 s0_sched_idx := src.schedIndex 365 } 366 367 def fromPrefetchSource(src: L1PrefetchReq) = { 368 s0_vaddr := src.getVaddr() 369 s0_mask := 0.U 370 s0_uop := DontCare 371 s0_try_l2l := false.B 372 s0_has_rob_entry := false.B 373 s0_rsIdx := 0.U 374 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 375 s0_mshrid := 0.U 376 s0_isFirstIssue := false.B 377 s0_fast_rep := false.B 378 s0_ld_rep := false.B 379 s0_l2l_fwd := false.B 380 s0_prf := true.B 381 s0_prf_rd := !src.is_store 382 s0_prf_wr := src.is_store 383 s0_sched_idx := 0.U 384 } 385 386 def fromIntIssueSource(src: MemExuInput) = { 387 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 388 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 389 s0_uop := src.uop 390 s0_try_l2l := false.B 391 s0_has_rob_entry := true.B 392 s0_rsIdx := src.iqIdx 393 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 394 s0_mshrid := 0.U 395 s0_isFirstIssue := true.B 396 s0_fast_rep := false.B 397 s0_ld_rep := false.B 398 s0_l2l_fwd := false.B 399 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 400 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 401 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 402 s0_sched_idx := 0.U 403 } 404 405 def fromVecIssueSource() = { 406 s0_vaddr := 0.U 407 s0_mask := 0.U 408 s0_uop := 0.U.asTypeOf(new DynInst) 409 s0_try_l2l := false.B 410 s0_has_rob_entry := false.B 411 s0_rsIdx := 0.U 412 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 413 s0_mshrid := 0.U 414 s0_isFirstIssue := false.B 415 s0_fast_rep := false.B 416 s0_ld_rep := false.B 417 s0_l2l_fwd := false.B 418 s0_prf := false.B 419 s0_prf_rd := false.B 420 s0_prf_wr := false.B 421 s0_sched_idx := 0.U 422 } 423 424 def fromLoadToLoadSource(src: LoadToLoadIO) = { 425 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 426 s0_mask := genVWmask(s0_vaddr, io.ldu_io.ld_fast_fuOpType(1, 0)) 427 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 428 // Assume the pointer chasing is always ld. 429 s0_uop.fuOpType := io.ldu_io.ld_fast_fuOpType 430 s0_try_l2l := true.B 431 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 432 // because these signals will be updated in S1 433 s0_has_rob_entry := false.B 434 s0_rsIdx := 0.U 435 s0_mshrid := 0.U 436 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 437 s0_isFirstIssue := true.B 438 s0_fast_rep := false.B 439 s0_ld_rep := false.B 440 s0_l2l_fwd := true.B 441 s0_prf := false.B 442 s0_prf_rd := false.B 443 s0_prf_wr := false.B 444 s0_sched_idx := 0.U 445 } 446 447 // set default 448 s0_uop := DontCare 449 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.ldu_io.replay.bits) } 450 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.ldu_io.fast_rep_in.bits) } 451 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.ldu_io.replay.bits) } 452 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.ldu_io.prefetch_req.bits) } 453 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.lsin.bits) } 454 .elsewhen (s0_vec_iss_select) { fromVecIssueSource() } 455 .otherwise { 456 if (EnableLoadToLoadForward) { 457 fromLoadToLoadSource(io.ldu_io.l2l_fwd_in) 458 } else { 459 fromNullSource() 460 } 461 } 462 463 // address align check 464 val s0_addr_aligned = LookupTree(s0_uop.fuOpType(1, 0), List( 465 "b00".U -> true.B, //b 466 "b01".U -> (s0_vaddr(0) === 0.U), //h 467 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 468 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 469 )) 470 471 // accept load flow if dcache ready (tlb is always ready) 472 // TODO: prefetch need writeback to loadQueueFlag 473 s0_out := DontCare 474 s0_out.rsIdx := s0_rsIdx 475 s0_out.vaddr := s0_vaddr 476 s0_out.mask := s0_mask 477 s0_out.uop := s0_uop 478 s0_out.isFirstIssue := s0_isFirstIssue 479 s0_out.hasROBEntry := s0_has_rob_entry 480 s0_out.isPrefetch := s0_prf 481 s0_out.isHWPrefetch := s0_hw_prf 482 s0_out.isFastReplay := s0_fast_rep 483 s0_out.isLoadReplay := s0_ld_rep 484 s0_out.isFastPath := s0_l2l_fwd 485 s0_out.mshrid := s0_mshrid 486 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned && s0_ld_flow 487 s0_out.uop.exceptionVec(storeAddrMisaligned) := !s0_addr_aligned && !s0_ld_flow 488 s0_out.forward_tlDchannel := s0_super_ld_rep_select 489 when(io.tlb.req.valid && s0_isFirstIssue) { 490 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 491 }.otherwise{ 492 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 493 } 494 s0_out.schedIndex := s0_sched_idx 495 496 // load fast replay 497 io.ldu_io.fast_rep_in.ready := (s0_can_go && io.dcache.req.ready && s0_ld_fast_rep_ready) 498 499 // load flow source ready 500 // cache missed load has highest priority 501 // always accept cache missed load flow from load replay queue 502 io.ldu_io.replay.ready := (s0_can_go && io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 503 504 // accept load flow from rs when: 505 // 1) there is no lsq-replayed load 506 // 2) there is no fast replayed load 507 // 3) there is no high confidence prefetch request 508 io.lsin.ready := (s0_can_go && (io.dcache.req.ready || !s0_ld_flow) && s0_int_iss_ready) 509 510 // for hw prefetch load flow feedback, to be added later 511 // io.prefetch_in.ready := s0_hw_prf_select 512 513 // dcache replacement extra info 514 // TODO: should prefetch load update replacement? 515 io.dcache.replacementUpdated := Mux(s0_ld_rep_select || s0_super_ld_rep_select, io.ldu_io.replay.bits.replacementUpdated, false.B) 516 517 io.stu_io.prefetch_req.ready := true.B 518 519 520 io.stu_io.st_mask_out.valid := s0_valid && !s0_ld_flow 521 io.stu_io.st_mask_out.bits.mask := s0_out.mask 522 io.stu_io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 523 524 // load debug 525 XSDebug(io.dcache.req.fire && s0_ld_flow, 526 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 527 ) 528 XSDebug(s0_valid && s0_ld_flow, 529 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lqIdx ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 530 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 531 532 // store debug 533 XSDebug(io.dcache.req.fire && !s0_ld_flow, 534 p"[DCACHE STORE REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 535 ) 536 XSDebug(s0_valid && !s0_ld_flow, 537 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, sqIdx ${Hexadecimal(s0_out.uop.sqIdx.asUInt)}, " + 538 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 539 540 541 // Pipeline 542 // -------------------------------------------------------------------------------- 543 // stage 1 544 // -------------------------------------------------------------------------------- 545 // TLB resp (send paddr to dcache) 546 val s1_valid = RegInit(false.B) 547 val s1_in = Wire(new LqWriteBundle) 548 val s1_out = Wire(new LqWriteBundle) 549 val s1_kill = Wire(Bool()) 550 val s1_can_go = s2_ready 551 val s1_fire = s1_valid && !s1_kill && s1_can_go 552 val s1_ld_flow = RegNext(s0_ld_flow) 553 554 s1_ready := !s1_valid || s1_kill || s2_ready 555 when (s0_fire) { s1_valid := true.B } 556 .elsewhen (s1_fire) { s1_valid := false.B } 557 .elsewhen (s1_kill) { s1_valid := false.B } 558 s1_in := RegEnable(s0_out, s0_fire) 559 560 val s1_fast_rep_dly_err = RegNext(io.ldu_io.fast_rep_in.bits.delayedLoadError) 561 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 562 val s1_l2l_fwd_dly_err = RegNext(io.ldu_io.l2l_fwd_in.dly_ld_err) 563 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 564 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 565 val s1_vaddr_hi = Wire(UInt()) 566 val s1_vaddr_lo = Wire(UInt()) 567 val s1_vaddr = Wire(UInt()) 568 val s1_paddr_dup_lsu = Wire(UInt()) 569 val s1_paddr_dup_dcache = Wire(UInt()) 570 val s1_ld_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 571 val s1_st_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR // af & pf exception were modified below. 572 val s1_exception = (s1_ld_flow && s1_ld_exception) || (!s1_ld_flow && s1_st_exception) 573 val s1_tlb_miss = io.tlb.resp.bits.miss 574 val s1_prf = s1_in.isPrefetch 575 val s1_hw_prf = s1_in.isHWPrefetch 576 val s1_sw_prf = s1_prf && !s1_hw_prf 577 val s1_tlb_memidx = io.tlb.resp.bits.memidx 578 579 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 580 s1_vaddr_lo := s1_in.vaddr(5, 0) 581 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 582 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 583 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 584 585 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && 586 s1_tlb_memidx.idx === s1_in.uop.lqIdx.value && s1_ld_flow) { 587 // printf("Load idx = %d\n", s1_tlb_memidx.idx) 588 s1_out.uop.debugInfo.tlbRespTime := GTimer() 589 } .elsewhen(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && 590 s1_tlb_memidx.idx === s1_out.uop.sqIdx.value && !s1_ld_flow) { 591 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 592 s1_out.uop.debugInfo.tlbRespTime := GTimer() 593 } 594 595 io.tlb.req_kill := s1_kill 596 io.tlb.resp.ready := true.B 597 598 io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 599 io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 600 io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception || !s1_ld_flow 601 602 // store to load forwarding 603 io.ldu_io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 604 io.ldu_io.sbuffer.vaddr := s1_vaddr 605 io.ldu_io.sbuffer.paddr := s1_paddr_dup_lsu 606 io.ldu_io.sbuffer.uop := s1_in.uop 607 io.ldu_io.sbuffer.sqIdx := s1_in.uop.sqIdx 608 io.ldu_io.sbuffer.mask := s1_in.mask 609 io.ldu_io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 610 611 io.ldu_io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 612 io.ldu_io.lsq.forward.vaddr := s1_vaddr 613 io.ldu_io.lsq.forward.paddr := s1_paddr_dup_lsu 614 io.ldu_io.lsq.forward.uop := s1_in.uop 615 io.ldu_io.lsq.forward.sqIdx := s1_in.uop.sqIdx 616 io.ldu_io.lsq.forward.sqIdxMask := 0.U 617 io.ldu_io.lsq.forward.mask := s1_in.mask 618 io.ldu_io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 619 620 // st-ld violation query 621 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 622 io.ldu_io.stld_nuke_query(w).valid && // query valid 623 isAfter(s1_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 624 // TODO: Fix me when vector instruction 625 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 626 (s1_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 627 })).asUInt.orR && !s1_tlb_miss && s1_ld_flow 628 629 s1_out := s1_in 630 s1_out.vaddr := s1_vaddr 631 s1_out.paddr := s1_paddr_dup_lsu 632 s1_out.tlbMiss := s1_tlb_miss 633 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 634 s1_out.rsIdx := s1_in.rsIdx 635 s1_out.rep_info.debug := s1_in.uop.debugInfo 636 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 637 s1_out.lateKill := s1_late_kill 638 639 when (s1_ld_flow) { 640 when (!s1_late_kill) { 641 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 642 // af & pf exception were modified 643 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 644 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 645 } .otherwise { 646 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B 647 s1_out.uop.exceptionVec(loadAccessFault) := s1_late_kill 648 } 649 } .otherwise { 650 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 651 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 652 } 653 654 // pointer chasing 655 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 656 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 657 val s1_fu_op_type_not_ld = WireInit(false.B) 658 val s1_not_fast_match = WireInit(false.B) 659 val s1_addr_mismatch = WireInit(false.B) 660 val s1_addr_misaligned = WireInit(false.B) 661 val s1_ptr_chasing_canceled = WireInit(false.B) 662 val s1_cancel_ptr_chasing = WireInit(false.B) 663 664 s1_kill := s1_late_kill || 665 s1_cancel_ptr_chasing || 666 s1_in.uop.robIdx.needFlush(io.redirect) || 667 RegEnable(s0_kill, false.B, io.lsin.valid || io.ldu_io.replay.valid || io.ldu_io.l2l_fwd_in.valid || io.ldu_io.fast_rep_in.valid) 668 669 if (EnableLoadToLoadForward) { 670 // Sometimes, we need to cancel the load-load forwarding. 671 // These can be put at S0 if timing is bad at S1. 672 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 673 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ldu_io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 674 // Case 1: the address is misaligned, kill s1 675 s1_addr_misaligned := LookupTree(s1_in.uop.fuOpType(1, 0), List( 676 "b00".U -> false.B, //b 677 "b01".U -> (s1_vaddr(0) =/= 0.U), //h 678 "b10".U -> (s1_vaddr(1, 0) =/= 0.U), //w 679 "b11".U -> (s1_vaddr(2, 0) =/= 0.U) //d 680 )) 681 // Case 2: this load-load uop is cancelled 682 s1_ptr_chasing_canceled := !io.lsin.valid 683 684 when (s1_try_ptr_chasing) { 685 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled 686 687 s1_in.uop := io.lsin.bits.uop 688 s1_in.rsIdx := io.lsin.bits.iqIdx 689 s1_in.isFirstIssue := io.lsin.bits.isFirstIssue 690 s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) 691 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 692 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 693 694 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 695 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 696 s1_in.uop.debugInfo.tlbRespTime := GTimer() 697 } 698 when (!s1_cancel_ptr_chasing) { 699 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.ldu_io.replay.fire && !io.ldu_io.fast_rep_in.fire 700 when (s1_try_ptr_chasing) { 701 io.lsin.ready := true.B 702 } 703 } 704 } 705 706 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 707 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 708 // to enable load-load, sqIdxMask must be calculated based on lsin.uop 709 // If the timing here is not OK, load-load forwarding has to be disabled. 710 // Or we calculate sqIdxMask at RS?? 711 io.ldu_io.lsq.forward.sqIdxMask := s1_sqIdx_mask 712 if (EnableLoadToLoadForward) { 713 when (s1_try_ptr_chasing) { 714 io.ldu_io.lsq.forward.sqIdxMask := UIntToMask(io.lsin.bits.uop.sqIdx.value, StoreQueueSize) 715 } 716 } 717 718 io.ldu_io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel && s1_ld_flow 719 io.ldu_io.forward_mshr.mshrid := s1_out.mshrid 720 io.ldu_io.forward_mshr.paddr := s1_out.paddr 721 722 723 // load debug 724 XSDebug(s1_valid && s1_ld_flow, 725 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 726 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 727 728 // store debug 729 XSDebug(s1_valid && !s1_ld_flow, 730 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.sqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 731 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 732 733 // store out 734 io.stu_io.lsq.valid := s1_valid && !s1_ld_flow 735 io.stu_io.lsq.bits := s1_out 736 io.stu_io.lsq.bits.miss := s1_tlb_miss 737 738 io.stu_io.issue.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow 739 io.stu_io.issue.bits := RegEnable(io.lsin.bits, io.lsin.fire) 740 741 // st-ld violation dectect request 742 io.stu_io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow 743 io.stu_io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 744 io.stu_io.stld_nuke_query.bits.paddr := s1_paddr_dup_lsu 745 io.stu_io.stld_nuke_query.bits.mask := s1_in.mask 746 747 // Pipeline 748 // -------------------------------------------------------------------------------- 749 // stage 2 750 // -------------------------------------------------------------------------------- 751 // s2: DCache resp 752 val s2_valid = RegInit(false.B) 753 val s2_in = Wire(new LqWriteBundle) 754 val s2_out = Wire(new LqWriteBundle) 755 val s2_kill = Wire(Bool()) 756 val s2_can_go = s3_ready 757 val s2_fire = s2_valid && !s2_kill && s2_can_go 758 759 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 760 s2_ready := !s2_valid || s2_kill || s3_ready 761 when (s1_fire) { s2_valid := true.B } 762 .elsewhen (s2_fire) { s2_valid := false.B } 763 .elsewhen (s2_kill) { s2_valid := false.B } 764 s2_in := RegEnable(s1_out, s1_fire) 765 766 val s2_pmp = WireInit(io.pmp) 767 768 val s2_prf = s2_in.isPrefetch 769 val s2_hw_prf = s2_in.isHWPrefetch 770 val s2_ld_flow = RegEnable(s1_ld_flow, s1_fire) 771 772 // exception that may cause load addr to be invalid / illegal 773 // if such exception happen, that inst and its exception info 774 // will be force writebacked to rob 775 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 776 when (s2_ld_flow) { 777 when (!s2_in.lateKill) { 778 s2_exception_vec(loadAccessFault) := s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld 779 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 780 when (s2_prf || s2_in.tlbMiss) { 781 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 782 } 783 } 784 } .otherwise { 785 s2_exception_vec(storeAccessFault) := s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st 786 when (s2_prf || s2_in.tlbMiss) { 787 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 788 } 789 } 790 val s2_ld_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR && s2_ld_flow 791 val s2_st_exception = ExceptionNO.selectByFu(s2_exception_vec, StaCfg).asUInt.orR && !s2_ld_flow 792 val s2_exception = s2_ld_exception || s2_st_exception 793 794 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.ldu_io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 795 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.ldu_io.forward_mshr.forward() 796 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 797 798 // writeback access fault caused by ecc error / bus error 799 // * ecc data error is slow to generate, so we will not use it until load stage 3 800 // * in load stage 3, an extra signal io.load_error will be used to 801 val s2_actually_mmio = s2_pmp.mmio 802 val s2_mmio = !s2_prf && 803 s2_actually_mmio && 804 !s2_exception && 805 !s2_in.tlbMiss 806 val s2_full_fwd = Wire(Bool()) 807 val s2_mem_amb = s2_in.uop.storeSetHit && 808 io.ldu_io.lsq.forward.addrInvalid 809 810 val s2_tlb_miss = s2_in.tlbMiss 811 val s2_fwd_fail = io.ldu_io.lsq.forward.dataInvalid 812 val s2_dcache_miss = io.dcache.resp.bits.miss && 813 !s2_fwd_frm_d_chan_or_mshr && 814 !s2_full_fwd 815 816 val s2_mq_nack = io.dcache.s2_mq_nack && 817 !s2_fwd_frm_d_chan_or_mshr && 818 !s2_full_fwd 819 820 val s2_bank_conflict = io.dcache.s2_bank_conflict && 821 !s2_fwd_frm_d_chan_or_mshr && 822 !s2_full_fwd 823 824 val s2_wpu_pred_fail = io.dcache.s2_wpu_pred_fail && 825 !s2_fwd_frm_d_chan_or_mshr && 826 !s2_full_fwd 827 828 val s2_rar_nack = io.ldu_io.lsq.ldld_nuke_query.req.valid && 829 !io.ldu_io.lsq.ldld_nuke_query.req.ready 830 831 val s2_raw_nack = io.ldu_io.lsq.stld_nuke_query.req.valid && 832 !io.ldu_io.lsq.stld_nuke_query.req.ready 833 834 // st-ld violation query 835 // NeedFastRecovery Valid when 836 // 1. Fast recovery query request Valid. 837 // 2. Load instruction is younger than requestors(store instructions). 838 // 3. Physical address match. 839 // 4. Data contains. 840 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 841 io.ldu_io.stld_nuke_query(w).valid && // query valid 842 isAfter(s2_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 843 // TODO: Fix me when vector instruction 844 (s2_in.paddr(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 845 (s2_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 846 })).asUInt.orR && s2_ld_flow || s2_in.rep_info.nuke 847 848 val s2_cache_handled = io.dcache.resp.bits.handled 849 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 850 io.dcache.resp.bits.tag_error 851 852 val s2_troublem = !s2_exception && 853 !s2_mmio && 854 !s2_prf && 855 !s2_in.lateKill 856 857 io.dcache.resp.ready := true.B 858 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_mmio || s2_prf || s2_in.lateKill) && s2_ld_flow 859 assert(!(s2_valid && (s2_dcache_should_resp && !io.dcache.resp.valid)), "DCache response got lost") 860 861 // fast replay require 862 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 863 val s2_nuke_fast_rep = !s2_mq_nack && 864 !s2_dcache_miss && 865 !s2_bank_conflict && 866 !s2_wpu_pred_fail && 867 !s2_rar_nack && 868 !s2_raw_nack && 869 s2_nuke 870 871 val s2_fast_rep = !s2_mem_amb && 872 !s2_tlb_miss && 873 !s2_fwd_fail && 874 (s2_dcache_fast_rep || s2_nuke_fast_rep) && 875 s2_troublem 876 877 // need allocate new entry 878 val s2_can_query = !s2_mem_amb && 879 !s2_tlb_miss && 880 !s2_fwd_fail && 881 !s2_dcache_fast_rep && 882 s2_troublem 883 884 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 885 886 // ld-ld violation require 887 io.ldu_io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 888 io.ldu_io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 889 io.ldu_io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 890 io.ldu_io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 891 io.ldu_io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 892 893 // st-ld violation require 894 io.ldu_io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 895 io.ldu_io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 896 io.ldu_io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 897 io.ldu_io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 898 io.ldu_io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 899 900 // merge forward result 901 // lsq has higher priority than sbuffer 902 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 903 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 904 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.ldu_io.lsq.forward.dataInvalid 905 // generate XLEN/8 Muxs 906 for (i <- 0 until VLEN / 8) { 907 s2_fwd_mask(i) := io.ldu_io.lsq.forward.forwardMask(i) || io.ldu_io.sbuffer.forwardMask(i) 908 s2_fwd_data(i) := Mux(io.ldu_io.lsq.forward.forwardMask(i), io.ldu_io.lsq.forward.forwardData(i), io.ldu_io.sbuffer.forwardData(i)) 909 } 910 911 XSDebug(s2_fire && s2_ld_flow, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 912 s2_in.uop.pc, 913 io.ldu_io.lsq.forward.forwardData.asUInt, io.ldu_io.lsq.forward.forwardMask.asUInt, 914 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 915 ) 916 917 // 918 s2_out := s2_in 919 s2_out.data := 0.U // data will be generated in load s3 920 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception && s2_ld_flow 921 s2_out.mmio := s2_mmio 922 s2_out.atomic := s2_pmp.atomic && !s2_ld_flow 923 s2_out.uop.flushPipe := false.B 924 s2_out.uop.exceptionVec := s2_exception_vec 925 s2_out.forwardMask := s2_fwd_mask 926 s2_out.forwardData := s2_fwd_data 927 s2_out.handledByMSHR := s2_cache_handled 928 s2_out.miss := s2_dcache_miss && s2_troublem 929 930 // Generate replay signal caused by: 931 // * st-ld violation check 932 // * tlb miss 933 // * dcache replay 934 // * forward data invalid 935 // * dcache miss 936 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 937 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 938 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 939 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 940 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 941 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 942 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 943 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 944 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 945 s2_out.rep_info.nuke := s2_nuke && s2_troublem 946 s2_out.rep_info.full_fwd := s2_data_fwded 947 s2_out.rep_info.data_inv_sq_idx := io.ldu_io.lsq.forward.dataInvalidSqIdx 948 s2_out.rep_info.addr_inv_sq_idx := io.ldu_io.lsq.forward.addrInvalidSqIdx 949 s2_out.rep_info.rep_carry := io.dcache.resp.bits.replayCarry 950 s2_out.rep_info.mshr_id := io.dcache.resp.bits.mshr_id 951 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 952 s2_out.rep_info.debug := s2_in.uop.debugInfo 953 954 // if forward fail, replay this inst from fetch 955 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 956 // if ld-ld violation is detected, replay from this inst from fetch 957 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_mmio && !s2_is_prefetch && !s2_in.tlbMiss 958 // io.out.bits.uop.replayInst := false.B 959 960 // to be removed 961 val s2_ld_need_fb = !s2_in.isLoadReplay && // already feedbacked 962 io.ldu_io.lq_rep_full && // LoadQueueReplay is full 963 s2_out.rep_info.need_rep && // need replay 964 !s2_exception && // no exception is triggered 965 !s2_hw_prf // not hardware prefetch 966 val s2_st_need_fb = !s2_ld_flow 967 io.feedback_fast.valid := s2_valid && (s2_ld_need_fb || s2_st_need_fb) 968 io.feedback_fast.bits.hit := false.B 969 io.feedback_fast.bits.flushState := s2_in.ptwBack 970 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 971 io.feedback_fast.bits.sourceType := Mux(s2_ld_flow, RSFeedbackType.lrqFull, RSFeedbackType.tlbMiss) 972 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 973 974 io.stu_io.lsq_replenish := s2_out 975 io.stu_io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss 976 977 io.ldu_io.ldCancel.ld1Cancel.valid := s2_valid && ( 978 (s2_out.rep_info.need_rep && s2_out.isFirstIssue) || // exe fail and issued from IQ 979 s2_mmio // is mmio 980 ) && s2_ld_flow 981 io.ldu_io.ldCancel.ld1Cancel.bits := s2_out.deqPortIdx 982 983 // fast wakeup 984 io.ldu_io.fast_uop.valid := RegNext( 985 !io.dcache.s1_disable_fast_wakeup && 986 s1_valid && 987 !s1_kill && 988 !io.tlb.resp.bits.miss && 989 !io.ldu_io.lsq.forward.dataInvalidFast 990 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_mmio && s2_ld_flow) 991 io.ldu_io.fast_uop.bits := RegNext(s1_out.uop) 992 993 // 994 io.ldu_io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, false.B, s1_fire) 995 996 // prefetch train 997 io.prefetch_train.valid := s2_valid && !s2_actually_mmio && !s2_in.tlbMiss 998 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 999 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss // TODO: use trace with bank conflict? 1000 io.prefetch_train.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 1001 io.prefetch_train.bits.meta_access := io.dcache.resp.bits.meta_access 1002 1003 io.prefetch_train_l1.valid := s2_valid && !s2_actually_mmio 1004 io.prefetch_train_l1.bits.fromLsPipelineBundle(s2_in) 1005 io.prefetch_train_l1.bits.miss := io.dcache.resp.bits.miss 1006 io.prefetch_train_l1.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 1007 io.prefetch_train_l1.bits.meta_access := io.dcache.resp.bits.meta_access 1008 if (env.FPGAPlatform){ 1009 io.dcache.s0_pc := DontCare 1010 io.dcache.s1_pc := DontCare 1011 io.dcache.s2_pc := DontCare 1012 }else{ 1013 io.dcache.s0_pc := s0_out.uop.pc 1014 io.dcache.s1_pc := s1_out.uop.pc 1015 io.dcache.s2_pc := s2_out.uop.pc 1016 } 1017 io.dcache.s2_kill := s2_pmp.ld || s2_pmp.st || s2_actually_mmio || s2_kill || !s2_ld_flow 1018 1019 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready && s1_ld_flow 1020 val s2_ld_valid_dup = RegInit(0.U(6.W)) 1021 s2_ld_valid_dup := 0x0.U(6.W) 1022 when (s1_ld_left_fire && !s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x3f.U(6.W) } 1023 when (s1_kill || s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x0.U(6.W) } 1024 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch))) 1025 1026 // Pipeline 1027 // -------------------------------------------------------------------------------- 1028 // stage 3 1029 // -------------------------------------------------------------------------------- 1030 // writeback and update load queue 1031 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 1032 val s3_in = RegEnable(s2_out, s2_fire) 1033 val s3_out = Wire(Valid(new MemExuOutput)) 1034 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, false.B, s2_fire) 1035 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 1036 val s3_fast_rep = Wire(Bool()) 1037 val s3_ld_flow = RegNext(s2_ld_flow) 1038 val s3_troublem = RegNext(s2_troublem) 1039 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 1040 s3_ready := !s3_valid || s3_kill || sx_can_go 1041 1042 // forwrad last beat 1043 val (s3_fwd_frm_d_chan, s3_fwd_data_frm_d_chan) = io.ldu_io.tl_d_channel.forward(s2_valid && s2_out.forward_tlDchannel, s2_out.mshrid, s2_out.paddr) 1044 val s3_fwd_data_valid = RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1045 val s3_fwd_frm_d_chan_valid = (s3_fwd_frm_d_chan && s3_fwd_data_valid) && s3_ld_flow 1046 1047 1048 // s3 load fast replay 1049 io.ldu_io.fast_rep_out.valid := s3_valid && 1050 s3_fast_rep && 1051 !s3_in.uop.robIdx.needFlush(io.redirect) && 1052 s3_ld_flow 1053 io.ldu_io.fast_rep_out.bits := s3_in 1054 1055 io.ldu_io.lsq.ldin.valid := s3_valid && 1056 (!s3_fast_rep || !io.ldu_io.fast_rep_out.ready) && 1057 !s3_in.feedbacked && 1058 !s3_in.lateKill && 1059 s3_ld_flow 1060 io.ldu_io.lsq.ldin.bits := s3_in 1061 io.ldu_io.lsq.ldin.bits.miss := s3_in.miss && !s3_fwd_frm_d_chan_valid 1062 1063 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1064 io.ldu_io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1065 io.ldu_io.lsq.ldin.bits.replacementUpdated := io.dcache.resp.bits.replacementUpdated 1066 io.ldu_io.lsq.ldin.bits.missDbUpdated := RegNext(s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated) 1067 1068 val s3_dly_ld_err = 1069 if (EnableAccurateLoadError) { 1070 (s3_in.lateKill || io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1071 } else { 1072 WireInit(false.B) 1073 } 1074 io.ldu_io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1075 io.ldu_io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1076 io.ldu_io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1077 1078 val s3_vp_match_fail = RegNext(io.ldu_io.lsq.forward.matchInvalid || io.ldu_io.sbuffer.matchInvalid) && s3_troublem 1079 val s3_ldld_rep_inst = 1080 io.ldu_io.lsq.ldld_nuke_query.resp.valid && 1081 io.ldu_io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1082 RegNext(io.csrCtrl.ldld_vio_check_enable) 1083 1084 val s3_rep_info = WireInit(s3_in.rep_info) 1085 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && !s3_fwd_frm_d_chan_valid && s3_troublem 1086 val s3_rep_frm_fetch = s3_vp_match_fail || s3_ldld_rep_inst 1087 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1088 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1089 !s3_in.uop.exceptionVec(loadAddrMisaligned) && 1090 s3_troublem 1091 1092 val s3_ld_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR && s3_ld_flow 1093 val s3_st_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, StaCfg).asUInt.orR && !s3_ld_flow 1094 val s3_exception = s3_ld_exception || s3_st_exception 1095 when ((s3_ld_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1096 io.ldu_io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1097 } .otherwise { 1098 io.ldu_io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1099 } 1100 1101 // Int flow, if hit, will be writebacked at s3 1102 s3_out.valid := s3_valid && 1103 (!s3_ld_flow || !io.ldu_io.lsq.ldin.bits.rep_info.need_rep && !s3_in.mmio) 1104 s3_out.bits.uop := s3_in.uop 1105 s3_out.bits.uop.exceptionVec(loadAccessFault) := (s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault)) && s3_ld_flow 1106 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1107 s3_out.bits.data := s3_in.data 1108 s3_out.bits.debug.isMMIO := s3_in.mmio 1109 s3_out.bits.debug.isPerfCnt := false.B 1110 s3_out.bits.debug.paddr := s3_in.paddr 1111 s3_out.bits.debug.vaddr := s3_in.vaddr 1112 1113 when (s3_force_rep) { 1114 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1115 } 1116 1117 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1118 io.ldu_io.lsq.ldin.bits.uop := s3_out.bits.uop 1119 1120 val s3_revoke = s3_exception || io.ldu_io.lsq.ldin.bits.rep_info.need_rep 1121 io.ldu_io.lsq.ldld_nuke_query.revoke := s3_revoke 1122 io.ldu_io.lsq.stld_nuke_query.revoke := s3_revoke 1123 1124 // feedback slow 1125 s3_fast_rep := RegNext(s2_fast_rep) && 1126 !s3_in.feedbacked && 1127 !s3_in.lateKill && 1128 !s3_rep_frm_fetch && 1129 !s3_exception 1130 1131 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.ldu_io.fast_rep_out.ready) && !s3_in.feedbacked 1132 1133 // 1134 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting && s3_ld_flow 1135 io.feedback_slow.bits.hit := !io.ldu_io.lsq.ldin.bits.rep_info.need_rep || io.ldu_io.lsq.ldin.ready 1136 io.feedback_slow.bits.flushState := s3_in.ptwBack 1137 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1138 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1139 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1140 1141 io.ldu_io.ldCancel.ld2Cancel.valid := s3_valid && ( 1142 (io.ldu_io.lsq.ldin.bits.rep_info.need_rep && s3_in.isFirstIssue) || 1143 s3_in.mmio 1144 ) && s3_ld_flow 1145 io.ldu_io.ldCancel.ld2Cancel.bits := s3_in.deqPortIdx 1146 1147 // data from dcache hit 1148 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1149 s3_ld_raw_data_frm_cache.respDcacheData := io.dcache.resp.bits.data_delayed 1150 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1151 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1152 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1153 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1154 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, false.B, s2_valid) || s3_fwd_frm_d_chan_valid 1155 s3_ld_raw_data_frm_cache.forwardData_D := Mux(s3_fwd_frm_d_chan_valid, s3_fwd_data_frm_d_chan, RegEnable(s2_fwd_data_frm_d_chan, s2_valid)) 1156 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, false.B, s2_valid) 1157 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1158 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1159 1160 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1161 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1162 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1163 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1164 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1165 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1166 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1167 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1168 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1169 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1170 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1171 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1172 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1173 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1174 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1175 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1176 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1177 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1178 )) 1179 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1180 1181 // FIXME: add 1 cycle delay ? 1182 io.ldout.bits := s3_out.bits 1183 io.ldout.bits.data := s3_ld_data_frm_cache 1184 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) && s3_ld_flow 1185 1186 // for uncache 1187 io.ldu_io.lsq.uncache.ready := true.B 1188 1189 // fast load to load forward 1190 io.ldu_io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill && s3_ld_flow 1191 io.ldu_io.l2l_fwd_out.data := s3_ld_data_frm_cache 1192 io.ldu_io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1193 1194 // hybrid unit writeback to rob 1195 // delay params 1196 val SelectGroupSize = RollbackGroupSize 1197 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 1198 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 1199 val TotalDelayCycles = TotalSelectCycles - 2 1200 1201 // writeback 1202 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 1203 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 1204 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 1205 1206 sx_can_go := sx_ready.head 1207 for (i <- 0 until TotalDelayCycles + 1) { 1208 if (i == 0) { 1209 sx_valid(i) := s3_valid && !s3_ld_flow 1210 sx_in(i) := s3_out.bits 1211 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 1212 } else { 1213 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 1214 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1215 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 1216 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 1217 1218 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1219 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 1220 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), sx_valid_can_go) 1221 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 1222 } 1223 } 1224 1225 val sx_last_valid = sx_valid.takeRight(1).head 1226 val sx_last_ready = sx_ready.takeRight(1).head 1227 val sx_last_in = sx_in.takeRight(1).head 1228 1229 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 1230 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) 1231 io.stout.bits := sx_last_in 1232 1233 // trigger 1234 val ld_trigger = FuType.isLoad(io.stout.bits.uop.fuType) 1235 val last_valid_data = RegEnable(io.stout.bits.data, io.stout.fire) 1236 val hit_ld_addr_trig_hit_vec = Wire(Vec(3, Bool())) 1237 val lq_ld_addr_trig_hit_vec = RegNext(io.ldu_io.lsq.trigger.lqLoadAddrTriggerHitVec) 1238 (0 until 3).map{i => { 1239 val tdata2 = RegNext(RegNext(io.ldu_io.trigger(i).tdata2)) 1240 val matchType = RegNext(RegNext(io.ldu_io.trigger(i).matchType)) 1241 val tEnable = RegNext(RegNext(io.ldu_io.trigger(i).tEnable)) 1242 1243 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s3_in.vaddr), tdata2, matchType, tEnable) 1244 io.ldu_io.trigger(i).addrHit := Mux(io.stout.valid && ld_trigger, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1245 io.ldu_io.trigger(i).lastDataHit := TriggerCmp(last_valid_data, tdata2, matchType, tEnable) 1246 }} 1247 io.ldu_io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1248 1249 // FIXME: please move this part to LoadQueueReplay 1250 io.ldu_io.debug_ls := DontCare 1251 io.stu_io.debug_ls := DontCare 1252 io.stu_io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch && !s1_ld_flow 1253 io.stu_io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 1254 1255 // Topdown 1256 io.ldu_io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1257 io.ldu_io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1258 io.ldu_io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1259 io.ldu_io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1260 io.ldu_io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1261 io.ldu_io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1262 io.ldu_io.lsTopdownInfo.s2.first_real_miss := io.dcache.resp.bits.real_miss 1263 io.ldu_io.lsTopdownInfo.s2.cache_miss_en := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated 1264 1265 // perf cnt 1266 XSPerfAccumulate("s0_in_valid", io.lsin.valid) 1267 XSPerfAccumulate("s0_in_block", io.lsin.valid && !io.lsin.fire) 1268 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1269 XSPerfAccumulate("s0_lsq_fire_first_issue", io.ldu_io.replay.fire) 1270 XSPerfAccumulate("s0_ldu_fire_first_issue", io.lsin.fire && s0_isFirstIssue) 1271 XSPerfAccumulate("s0_fast_replay_issue", io.ldu_io.fast_rep_in.fire) 1272 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1273 XSPerfAccumulate("s0_stall_dcache", s0_valid && !io.dcache.req.ready) 1274 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12)) 1275 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12)) 1276 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1277 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1278 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1279 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1280 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1281 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.ldu_io.prefetch_req.valid && !s0_hw_prf_select) 1282 XSPerfAccumulate("s0_hardware_prefetch_total", io.ldu_io.prefetch_req.valid) 1283 1284 XSPerfAccumulate("s1_in_valid", s1_valid) 1285 XSPerfAccumulate("s1_in_fire", s1_fire) 1286 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1287 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1288 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1289 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1290 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1291 1292 XSPerfAccumulate("s2_in_valid", s2_valid) 1293 XSPerfAccumulate("s2_in_fire", s2_fire) 1294 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1295 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.dcache.resp.bits.miss) 1296 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1297 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1298 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1299 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1300 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1301 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1302 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1303 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1304 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1305 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.dcache.resp.bits.miss) // prefetch req miss in l1 1306 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.dcache.resp.bits.miss) // prefetch req hit in l1 1307 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.dcache.resp.bits.miss && !s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1308 XSPerfAccumulate("s2_forward_req", s2_fire && s2_in.forward_tlDchannel) 1309 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fire && s2_fwd_frm_d_chan && s2_fwd_data_valid) 1310 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fire && s2_fwd_frm_mshr && s2_fwd_data_valid) 1311 1312 XSPerfAccumulate("s3_fwd_frm_d_chan", s3_valid && s3_fwd_frm_d_chan_valid) 1313 1314 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1315 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1316 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1317 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1318 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1319 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1320 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1321 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1322 1323 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1324 // hardware performance counter 1325 val perfEvents = Seq( 1326 ("load_s0_in_fire ", s0_fire ), 1327 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1328 ("stall_dcache ", s0_valid && s0_can_go && !io.dcache.req.ready ), 1329 ("load_s1_in_fire ", s0_fire ), 1330 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1331 ("load_s2_in_fire ", s1_fire ), 1332 ("load_s2_dcache_miss ", s2_fire && io.dcache.resp.bits.miss ), 1333 ) 1334 generatePerfEvent() 1335}