1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.fu.NewCSR._ 31import xiangshan.backend.rob.RobPtr 32import xiangshan.backend.fu._ 33import xiangshan.backend.fu.util.SdtrigExt 34import xiangshan.cache._ 35import xiangshan.cache.wpu.ReplayCarry 36import xiangshan.cache.mmu.{TlbCmd, TlbHintReq, TlbReq, TlbRequestIO, TlbResp} 37import xiangshan.mem.mdp._ 38 39class HybridUnit(implicit p: Parameters) extends XSModule 40 with HasLoadHelper 41 with HasPerfEvents 42 with HasDCacheParameters 43 with HasCircularQueuePtrHelper 44 with HasVLSUParameters 45 with SdtrigExt 46{ 47 val io = IO(new Bundle() { 48 // control 49 val redirect = Flipped(ValidIO(new Redirect)) 50 val csrCtrl = Flipped(new CustomCSRCtrlIO) 51 52 // flow in 53 val lsin = Flipped(Decoupled(new MemExuInput)) 54 55 // flow out 56 val ldout = DecoupledIO(new MemExuOutput) 57 val stout = DecoupledIO(new MemExuOutput) 58 59 val ldu_io = new Bundle() { 60 // dcache 61 val dcache = new DCacheLoadIO 62 63 // data path 64 val sbuffer = new LoadForwardQueryIO 65 val ubuffer = new LoadForwardQueryIO 66 val vec_forward = new LoadForwardQueryIO 67 val lsq = new LoadToLsqIO 68 val tl_d_channel = Input(new DcacheToLduForwardIO) 69 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 70 val tlb_hint = Flipped(new TlbHintReq) 71 val l2_hint = Input(Valid(new L2ToL1Hint)) 72 73 // fast wakeup 74 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 75 76 // trigger 77 val trigger = Vec(TriggerNum, new LoadUnitTriggerIO) 78 79 // load to load fast path 80 val l2l_fwd_in = Input(new LoadToLoadIO) 81 val l2l_fwd_out = Output(new LoadToLoadIO) 82 83 val ld_fast_match = Input(Bool()) 84 val ld_fast_fuOpType = Input(UInt()) 85 val ld_fast_imm = Input(UInt(12.W)) 86 87 // hardware prefetch to l1 cache req 88 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) 89 90 // iq cancel 91 val ldCancel = Output(new LoadCancelIO()) // use to cancel the uops waked by this load, and cancel load 92 93 // iq wakeup, use to wakeup consumer uop at load s2 94 val wakeup = ValidIO(new DynInst) 95 96 // load ecc error 97 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 98 99 // schedule error query 100 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 101 102 // queue-based replay 103 val replay = Flipped(Decoupled(new LsPipelineBundle)) 104 val lq_rep_full = Input(Bool()) 105 106 // misc 107 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 108 109 // Load fast replay path 110 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 111 val fast_rep_out = Decoupled(new LqWriteBundle) 112 113 // Load RAR rollback 114 val rollback = Valid(new Redirect) 115 116 // perf 117 val debug_ls = Output(new DebugLsInfoBundle) 118 val lsTopdownInfo = Output(new LsTopdownInfo) 119 } 120 121 val stu_io = new Bundle() { 122 val dcache = new DCacheStoreIO 123 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 124 val issue = Valid(new MemExuInput) 125 val lsq = ValidIO(new LsPipelineBundle) 126 val lsq_replenish = Output(new LsPipelineBundle()) 127 val stld_nuke_query = Valid(new StoreNukeQueryIO) 128 val st_mask_out = Valid(new StoreMaskBundle) 129 val debug_ls = Output(new DebugLsInfoBundle) 130 } 131 132 val vec_stu_io = new Bundle() { 133 val in = Flipped(DecoupledIO(new VecPipeBundle())) 134 val isFirstIssue = Input(Bool()) 135 val lsq = ValidIO(new LsPipelineBundle()) 136 val feedbackSlow = ValidIO(new VSFQFeedback) 137 } 138 139 // speculative for gated control 140 val s0_prefetch_spec = Output(Bool()) 141 val s1_prefetch_spec = Output(Bool()) 142 // prefetch 143 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to sms 144 val prefetch_train_l1 = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to stream & stride 145 val canAcceptLowConfPrefetch = Output(Bool()) 146 val canAcceptHighConfPrefetch = Output(Bool()) 147 val correctMissTrain = Input(Bool()) 148 149 // data path 150 val tlb = new TlbRequestIO(2) 151 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 152 153 // rs feedback 154 val feedback_fast = ValidIO(new RSFeedback) // stage 2 155 val feedback_slow = ValidIO(new RSFeedback) // stage 3 156 157 // for store trigger 158 val fromCsrTrigger = Input(new CsrTriggerBundle) 159 }) 160 161 val StorePrefetchL1Enabled = EnableStorePrefetchAtCommit || EnableStorePrefetchAtIssue || EnableStorePrefetchSPB 162 val s1_ready, s2_ready, s3_ready, sx_can_go = WireInit(false.B) 163 164 // Pipeline 165 // -------------------------------------------------------------------------------- 166 // stage 0 167 // -------------------------------------------------------------------------------- 168 // generate addr, use addr to query DCache and DTLB 169 val s0_valid = Wire(Bool()) 170 val s0_dcache_ready = Wire(Bool()) 171 val s0_kill = Wire(Bool()) 172 val s0_vaddr = Wire(UInt(VAddrBits.W)) 173 val s0_mask = Wire(UInt((VLEN/8).W)) 174 val s0_uop = Wire(new DynInst) 175 val s0_has_rob_entry = Wire(Bool()) 176 val s0_mshrid = Wire(UInt()) 177 val s0_try_l2l = Wire(Bool()) 178 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 179 val s0_isFirstIssue = Wire(Bool()) 180 val s0_fast_rep = Wire(Bool()) 181 val s0_ld_rep = Wire(Bool()) 182 val s0_l2l_fwd = Wire(Bool()) 183 val s0_sched_idx = Wire(UInt()) 184 val s0_can_go = s1_ready 185 val s0_fire = s0_valid && s0_dcache_ready && s0_can_go 186 val s0_out = Wire(new LqWriteBundle) 187 // vector 188 val s0_isvec = WireInit(false.B) 189 val s0_vecActive = WireInit(true.B) 190 // val s0_flowPtr = WireInit(0.U.asTypeOf(new VsFlowPtr)) 191 val s0_isLastElem = WireInit(false.B) 192 193 // load flow select/gen 194 // src0: super load replayed by LSQ (cache miss replay) (io.ldu_io.replay) 195 // src1: fast load replay (io.ldu_io.fast_rep_in) 196 // src2: load replayed by LSQ (io.ldu_io.replay) 197 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 198 // src4: int read / software prefetch first issue from RS (io.in) 199 // src5: vec read first issue from RS (TODO) 200 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 201 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 202 // priority: high to low 203 val s0_ld_flow = FuType.isLoad(s0_uop.fuType) || FuType.isVLoad(s0_uop.fuType) 204 val s0_rep_stall = io.lsin.valid && isAfter(io.ldu_io.replay.bits.uop.robIdx, io.lsin.bits.uop.robIdx) 205 private val SRC_NUM = 8 206 private val Seq( 207 super_rep_idx, fast_rep_idx, lsq_rep_idx, high_pf_idx, 208 int_iss_idx, vec_iss_idx, l2l_fwd_idx, low_pf_idx 209 ) = (0 until SRC_NUM).toSeq 210 // load flow source valid 211 val s0_src_valid_vec = WireInit(VecInit(Seq( 212 io.ldu_io.replay.valid && io.ldu_io.replay.bits.forward_tlDchannel, 213 io.ldu_io.fast_rep_in.valid, 214 io.ldu_io.replay.valid && !io.ldu_io.replay.bits.forward_tlDchannel && !s0_rep_stall, 215 io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence > 0.U, 216 io.lsin.valid, // int flow first issue or software prefetch 217 io.vec_stu_io.in.valid, 218 io.ldu_io.l2l_fwd_in.valid && io.ldu_io.ld_fast_match, 219 io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence === 0.U, 220 ))) 221 // load flow source ready 222 val s0_src_ready_vec = Wire(Vec(SRC_NUM, Bool())) 223 s0_src_ready_vec(0) := true.B 224 for(i <- 1 until SRC_NUM){ 225 s0_src_ready_vec(i) := !s0_src_valid_vec.take(i).reduce(_ || _) 226 } 227 // load flow source select (OH) 228 val s0_src_select_vec = WireInit(VecInit((0 until SRC_NUM).map{i => s0_src_valid_vec(i) && s0_src_ready_vec(i)})) 229 val s0_hw_prf_select = s0_src_select_vec(high_pf_idx) || s0_src_select_vec(low_pf_idx) 230 231 if (backendParams.debugEn){ 232 dontTouch(s0_src_valid_vec) 233 dontTouch(s0_src_ready_vec) 234 dontTouch(s0_src_select_vec) 235 } 236 237 s0_valid := s0_src_valid_vec.reduce(_ || _) && !s0_kill 238 239 // which is S0's out is ready and dcache is ready 240 val s0_try_ptr_chasing = s0_src_select_vec(l2l_fwd_idx) 241 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.ldu_io.dcache.req.ready 242 val s0_ptr_chasing_vaddr = io.ldu_io.l2l_fwd_in.data(5, 0) +& io.ldu_io.ld_fast_imm(5, 0) 243 val s0_ptr_chasing_canceled = WireInit(false.B) 244 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 245 246 // prefetch related ctrl signal 247 val s0_prf = Wire(Bool()) 248 val s0_prf_rd = Wire(Bool()) 249 val s0_prf_wr = Wire(Bool()) 250 val s0_hw_prf = s0_hw_prf_select 251 252 io.canAcceptLowConfPrefetch := s0_src_ready_vec(low_pf_idx) && io.ldu_io.dcache.req.ready 253 io.canAcceptHighConfPrefetch := s0_src_ready_vec(high_pf_idx) && io.ldu_io.dcache.req.ready 254 255 if (StorePrefetchL1Enabled) { 256 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, io.stu_io.dcache.req.ready) 257 } else { 258 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, true.B) 259 } 260 261 // query DTLB 262 io.tlb.req.valid := s0_valid && s0_dcache_ready 263 io.tlb.req.bits.cmd := Mux(s0_prf, 264 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 265 Mux(s0_ld_flow, TlbCmd.read, TlbCmd.write) 266 ) 267 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.paddr, s0_vaddr) 268 io.tlb.req.bits.size := Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1, 0), LSUOpType.size(s0_uop.fuOpType)) // may broken if use it in feature 269 io.tlb.req.bits.kill := s0_kill 270 io.tlb.req.bits.memidx.is_ld := s0_ld_flow 271 io.tlb.req.bits.memidx.is_st := !s0_ld_flow 272 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 273 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 274 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 275 io.tlb.req.bits.debug.pc := s0_uop.pc 276 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 277 278 // query DCache 279 // for load 280 io.ldu_io.dcache.req.valid := s0_valid && s0_dcache_ready && s0_ld_flow 281 io.ldu_io.dcache.req.bits.cmd := Mux(s0_prf_rd, MemoryOpConstants.M_PFR, 282 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD)) 283 io.ldu_io.dcache.req.bits.vaddr := s0_vaddr 284 io.ldu_io.dcache.req.bits.mask := s0_mask 285 io.ldu_io.dcache.req.bits.data := DontCare 286 io.ldu_io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 287 io.ldu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 288 io.ldu_io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 289 io.ldu_io.dcache.req.bits.replayCarry := s0_rep_carry 290 io.ldu_io.dcache.req.bits.id := DontCare // TODO: update cache meta 291 io.ldu_io.dcache.pf_source := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.pf_source.value, L1_HW_PREFETCH_NULL) 292 io.ldu_io.dcache.is128Req := is128Bit(io.vec_stu_io.in.bits.alignedType) && io.vec_stu_io.in.valid && s0_src_select_vec(vec_iss_idx) 293 294 // for store 295 io.stu_io.dcache.req.valid := s0_valid && s0_dcache_ready && !s0_ld_flow && !s0_prf 296 io.stu_io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 297 io.stu_io.dcache.req.bits.vaddr := s0_vaddr 298 io.stu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, STORE_SOURCE.U) 299 300 // load flow priority mux 301 def fromNullSource() = { 302 s0_vaddr := 0.U 303 s0_mask := 0.U 304 s0_uop := 0.U.asTypeOf(new DynInst) 305 s0_try_l2l := false.B 306 s0_has_rob_entry := false.B 307 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 308 s0_mshrid := 0.U 309 s0_isFirstIssue := false.B 310 s0_fast_rep := false.B 311 s0_ld_rep := false.B 312 s0_l2l_fwd := false.B 313 s0_prf := false.B 314 s0_prf_rd := false.B 315 s0_prf_wr := false.B 316 s0_sched_idx := 0.U 317 } 318 319 def fromFastReplaySource(src: LqWriteBundle) = { 320 s0_vaddr := src.vaddr 321 s0_mask := src.mask 322 s0_uop := src.uop 323 s0_try_l2l := false.B 324 s0_has_rob_entry := src.hasROBEntry 325 s0_rep_carry := src.rep_info.rep_carry 326 s0_mshrid := src.rep_info.mshr_id 327 s0_isFirstIssue := false.B 328 s0_fast_rep := true.B 329 s0_ld_rep := src.isLoadReplay 330 s0_l2l_fwd := false.B 331 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 332 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 333 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 334 s0_sched_idx := src.schedIndex 335 } 336 337 def fromNormalReplaySource(src: LsPipelineBundle) = { 338 s0_vaddr := src.vaddr 339 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 340 s0_uop := src.uop 341 s0_try_l2l := false.B 342 s0_has_rob_entry := true.B 343 s0_rep_carry := src.replayCarry 344 s0_mshrid := src.mshrid 345 s0_isFirstIssue := false.B 346 s0_fast_rep := false.B 347 s0_ld_rep := true.B 348 s0_l2l_fwd := false.B 349 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 350 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 351 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 352 s0_sched_idx := src.schedIndex 353 } 354 355 def fromPrefetchSource(src: L1PrefetchReq) = { 356 s0_vaddr := src.getVaddr() 357 s0_mask := 0.U 358 s0_uop := DontCare 359 s0_try_l2l := false.B 360 s0_has_rob_entry := false.B 361 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 362 s0_mshrid := 0.U 363 s0_isFirstIssue := false.B 364 s0_fast_rep := false.B 365 s0_ld_rep := false.B 366 s0_l2l_fwd := false.B 367 s0_prf := true.B 368 s0_prf_rd := !src.is_store 369 s0_prf_wr := src.is_store 370 s0_sched_idx := 0.U 371 } 372 373 def fromIntIssueSource(src: MemExuInput) = { 374 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 375 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 376 s0_uop := src.uop 377 s0_try_l2l := false.B 378 s0_has_rob_entry := true.B 379 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 380 s0_mshrid := 0.U 381 s0_isFirstIssue := true.B 382 s0_fast_rep := false.B 383 s0_ld_rep := false.B 384 s0_l2l_fwd := false.B 385 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 386 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 387 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 388 s0_sched_idx := 0.U 389 } 390 391 def fromVecIssueSource(src: VecPipeBundle) = { 392 // For now, vector port handles only vector store flows 393 s0_vaddr := src.vaddr 394 s0_mask := src.mask 395 s0_uop := src.uop 396 s0_try_l2l := false.B 397 s0_has_rob_entry := true.B 398 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 399 s0_mshrid := 0.U 400 // s0_isFirstIssue := src.isFirstIssue 401 s0_fast_rep := false.B 402 s0_ld_rep := false.B 403 s0_l2l_fwd := false.B 404 s0_prf := false.B 405 s0_prf_rd := false.B 406 s0_prf_wr := false.B 407 s0_sched_idx := 0.U 408 409 s0_isvec := true.B 410 s0_vecActive := io.vec_stu_io.in.bits.vecActive 411 // s0_flowPtr := io.vec_stu_io.in.bits.flowPtr 412 // s0_isLastElem := io.vec_stu_io.in.bits.isLastElem 413 } 414 415 def fromLoadToLoadSource(src: LoadToLoadIO) = { 416 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 417 s0_mask := genVWmask(s0_vaddr, io.ldu_io.ld_fast_fuOpType(1, 0)) 418 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 419 // Assume the pointer chasing is always ld. 420 s0_uop.fuOpType := io.ldu_io.ld_fast_fuOpType 421 s0_try_l2l := true.B 422 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 423 // because these signals will be updated in S1 424 s0_has_rob_entry := false.B 425 s0_mshrid := 0.U 426 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 427 s0_isFirstIssue := true.B 428 s0_fast_rep := false.B 429 s0_ld_rep := false.B 430 s0_l2l_fwd := true.B 431 s0_prf := false.B 432 s0_prf_rd := false.B 433 s0_prf_wr := false.B 434 s0_sched_idx := 0.U 435 } 436 437 // set default 438 s0_uop := DontCare 439 when (s0_src_select_vec(super_rep_idx)) { fromNormalReplaySource(io.ldu_io.replay.bits) } 440 .elsewhen (s0_src_select_vec(fast_rep_idx)) { fromFastReplaySource(io.ldu_io.fast_rep_in.bits) } 441 .elsewhen (s0_src_select_vec(lsq_rep_idx)) { fromNormalReplaySource(io.ldu_io.replay.bits) } 442 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.ldu_io.prefetch_req.bits) } 443 .elsewhen (s0_src_select_vec(int_iss_idx)) { fromIntIssueSource(io.lsin.bits) } 444 .elsewhen (s0_src_select_vec(vec_iss_idx)) { fromVecIssueSource(io.vec_stu_io.in.bits) } 445 .otherwise { 446 if (EnableLoadToLoadForward) { 447 fromLoadToLoadSource(io.ldu_io.l2l_fwd_in) 448 } else { 449 fromNullSource() 450 } 451 } 452 453 // address align check 454 val s0_addr_aligned = LookupTree(Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 455 "b00".U -> true.B, //b 456 "b01".U -> (s0_vaddr(0) === 0.U), //h 457 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 458 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 459 ))// may broken if use it in feature 460 461 // accept load flow if dcache ready (tlb is always ready) 462 // TODO: prefetch need writeback to loadQueueFlag 463 s0_out := DontCare 464 s0_out.vaddr := s0_vaddr 465 s0_out.mask := s0_mask 466 s0_out.uop := s0_uop 467 s0_out.isFirstIssue := s0_isFirstIssue 468 s0_out.hasROBEntry := s0_has_rob_entry 469 s0_out.isPrefetch := s0_prf 470 s0_out.isHWPrefetch := s0_hw_prf 471 s0_out.isFastReplay := s0_fast_rep 472 s0_out.isLoadReplay := s0_ld_rep 473 s0_out.isFastPath := s0_l2l_fwd 474 s0_out.mshrid := s0_mshrid 475 s0_out.isvec := s0_isvec 476 s0_out.isLastElem := s0_isLastElem 477 s0_out.vecActive := s0_vecActive 478 // s0_out.sflowPtr := s0_flowPtr 479 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned && s0_ld_flow 480 s0_out.uop.exceptionVec(storeAddrMisaligned) := !s0_addr_aligned && !s0_ld_flow 481 s0_out.forward_tlDchannel := s0_src_select_vec(super_rep_idx) 482 when(io.tlb.req.valid && s0_isFirstIssue) { 483 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 484 }.otherwise{ 485 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 486 } 487 s0_out.schedIndex := s0_sched_idx 488 489 // load fast replay 490 io.ldu_io.fast_rep_in.ready := (s0_can_go && io.ldu_io.dcache.req.ready && s0_src_ready_vec(fast_rep_idx)) 491 492 // load flow source ready 493 // cache missed load has highest priority 494 // always accept cache missed load flow from load replay queue 495 io.ldu_io.replay.ready := (s0_can_go && io.ldu_io.dcache.req.ready && (s0_src_ready_vec(lsq_rep_idx) && !s0_rep_stall || s0_src_select_vec(super_rep_idx))) 496 497 // accept load flow from rs when: 498 // 1) there is no lsq-replayed load 499 // 2) there is no fast replayed load 500 // 3) there is no high confidence prefetch request 501 io.lsin.ready := (s0_can_go && 502 Mux(FuType.isLoad(io.lsin.bits.uop.fuType), io.ldu_io.dcache.req.ready, 503 (if (StorePrefetchL1Enabled) io.stu_io.dcache.req.ready else true.B)) && s0_src_ready_vec(int_iss_idx)) 504 io.vec_stu_io.in.ready := s0_can_go && io.ldu_io.dcache.req.ready && s0_src_ready_vec(vec_iss_idx) 505 506 507 // for hw prefetch load flow feedback, to be added later 508 // io.prefetch_in.ready := s0_hw_prf_select 509 510 // dcache replacement extra info 511 // TODO: should prefetch load update replacement? 512 io.ldu_io.dcache.replacementUpdated := Mux(s0_src_select_vec(lsq_rep_idx) || s0_src_select_vec(super_rep_idx), io.ldu_io.replay.bits.replacementUpdated, false.B) 513 514 io.stu_io.prefetch_req.ready := s1_ready && io.stu_io.dcache.req.ready && !io.lsin.valid 515 516 // load debug 517 XSDebug(io.ldu_io.dcache.req.fire && s0_ld_flow, 518 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 519 ) 520 XSDebug(s0_valid && s0_ld_flow, 521 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lqIdx ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 522 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 523 524 // store debug 525 XSDebug(io.stu_io.dcache.req.fire && !s0_ld_flow, 526 p"[DCACHE STORE REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 527 ) 528 XSDebug(s0_valid && !s0_ld_flow, 529 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, sqIdx ${Hexadecimal(s0_out.uop.sqIdx.asUInt)}, " + 530 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 531 532 533 // Pipeline 534 // -------------------------------------------------------------------------------- 535 // stage 1 536 // -------------------------------------------------------------------------------- 537 // TLB resp (send paddr to dcache) 538 val s1_valid = RegInit(false.B) 539 val s1_in = Wire(new LqWriteBundle) 540 val s1_out = Wire(new LqWriteBundle) 541 val s1_kill = Wire(Bool()) 542 val s1_can_go = s2_ready 543 val s1_fire = s1_valid && !s1_kill && s1_can_go 544 val s1_ld_flow = RegNext(s0_ld_flow) 545 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 546 val s1_isLastElem = RegEnable(s0_out.isLastElem, false.B, s0_fire) 547 548 s1_ready := !s1_valid || s1_kill || s2_ready 549 when (s0_fire) { s1_valid := true.B } 550 .elsewhen (s1_fire) { s1_valid := false.B } 551 .elsewhen (s1_kill) { s1_valid := false.B } 552 s1_in := RegEnable(s0_out, s0_fire) 553 554 val s1_fast_rep_dly_err = RegNext(io.ldu_io.fast_rep_in.bits.delayedLoadError) 555 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 556 val s1_l2l_fwd_dly_err = RegNext(io.ldu_io.l2l_fwd_in.dly_ld_err) 557 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 558 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 559 val s1_vaddr_hi = Wire(UInt()) 560 val s1_vaddr_lo = Wire(UInt()) 561 val s1_vaddr = Wire(UInt()) 562 val s1_paddr_dup_lsu = Wire(UInt()) 563 val s1_paddr_dup_dcache = Wire(UInt()) 564 val s1_ld_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 565 val s1_st_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR // af & pf exception were modified below. 566 val s1_exception = (s1_ld_flow && s1_ld_exception) || (!s1_ld_flow && s1_st_exception) 567 val s1_tlb_miss = io.tlb.resp.bits.miss 568 val s1_prf = s1_in.isPrefetch 569 val s1_hw_prf = s1_in.isHWPrefetch 570 val s1_sw_prf = s1_prf && !s1_hw_prf 571 val s1_tlb_memidx = io.tlb.resp.bits.memidx 572 573 // mmio cbo decoder 574 val s1_mmio_cbo = (s1_in.uop.fuOpType === LSUOpType.cbo_clean || 575 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 576 s1_in.uop.fuOpType === LSUOpType.cbo_inval) && !s1_ld_flow && !s1_prf 577 val s1_mmio = s1_mmio_cbo 578 579 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 580 s1_vaddr_lo := s1_in.vaddr(5, 0) 581 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 582 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 583 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 584 585 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && 586 s1_tlb_memidx.idx === s1_in.uop.lqIdx.value && s1_ld_flow) { 587 // printf("Load idx = %d\n", s1_tlb_memidx.idx) 588 s1_out.uop.debugInfo.tlbRespTime := GTimer() 589 } .elsewhen(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && 590 s1_tlb_memidx.idx === s1_out.uop.sqIdx.value && !s1_ld_flow) { 591 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 592 s1_out.uop.debugInfo.tlbRespTime := GTimer() 593 } 594 595 io.tlb.req_kill := s1_kill 596 io.tlb.resp.ready := true.B 597 598 io.ldu_io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 599 io.ldu_io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 600 io.ldu_io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception 601 io.ldu_io.dcache.s1_kill_data_read := s1_kill || s1_tlb_miss 602 603 // store to load forwarding 604 io.ldu_io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 605 io.ldu_io.sbuffer.vaddr := s1_vaddr 606 io.ldu_io.sbuffer.paddr := s1_paddr_dup_lsu 607 io.ldu_io.sbuffer.uop := s1_in.uop 608 io.ldu_io.sbuffer.sqIdx := s1_in.uop.sqIdx 609 io.ldu_io.sbuffer.mask := s1_in.mask 610 io.ldu_io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 611 612 io.ldu_io.ubuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 613 io.ldu_io.ubuffer.vaddr := s1_vaddr 614 io.ldu_io.ubuffer.paddr := s1_paddr_dup_lsu 615 io.ldu_io.ubuffer.uop := s1_in.uop 616 io.ldu_io.ubuffer.sqIdx := s1_in.uop.sqIdx 617 io.ldu_io.ubuffer.mask := s1_in.mask 618 io.ldu_io.ubuffer.pc := s1_in.uop.pc // FIXME: remove it 619 620 io.ldu_io.vec_forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 621 io.ldu_io.vec_forward.vaddr := s1_vaddr 622 io.ldu_io.vec_forward.paddr := s1_paddr_dup_lsu 623 io.ldu_io.vec_forward.uop := s1_in.uop 624 io.ldu_io.vec_forward.sqIdx := s1_in.uop.sqIdx 625 io.ldu_io.vec_forward.mask := s1_in.mask 626 io.ldu_io.vec_forward.pc := s1_in.uop.pc // FIXME: remove it 627 628 io.ldu_io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 629 io.ldu_io.lsq.forward.vaddr := s1_vaddr 630 io.ldu_io.lsq.forward.paddr := s1_paddr_dup_lsu 631 io.ldu_io.lsq.forward.uop := s1_in.uop 632 io.ldu_io.lsq.forward.sqIdx := s1_in.uop.sqIdx 633 io.ldu_io.lsq.forward.sqIdxMask := 0.U 634 io.ldu_io.lsq.forward.mask := s1_in.mask 635 io.ldu_io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 636 637 // st-ld violation query 638 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 639 io.ldu_io.stld_nuke_query(w).valid && // query valid 640 isAfter(s1_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 641 // TODO: Fix me when vector instruction 642 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 643 (s1_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 644 })).asUInt.orR && !s1_tlb_miss && s1_ld_flow 645 646 s1_out := s1_in 647 s1_out.vaddr := s1_vaddr 648 s1_out.paddr := s1_paddr_dup_lsu 649 s1_out.tlbMiss := s1_tlb_miss 650 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 651 s1_out.rep_info.debug := s1_in.uop.debugInfo 652 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 653 s1_out.lateKill := s1_late_kill 654 655 // store trigger 656 val storeTrigger = Module(new MemTrigger(MemType.STORE)) 657 storeTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 658 storeTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 659 storeTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 660 storeTrigger.io.fromCsrTrigger.debugMode := io.fromCsrTrigger.debugMode 661 storeTrigger.io.fromLoadStore.vaddr := s1_vaddr 662 storeTrigger.io.fromLoadStore.isVectorUnitStride := s1_in.isvec && s1_in.is128bit 663 storeTrigger.io.fromLoadStore.mask := s1_in.mask 664 665 when (s1_ld_flow) { 666 when (!s1_late_kill) { 667 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 668 // af & pf exception were modified 669 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 670 s1_out.uop.exceptionVec(loadGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.ld 671 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 672 } .otherwise { 673 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B 674 s1_out.uop.exceptionVec(loadAccessFault) := s1_late_kill 675 } 676 } .otherwise { 677 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 678 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st 679 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 680 s1_out.uop.trigger := storeTrigger.io.toLoadStore.triggerAction 681 s1_out.uop.exceptionVec(breakPoint) := TriggerAction.isExp(storeTrigger.io.toLoadStore.triggerAction) 682 } 683 684 // load trigger 685 val loadTrigger = Module(new MemTrigger(MemType.LOAD)) 686 loadTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 687 loadTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 688 loadTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 689 loadTrigger.io.fromCsrTrigger.debugMode := io.fromCsrTrigger.debugMode 690 loadTrigger.io.fromLoadStore.vaddr := s1_vaddr 691 loadTrigger.io.fromLoadStore.isVectorUnitStride := s1_in.isvec && s1_in.is128bit 692 loadTrigger.io.fromLoadStore.mask := s1_in.mask 693 694 when (s1_ld_flow) { 695 s1_out.uop.exceptionVec(breakPoint) := TriggerAction.isExp(loadTrigger.io.toLoadStore.triggerAction) 696 s1_out.uop.trigger := loadTrigger.io.toLoadStore.triggerAction 697 } 698 699 // pointer chasing 700 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 701 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 702 val s1_fu_op_type_not_ld = WireInit(false.B) 703 val s1_not_fast_match = WireInit(false.B) 704 val s1_addr_mismatch = WireInit(false.B) 705 val s1_addr_misaligned = WireInit(false.B) 706 val s1_ptr_chasing_canceled = WireInit(false.B) 707 val s1_cancel_ptr_chasing = WireInit(false.B) 708 709 s1_kill := s1_late_kill || 710 s1_cancel_ptr_chasing || 711 s1_in.uop.robIdx.needFlush(io.redirect) || 712 RegEnable(s0_kill, false.B, io.lsin.valid || io.ldu_io.replay.valid || io.ldu_io.l2l_fwd_in.valid || io.ldu_io.fast_rep_in.valid || io.vec_stu_io.in.valid) 713 714 if (EnableLoadToLoadForward) { 715 // Sometimes, we need to cancel the load-load forwarding. 716 // These can be put at S0 if timing is bad at S1. 717 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 718 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ldu_io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 719 // Case 1: the address is misaligned, kill s1 720 s1_addr_misaligned := LookupTree(s1_in.uop.fuOpType(1, 0), List( 721 "b00".U -> false.B, //b 722 "b01".U -> (s1_vaddr(0) =/= 0.U), //h 723 "b10".U -> (s1_vaddr(1, 0) =/= 0.U), //w 724 "b11".U -> (s1_vaddr(2, 0) =/= 0.U) //d 725 )) 726 // Case 2: this load-load uop is cancelled 727 s1_ptr_chasing_canceled := !io.lsin.valid || FuType.isStore(io.lsin.bits.uop.fuType) 728 729 when (s1_try_ptr_chasing) { 730 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled 731 732 s1_in.uop := io.lsin.bits.uop 733 s1_in.isFirstIssue := io.lsin.bits.isFirstIssue 734 s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) 735 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 736 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 737 738 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 739 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 740 s1_in.uop.debugInfo.tlbRespTime := GTimer() 741 } 742 when (!s1_cancel_ptr_chasing) { 743 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.ldu_io.replay.fire && !io.ldu_io.fast_rep_in.fire && !(s0_src_valid_vec(high_pf_idx) && io.canAcceptHighConfPrefetch) 744 when (s1_try_ptr_chasing) { 745 io.lsin.ready := true.B 746 } 747 } 748 } 749 750 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 751 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 752 // to enable load-load, sqIdxMask must be calculated based on lsin.uop 753 // If the timing here is not OK, load-load forwarding has to be disabled. 754 // Or we calculate sqIdxMask at RS?? 755 io.ldu_io.lsq.forward.sqIdxMask := s1_sqIdx_mask 756 if (EnableLoadToLoadForward) { 757 when (s1_try_ptr_chasing) { 758 io.ldu_io.lsq.forward.sqIdxMask := UIntToMask(io.lsin.bits.uop.sqIdx.value, StoreQueueSize) 759 } 760 } 761 762 io.ldu_io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel && s1_ld_flow 763 io.ldu_io.forward_mshr.mshrid := s1_out.mshrid 764 io.ldu_io.forward_mshr.paddr := s1_out.paddr 765 766 io.ldu_io.wakeup.valid := s0_fire && s0_ld_flow && (s0_src_select_vec(super_rep_idx) || s0_src_select_vec(fast_rep_idx) || s0_src_select_vec(lsq_rep_idx) || s0_src_select_vec(int_iss_idx)) 767 io.ldu_io.wakeup.bits := s0_uop 768 769 io.stu_io.dcache.s1_kill := s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect) 770 io.stu_io.dcache.s1_paddr := s1_paddr_dup_dcache 771 772 773 // load debug 774 XSDebug(s1_valid && s1_ld_flow, 775 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 776 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 777 778 // store debug 779 XSDebug(s1_valid && !s1_ld_flow, 780 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.sqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 781 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 782 783 // store out 784 io.stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && !s1_isvec 785 io.stu_io.lsq.bits := s1_out 786 io.stu_io.lsq.bits.miss := s1_tlb_miss 787 788 io.vec_stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && s1_isvec 789 io.vec_stu_io.lsq.bits := s1_out 790 io.vec_stu_io.lsq.bits.miss := s1_tlb_miss 791 io.vec_stu_io.lsq.bits.isLastElem := s1_isLastElem 792 793 io.stu_io.st_mask_out.valid := s1_valid && !s1_ld_flow && !s1_prf 794 io.stu_io.st_mask_out.bits.mask := s1_out.mask 795 io.stu_io.st_mask_out.bits.sqIdx := s1_out.uop.sqIdx 796 797 io.stu_io.issue.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf && !s1_isvec 798 io.stu_io.issue.bits := RegEnable(io.lsin.bits, io.lsin.fire) 799 800 // st-ld violation dectect request 801 io.stu_io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf 802 io.stu_io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 803 io.stu_io.stld_nuke_query.bits.paddr := s1_paddr_dup_lsu 804 io.stu_io.stld_nuke_query.bits.mask := s1_in.mask 805 806 // Pipeline 807 // -------------------------------------------------------------------------------- 808 // stage 2 809 // -------------------------------------------------------------------------------- 810 // s2: DCache resp 811 val s2_valid = RegInit(false.B) 812 val s2_in = Wire(new LqWriteBundle) 813 val s2_out = Wire(new LqWriteBundle) 814 val s2_kill = Wire(Bool()) 815 val s2_can_go = s3_ready 816 val s2_fire = s2_valid && !s2_kill && s2_can_go 817 val s2_isvec = RegEnable(s1_isvec, false.B, s1_fire) 818 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 819 val s2_paddr = RegEnable(s1_paddr_dup_lsu, s1_fire) 820 821 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 822 s2_ready := !s2_valid || s2_kill || s3_ready 823 when (s1_fire) { s2_valid := true.B } 824 .elsewhen (s2_fire) { s2_valid := false.B } 825 .elsewhen (s2_kill) { s2_valid := false.B } 826 s2_in := RegEnable(s1_out, s1_fire) 827 828 val s2_pmp = WireInit(io.pmp) 829 830 val s2_prf = s2_in.isPrefetch 831 val s2_hw_prf = s2_in.isHWPrefetch 832 val s2_ld_flow = RegEnable(s1_ld_flow, s1_fire) 833 834 // exception that may cause load addr to be invalid / illegal 835 // if such exception happen, that inst and its exception info 836 // will be force writebacked to rob 837 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 838 when (s2_ld_flow) { 839 when (!s2_in.lateKill) { 840 s2_exception_vec(loadAccessFault) := s2_vecActive && ( 841 s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld || 842 s2_fwd_frm_d_chan && s2_d_corrupt || 843 s2_fwd_frm_mshr && s2_mshr_corrupt 844 ) 845 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 846 when (s2_prf || s2_in.tlbMiss) { 847 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 848 } 849 } 850 } .otherwise { 851 s2_exception_vec(storeAccessFault) := s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st 852 when (s2_prf || s2_in.tlbMiss) { 853 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 854 } 855 } 856 val s2_ld_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR && s2_ld_flow 857 val s2_st_exception = ExceptionNO.selectByFu(s2_exception_vec, StaCfg).asUInt.orR && !s2_ld_flow 858 val s2_exception = s2_ld_exception || s2_st_exception 859 860 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan, s2_d_corrupt) = io.ldu_io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 861 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr, s2_mshr_corrupt) = io.ldu_io.forward_mshr.forward() 862 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 863 864 // writeback access fault caused by ecc error / bus error 865 // * ecc data error is slow to generate, so we will not use it until load stage 3 866 // * in load stage 3, an extra signal io.load_error will be used to 867 val s2_actually_mmio = s2_pmp.mmio 868 val s2_ld_mmio = !s2_prf && 869 s2_actually_mmio && 870 !s2_exception && 871 !s2_in.tlbMiss && 872 s2_ld_flow 873 val s2_st_mmio = !s2_prf && 874 (RegNext(s1_mmio) || s2_pmp.mmio) && 875 !s2_exception && 876 !s2_in.tlbMiss && 877 !s2_ld_flow 878 val s2_st_atomic = !s2_prf && 879 (RegNext(s1_mmio) || s2_pmp.atomic) && 880 !s2_exception && 881 !s2_in.tlbMiss && 882 !s2_ld_flow 883 val s2_full_fwd = Wire(Bool()) 884 val s2_mem_amb = s2_in.uop.storeSetHit && 885 io.ldu_io.lsq.forward.addrInvalid 886 887 val s2_tlb_miss = s2_in.tlbMiss 888 val s2_fwd_fail = io.ldu_io.lsq.forward.dataInvalid || io.ldu_io.vec_forward.dataInvalid 889 val s2_dcache_miss = io.ldu_io.dcache.resp.bits.miss && 890 !s2_fwd_frm_d_chan_or_mshr && 891 !s2_full_fwd 892 893 val s2_mq_nack = io.ldu_io.dcache.s2_mq_nack && 894 !s2_fwd_frm_d_chan_or_mshr && 895 !s2_full_fwd 896 897 val s2_bank_conflict = io.ldu_io.dcache.s2_bank_conflict && 898 !s2_fwd_frm_d_chan_or_mshr && 899 !s2_full_fwd 900 901 val s2_wpu_pred_fail = io.ldu_io.dcache.s2_wpu_pred_fail && 902 !s2_fwd_frm_d_chan_or_mshr && 903 !s2_full_fwd 904 905 val s2_rar_nack = io.ldu_io.lsq.ldld_nuke_query.req.valid && 906 !io.ldu_io.lsq.ldld_nuke_query.req.ready 907 908 val s2_raw_nack = io.ldu_io.lsq.stld_nuke_query.req.valid && 909 !io.ldu_io.lsq.stld_nuke_query.req.ready 910 911 // st-ld violation query 912 // NeedFastRecovery Valid when 913 // 1. Fast recovery query request Valid. 914 // 2. Load instruction is younger than requestors(store instructions). 915 // 3. Physical address match. 916 // 4. Data contains. 917 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 918 io.ldu_io.stld_nuke_query(w).valid && // query valid 919 isAfter(s2_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 920 // TODO: Fix me when vector instruction 921 (s2_in.paddr(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 922 (s2_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 923 })).asUInt.orR && s2_ld_flow || s2_in.rep_info.nuke 924 925 val s2_cache_handled = io.ldu_io.dcache.resp.bits.handled 926 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 927 io.ldu_io.dcache.resp.bits.tag_error 928 929 val s2_troublem = !s2_exception && 930 !s2_ld_mmio && 931 !s2_prf && 932 !s2_in.lateKill && 933 s2_ld_flow 934 935 io.ldu_io.dcache.resp.ready := true.B 936 io.stu_io.dcache.resp.ready := true.B 937 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_ld_mmio || s2_prf || s2_in.lateKill) && s2_ld_flow 938 assert(!(s2_valid && (s2_dcache_should_resp && !io.ldu_io.dcache.resp.valid)), "DCache response got lost") 939 940 // fast replay require 941 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 942 val s2_nuke_fast_rep = !s2_mq_nack && 943 !s2_dcache_miss && 944 !s2_bank_conflict && 945 !s2_wpu_pred_fail && 946 !s2_rar_nack && 947 !s2_raw_nack && 948 s2_nuke 949 950 val s2_fast_rep = !s2_mem_amb && 951 !s2_tlb_miss && 952 !s2_fwd_fail && 953 (s2_dcache_fast_rep || s2_nuke_fast_rep) && 954 s2_troublem 955 956 // need allocate new entry 957 val s2_can_query = !s2_mem_amb && 958 !s2_tlb_miss && 959 !s2_fwd_fail && 960 !s2_dcache_fast_rep && 961 s2_troublem 962 963 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 964 965 // ld-ld violation require 966 io.ldu_io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 967 io.ldu_io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 968 io.ldu_io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 969 io.ldu_io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 970 io.ldu_io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 971 972 // st-ld violation require 973 io.ldu_io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 974 io.ldu_io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 975 io.ldu_io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 976 io.ldu_io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 977 io.ldu_io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 978 979 // merge forward result 980 // lsq has higher priority than sbuffer 981 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 982 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 983 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.ldu_io.lsq.forward.dataInvalid && !io.ldu_io.vec_forward.dataInvalid 984 // generate XLEN/8 Muxs 985 for (i <- 0 until VLEN / 8) { 986 s2_fwd_mask(i) := io.ldu_io.lsq.forward.forwardMask(i) || io.ldu_io.sbuffer.forwardMask(i) || io.ldu_io.vec_forward.forwardMask(i) || io.ldu_io.ubuffer.forwardMask(i) 987 s2_fwd_data(i) := 988 Mux(io.ldu_io.lsq.forward.forwardMask(i), io.ldu_io.lsq.forward.forwardData(i), 989 Mux(io.ldu_io.vec_forward.forwardMask(i), io.ldu_io.vec_forward.forwardData(i), 990 Mux(io.ldu_io.ubuffer.forwardMask(i), io.ldu_io.ubuffer.forwardData(i), 991 io.ldu_io.sbuffer.forwardData(i)))) 992 } 993 994 XSDebug(s2_fire && s2_ld_flow, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 995 s2_in.uop.pc, 996 io.ldu_io.lsq.forward.forwardData.asUInt, io.ldu_io.lsq.forward.forwardMask.asUInt, 997 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 998 ) 999 1000 // 1001 s2_out := s2_in 1002 s2_out.data := 0.U // data will be generated in load s3 1003 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception && s2_ld_flow 1004 s2_out.mmio := s2_ld_mmio || s2_st_mmio 1005 s2_out.atomic := s2_st_atomic 1006 s2_out.uop.flushPipe := false.B 1007 s2_out.uop.exceptionVec := s2_exception_vec 1008 s2_out.forwardMask := s2_fwd_mask 1009 s2_out.forwardData := s2_fwd_data 1010 s2_out.handledByMSHR := s2_cache_handled 1011 s2_out.miss := s2_dcache_miss && s2_troublem 1012 s2_out.feedbacked := io.feedback_fast.valid && !io.feedback_fast.bits.hit 1013 1014 // Generate replay signal caused by: 1015 // * st-ld violation check 1016 // * tlb miss 1017 // * dcache replay 1018 // * forward data invalid 1019 // * dcache miss 1020 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 1021 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 1022 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 1023 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 1024 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 1025 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 1026 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 1027 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 1028 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 1029 s2_out.rep_info.nuke := s2_nuke && s2_troublem 1030 s2_out.rep_info.full_fwd := s2_data_fwded 1031 s2_out.rep_info.data_inv_sq_idx := Mux(io.ldu_io.vec_forward.dataInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.dataInvalidSqIdx) 1032 s2_out.rep_info.addr_inv_sq_idx := Mux(io.ldu_io.vec_forward.addrInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.addrInvalidSqIdx) 1033 s2_out.rep_info.rep_carry := io.ldu_io.dcache.resp.bits.replayCarry 1034 s2_out.rep_info.mshr_id := io.ldu_io.dcache.resp.bits.mshr_id 1035 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 1036 s2_out.rep_info.debug := s2_in.uop.debugInfo 1037 s2_out.rep_info.tlb_id := io.ldu_io.tlb_hint.id 1038 s2_out.rep_info.tlb_full := io.ldu_io.tlb_hint.full 1039 1040 // if forward fail, replay this inst from fetch 1041 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 1042 // if ld-ld violation is detected, replay from this inst from fetch 1043 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_ld_mmio && !s2_is_prefetch && !s2_in.tlbMiss 1044 // io.out.bits.uop.replayInst := false.B 1045 1046 // to be removed 1047 val s2_ld_need_fb = !s2_in.isLoadReplay && // already feedbacked 1048 io.ldu_io.lq_rep_full && // LoadQueueReplay is full 1049 s2_out.rep_info.need_rep && // need replay 1050 !s2_exception && // no exception is triggered 1051 !s2_hw_prf && // not hardware prefetch 1052 !s2_isvec 1053 val s2_st_need_fb = !s2_ld_flow && !s2_hw_prf && !s2_isvec 1054 io.feedback_fast.valid := s2_valid && (s2_ld_need_fb || s2_st_need_fb) 1055 io.feedback_fast.bits.hit := Mux(s2_ld_flow, false.B, !s2_tlb_miss) 1056 io.feedback_fast.bits.flushState := s2_in.ptwBack 1057 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 1058 io.feedback_fast.bits.sourceType := Mux(s2_ld_flow, RSFeedbackType.lrqFull, RSFeedbackType.tlbMiss) 1059 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 1060 1061 val s2_vec_feedback = Wire(Valid(new VSFQFeedback)) 1062 s2_vec_feedback.valid := s2_valid && !s2_ld_flow && !s2_hw_prf && s2_isvec 1063 // s2_vec_feedback.bits.flowPtr := s2_out.sflowPtr 1064 s2_vec_feedback.bits.hit := !s2_tlb_miss 1065 s2_vec_feedback.bits.sourceType := RSFeedbackType.tlbMiss 1066 s2_vec_feedback.bits.paddr := s2_paddr 1067 s2_vec_feedback.bits.mmio := s2_st_mmio 1068 s2_vec_feedback.bits.atomic := s2_st_mmio 1069 s2_vec_feedback.bits.exceptionVec := s2_exception_vec 1070 1071 io.stu_io.lsq_replenish := s2_out 1072 io.stu_io.lsq_replenish.miss := io.ldu_io.dcache.resp.fire && io.ldu_io.dcache.resp.bits.miss 1073 1074 io.ldu_io.ldCancel.ld1Cancel := false.B 1075 1076 // fast wakeup 1077 io.ldu_io.fast_uop.valid := RegNext( 1078 !io.ldu_io.dcache.s1_disable_fast_wakeup && 1079 s1_valid && 1080 !s1_kill && 1081 !io.tlb.resp.bits.miss && 1082 !io.ldu_io.lsq.forward.dataInvalidFast 1083 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_ld_mmio && s2_ld_flow) && !s2_isvec 1084 io.ldu_io.fast_uop.bits := RegNext(s1_out.uop) 1085 1086 // 1087 io.ldu_io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, false.B, s1_fire) 1088 1089 // prefetch train 1090 io.s0_prefetch_spec := s0_fire 1091 io.s1_prefetch_spec := s1_fire 1092 io.prefetch_train.valid := s2_valid && !s2_actually_mmio && !s2_in.tlbMiss 1093 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 1094 io.prefetch_train.bits.miss := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.miss, io.stu_io.dcache.resp.bits.miss) // TODO: use trace with bank conflict? 1095 io.prefetch_train.bits.meta_prefetch := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_prefetch, false.B) 1096 io.prefetch_train.bits.meta_access := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_access, false.B) 1097 1098 io.prefetch_train_l1.valid := s2_valid && !s2_actually_mmio && s2_ld_flow 1099 io.prefetch_train_l1.bits.fromLsPipelineBundle(s2_in) 1100 io.prefetch_train_l1.bits.miss := io.ldu_io.dcache.resp.bits.miss 1101 io.prefetch_train_l1.bits.meta_prefetch := io.ldu_io.dcache.resp.bits.meta_prefetch 1102 io.prefetch_train_l1.bits.meta_access := io.ldu_io.dcache.resp.bits.meta_access 1103 if (env.FPGAPlatform){ 1104 io.ldu_io.dcache.s0_pc := DontCare 1105 io.ldu_io.dcache.s1_pc := DontCare 1106 io.ldu_io.dcache.s2_pc := DontCare 1107 }else{ 1108 io.ldu_io.dcache.s0_pc := s0_out.uop.pc 1109 io.ldu_io.dcache.s1_pc := s1_out.uop.pc 1110 io.ldu_io.dcache.s2_pc := s2_out.uop.pc 1111 } 1112 io.ldu_io.dcache.s2_kill := s2_pmp.ld || s2_actually_mmio || s2_kill 1113 io.stu_io.dcache.s2_kill := s2_pmp.st || s2_actually_mmio || s2_kill 1114 io.stu_io.dcache.s2_pc := s2_out.uop.pc 1115 1116 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready && s1_ld_flow 1117 val s2_ld_valid_dup = RegInit(0.U(6.W)) 1118 s2_ld_valid_dup := 0x0.U(6.W) 1119 when (s1_ld_left_fire && !s1_out.isHWPrefetch && s1_ld_flow) { s2_ld_valid_dup := 0x3f.U(6.W) } 1120 when (s1_kill || s1_out.isHWPrefetch || !s1_ld_flow) { s2_ld_valid_dup := 0x0.U(6.W) } 1121 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch) || RegNext(!s1_ld_flow))) 1122 1123 // Pipeline 1124 // -------------------------------------------------------------------------------- 1125 // stage 3 1126 // -------------------------------------------------------------------------------- 1127 // writeback and update load queue 1128 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 1129 val s3_in = RegEnable(s2_out, s2_fire) 1130 val s3_out = Wire(Valid(new MemExuOutput)) 1131 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, false.B, s2_fire) 1132 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 1133 val s3_fast_rep = Wire(Bool()) 1134 val s3_ld_flow = RegNext(s2_ld_flow) 1135 val s3_troublem = RegNext(s2_troublem) 1136 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 1137 val s3_isvec = RegNext(s2_isvec) 1138 s3_ready := !s3_valid || s3_kill || sx_can_go 1139 1140 // s3 load fast replay 1141 io.ldu_io.fast_rep_out.valid := s3_valid && 1142 s3_fast_rep && 1143 !s3_in.uop.robIdx.needFlush(io.redirect) && 1144 s3_ld_flow && 1145 !s3_isvec 1146 io.ldu_io.fast_rep_out.bits := s3_in 1147 1148 io.ldu_io.lsq.ldin.valid := s3_valid && 1149 (!s3_fast_rep || !io.ldu_io.fast_rep_out.ready) && 1150 !s3_in.feedbacked && 1151 !s3_in.lateKill && 1152 s3_ld_flow 1153 io.ldu_io.lsq.ldin.bits := s3_in 1154 io.ldu_io.lsq.ldin.bits.miss := s3_in.miss 1155 1156 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1157 io.ldu_io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1158 io.ldu_io.lsq.ldin.bits.replacementUpdated := io.ldu_io.dcache.resp.bits.replacementUpdated 1159 io.ldu_io.lsq.ldin.bits.missDbUpdated := RegNext(s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated) 1160 1161 val s3_dly_ld_err = 1162 if (EnableAccurateLoadError) { 1163 (s3_in.lateKill || io.ldu_io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1164 } else { 1165 WireInit(false.B) 1166 } 1167 io.ldu_io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1168 io.ldu_io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1169 io.ldu_io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1170 1171 val s3_vp_match_fail = RegNext(io.ldu_io.lsq.forward.matchInvalid || io.ldu_io.sbuffer.matchInvalid || io.ldu_io.ubuffer.matchInvalid) && s3_troublem 1172 val s3_ldld_rep_inst = 1173 io.ldu_io.lsq.ldld_nuke_query.resp.valid && 1174 io.ldu_io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1175 RegNext(io.csrCtrl.ldld_vio_check_enable) 1176 1177 val s3_rep_info = WireInit(s3_in.rep_info) 1178 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && s3_troublem 1179 val s3_rep_frm_fetch = s3_vp_match_fail 1180 val s3_flushPipe = s3_ldld_rep_inst 1181 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1182 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1183 !s3_in.uop.exceptionVec(loadAddrMisaligned) && 1184 s3_troublem 1185 1186 val s3_ld_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR && s3_ld_flow 1187 val s3_st_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, StaCfg).asUInt.orR && !s3_ld_flow 1188 val s3_exception = s3_ld_exception || s3_st_exception 1189 when ((s3_ld_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1190 io.ldu_io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1191 } .otherwise { 1192 io.ldu_io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1193 } 1194 1195 // Int flow, if hit, will be writebacked at s3 1196 s3_out.valid := s3_valid && 1197 (!s3_ld_flow && !s3_in.feedbacked || !io.ldu_io.lsq.ldin.bits.rep_info.need_rep) && !s3_in.mmio 1198 s3_out.bits.uop := s3_in.uop 1199 s3_out.bits.uop.exceptionVec(loadAccessFault) := (s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault)) && s3_ld_flow 1200 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1201 s3_out.bits.data := s3_in.data 1202 s3_out.bits.debug.isMMIO := s3_in.mmio 1203 s3_out.bits.debug.isNC := s3_in.nc 1204 s3_out.bits.debug.isPerfCnt := false.B 1205 s3_out.bits.debug.paddr := s3_in.paddr 1206 s3_out.bits.debug.vaddr := s3_in.vaddr 1207 1208 when (s3_force_rep) { 1209 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1210 } 1211 1212 io.ldu_io.rollback.valid := s3_valid && (s3_rep_frm_fetch || s3_flushPipe) && !s3_exception && s3_ld_flow 1213 io.ldu_io.rollback.bits := DontCare 1214 io.ldu_io.rollback.bits.isRVC := s3_out.bits.uop.preDecodeInfo.isRVC 1215 io.ldu_io.rollback.bits.robIdx := s3_out.bits.uop.robIdx 1216 io.ldu_io.rollback.bits.ftqIdx := s3_out.bits.uop.ftqPtr 1217 io.ldu_io.rollback.bits.ftqOffset := s3_out.bits.uop.ftqOffset 1218 io.ldu_io.rollback.bits.level := Mux(s3_rep_frm_fetch, RedirectLevel.flush, RedirectLevel.flushAfter) 1219 io.ldu_io.rollback.bits.cfiUpdate.target := s3_out.bits.uop.pc 1220 io.ldu_io.rollback.bits.debug_runahead_checkpoint_id := s3_out.bits.uop.debugInfo.runahead_checkpoint_id 1221 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1222 io.ldu_io.lsq.ldin.bits.uop := s3_out.bits.uop 1223 1224 val s3_revoke = s3_exception || io.ldu_io.lsq.ldin.bits.rep_info.need_rep 1225 io.ldu_io.lsq.ldld_nuke_query.revoke := s3_revoke 1226 io.ldu_io.lsq.stld_nuke_query.revoke := s3_revoke 1227 1228 // feedback slow 1229 s3_fast_rep := RegNext(s2_fast_rep) && 1230 !s3_in.feedbacked && 1231 !s3_in.lateKill && 1232 !s3_rep_frm_fetch && 1233 !s3_exception 1234 1235 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.ldu_io.fast_rep_out.ready) && !s3_in.feedbacked 1236 1237 // 1238 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting && s3_ld_flow 1239 io.feedback_slow.bits.hit := !io.ldu_io.lsq.ldin.bits.rep_info.need_rep || io.ldu_io.lsq.ldin.ready 1240 io.feedback_slow.bits.flushState := s3_in.ptwBack 1241 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1242 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1243 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1244 1245 io.vec_stu_io.feedbackSlow.valid := RegNext(s2_vec_feedback.valid && !s2_out.uop.robIdx.needFlush(io.redirect)) 1246 io.vec_stu_io.feedbackSlow.bits := RegNext(s2_vec_feedback.bits) 1247 1248 io.ldu_io.ldCancel.ld2Cancel := s3_valid && s3_ld_flow && ( // is load 1249 io.ldu_io.lsq.ldin.bits.rep_info.need_rep || s3_in.mmio // exe fail or is mmio 1250 ) 1251 1252 // data from dcache hit 1253 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1254 s3_ld_raw_data_frm_cache.respDcacheData := io.ldu_io.dcache.resp.bits.data 1255 s3_ld_raw_data_frm_cache.forward_D := s2_fwd_frm_d_chan 1256 s3_ld_raw_data_frm_cache.forwardData_D := s2_fwd_data_frm_d_chan 1257 s3_ld_raw_data_frm_cache.forward_mshr := s2_fwd_frm_mshr 1258 s3_ld_raw_data_frm_cache.forwardData_mshr := s2_fwd_data_frm_mshr 1259 s3_ld_raw_data_frm_cache.forward_result_valid := s2_fwd_data_valid 1260 1261 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1262 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1263 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1264 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1265 1266 val s3_merged_data_frm_tlD = RegEnable(s3_ld_raw_data_frm_cache.mergeTLData(), s2_valid) 1267 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergeLsqFwdData(s3_merged_data_frm_tlD) 1268 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1269 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1270 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1271 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1272 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1273 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1274 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1275 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1276 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1277 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1278 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1279 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1280 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1281 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1282 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1283 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1284 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1285 )) 1286 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1287 1288 // FIXME: add 1 cycle delay ? 1289 io.ldout.bits := s3_out.bits 1290 io.ldout.bits.data := s3_ld_data_frm_cache 1291 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) && s3_ld_flow && !s3_isvec 1292 1293 // for uncache 1294 io.ldu_io.lsq.uncache.ready := true.B 1295 1296 // fast load to load forward 1297 if (EnableLoadToLoadForward) { 1298 io.ldu_io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill && s3_ld_flow 1299 io.ldu_io.l2l_fwd_out.data := s3_ld_data_frm_cache 1300 io.ldu_io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1301 } else { 1302 io.ldu_io.l2l_fwd_out.valid := false.B 1303 io.ldu_io.l2l_fwd_out.data := DontCare 1304 io.ldu_io.l2l_fwd_out.dly_ld_err := DontCare 1305 } 1306 1307 // hybrid unit writeback to rob 1308 // delay params 1309 val SelectGroupSize = RollbackGroupSize 1310 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 1311 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 1312 val TotalDelayCycles = TotalSelectCycles - 2 1313 1314 // writeback 1315 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 1316 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 1317 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 1318 1319 sx_can_go := sx_ready.head 1320 for (i <- 0 until TotalDelayCycles + 1) { 1321 if (i == 0) { 1322 sx_valid(i) := s3_valid && 1323 !s3_ld_flow && 1324 !s3_in.feedbacked && 1325 !s3_in.mmio 1326 sx_in(i) := s3_out.bits 1327 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 1328 } else { 1329 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 1330 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1331 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 1332 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 1333 1334 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1335 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 1336 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), sx_valid_can_go) 1337 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 1338 } 1339 } 1340 1341 val sx_last_valid = sx_valid.takeRight(1).head 1342 val sx_last_ready = sx_ready.takeRight(1).head 1343 val sx_last_in = sx_in.takeRight(1).head 1344 1345 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 1346 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) && FuType.isStore(sx_last_in.uop.fuType) 1347 io.stout.bits := sx_last_in 1348 1349 // FIXME: please move this part to LoadQueueReplay 1350 io.ldu_io.debug_ls := DontCare 1351 io.stu_io.debug_ls := DontCare 1352 io.stu_io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch && !s1_ld_flow 1353 io.stu_io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 1354 1355 // Topdown 1356 io.ldu_io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1357 io.ldu_io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1358 io.ldu_io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1359 io.ldu_io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1360 io.ldu_io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1361 io.ldu_io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1362 io.ldu_io.lsTopdownInfo.s2.first_real_miss := io.ldu_io.dcache.resp.bits.real_miss 1363 io.ldu_io.lsTopdownInfo.s2.cache_miss_en := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated 1364 1365 // perf cnt 1366 XSPerfAccumulate("s0_in_valid", io.lsin.valid) 1367 XSPerfAccumulate("s0_in_block", io.lsin.valid && !io.lsin.fire) 1368 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1369 XSPerfAccumulate("s0_lsq_fire_first_issue", io.ldu_io.replay.fire) 1370 XSPerfAccumulate("s0_ldu_fire_first_issue", io.lsin.fire && s0_isFirstIssue) 1371 XSPerfAccumulate("s0_fast_replay_issue", io.ldu_io.fast_rep_in.fire) 1372 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1373 XSPerfAccumulate("s0_stall_ld_dcache", s0_valid && !io.ldu_io.dcache.req.ready) 1374 XSPerfAccumulate("s0_stall_st_dcache", s0_valid && !io.stu_io.dcache.req.ready) 1375 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12)) 1376 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12)) 1377 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1378 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1379 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1380 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1381 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_src_select_vec(int_iss_idx)) 1382 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.ldu_io.prefetch_req.valid && !s0_hw_prf_select) 1383 XSPerfAccumulate("s0_hardware_prefetch_total", io.ldu_io.prefetch_req.valid) 1384 1385 XSPerfAccumulate("s1_in_valid", s1_valid) 1386 XSPerfAccumulate("s1_in_fire", s1_fire) 1387 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1388 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1389 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1390 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1391 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1392 1393 XSPerfAccumulate("s2_in_valid", s2_valid) 1394 XSPerfAccumulate("s2_in_fire", s2_fire) 1395 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1396 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.ldu_io.dcache.resp.bits.miss) 1397 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1398 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1399 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1400 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1401 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1402 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1403 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1404 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1405 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && io.ldu_io.dcache.s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1406 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss) // prefetch req miss in l1 1407 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.ldu_io.dcache.resp.bits.miss) // prefetch req hit in l1 1408 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss && !io.ldu_io.dcache.s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1409 XSPerfAccumulate("s2_forward_req", s2_fire && s2_in.forward_tlDchannel) 1410 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fire && s2_fwd_frm_d_chan && s2_fwd_data_valid) 1411 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fire && s2_fwd_frm_mshr && s2_fwd_data_valid) 1412 1413 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1414 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1415 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1416 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1417 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1418 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1419 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1420 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1421 1422 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1423 // hardware performance counter 1424 val perfEvents = Seq( 1425 ("load_s0_in_fire ", s0_fire ), 1426 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1427 ("stall_dcache ", s0_valid && s0_can_go && !io.ldu_io.dcache.req.ready ), 1428 ("load_s1_in_fire ", s0_fire ), 1429 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1430 ("load_s2_in_fire ", s1_fire ), 1431 ("load_s2_dcache_miss ", s2_fire && io.ldu_io.dcache.resp.bits.miss ), 1432 ) 1433 generatePerfEvent() 1434}