1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.fu.NewCSR._ 31import xiangshan.backend.rob.RobPtr 32import xiangshan.backend.fu._ 33import xiangshan.backend.fu.util.SdtrigExt 34import xiangshan.cache._ 35import xiangshan.cache.wpu.ReplayCarry 36import xiangshan.cache.mmu.{TlbCmd, TlbHintReq, TlbReq, TlbRequestIO, TlbResp} 37import xiangshan.mem.mdp._ 38 39class HybridUnit(implicit p: Parameters) extends XSModule 40 with HasLoadHelper 41 with HasPerfEvents 42 with HasDCacheParameters 43 with HasCircularQueuePtrHelper 44 with HasVLSUParameters 45 with SdtrigExt 46{ 47 val io = IO(new Bundle() { 48 // control 49 val redirect = Flipped(ValidIO(new Redirect)) 50 val csrCtrl = Flipped(new CustomCSRCtrlIO) 51 52 // flow in 53 val lsin = Flipped(Decoupled(new MemExuInput)) 54 55 // flow out 56 val ldout = DecoupledIO(new MemExuOutput) 57 val stout = DecoupledIO(new MemExuOutput) 58 59 val ldu_io = new Bundle() { 60 // dcache 61 val dcache = new DCacheLoadIO 62 63 // data path 64 val sbuffer = new LoadForwardQueryIO 65 val vec_forward = new LoadForwardQueryIO 66 val lsq = new LoadToLsqIO 67 val tl_d_channel = Input(new DcacheToLduForwardIO) 68 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 69 val tlb_hint = Flipped(new TlbHintReq) 70 val l2_hint = Input(Valid(new L2ToL1Hint)) 71 72 // fast wakeup 73 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 74 75 // trigger 76 val trigger = Vec(TriggerNum, new LoadUnitTriggerIO) 77 78 // load to load fast path 79 val l2l_fwd_in = Input(new LoadToLoadIO) 80 val l2l_fwd_out = Output(new LoadToLoadIO) 81 82 val ld_fast_match = Input(Bool()) 83 val ld_fast_fuOpType = Input(UInt()) 84 val ld_fast_imm = Input(UInt(12.W)) 85 86 // hardware prefetch to l1 cache req 87 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) 88 89 // iq cancel 90 val ldCancel = Output(new LoadCancelIO()) // use to cancel the uops waked by this load, and cancel load 91 92 // iq wakeup, use to wakeup consumer uop at load s2 93 val wakeup = ValidIO(new DynInst) 94 95 // load ecc error 96 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 97 98 // schedule error query 99 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 100 101 // queue-based replay 102 val replay = Flipped(Decoupled(new LsPipelineBundle)) 103 val lq_rep_full = Input(Bool()) 104 105 // misc 106 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 107 108 // Load fast replay path 109 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 110 val fast_rep_out = Decoupled(new LqWriteBundle) 111 112 // Load RAR rollback 113 val rollback = Valid(new Redirect) 114 115 // perf 116 val debug_ls = Output(new DebugLsInfoBundle) 117 val lsTopdownInfo = Output(new LsTopdownInfo) 118 } 119 120 val stu_io = new Bundle() { 121 val dcache = new DCacheStoreIO 122 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 123 val issue = Valid(new MemExuInput) 124 val lsq = ValidIO(new LsPipelineBundle) 125 val lsq_replenish = Output(new LsPipelineBundle()) 126 val stld_nuke_query = Valid(new StoreNukeQueryIO) 127 val st_mask_out = Valid(new StoreMaskBundle) 128 val debug_ls = Output(new DebugLsInfoBundle) 129 } 130 131 val vec_stu_io = new Bundle() { 132 val in = Flipped(DecoupledIO(new VecPipeBundle())) 133 val isFirstIssue = Input(Bool()) 134 val lsq = ValidIO(new LsPipelineBundle()) 135 val feedbackSlow = ValidIO(new VSFQFeedback) 136 } 137 138 // speculative for gated control 139 val s0_prefetch_spec = Output(Bool()) 140 val s1_prefetch_spec = Output(Bool()) 141 // prefetch 142 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to sms 143 val prefetch_train_l1 = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to stream & stride 144 val canAcceptLowConfPrefetch = Output(Bool()) 145 val canAcceptHighConfPrefetch = Output(Bool()) 146 val correctMissTrain = Input(Bool()) 147 148 // data path 149 val tlb = new TlbRequestIO(2) 150 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 151 152 // rs feedback 153 val feedback_fast = ValidIO(new RSFeedback) // stage 2 154 val feedback_slow = ValidIO(new RSFeedback) // stage 3 155 156 // for store trigger 157 val fromCsrTrigger = Input(new CsrTriggerBundle) 158 }) 159 160 val StorePrefetchL1Enabled = EnableStorePrefetchAtCommit || EnableStorePrefetchAtIssue || EnableStorePrefetchSPB 161 val s1_ready, s2_ready, s3_ready, sx_can_go = WireInit(false.B) 162 163 // Pipeline 164 // -------------------------------------------------------------------------------- 165 // stage 0 166 // -------------------------------------------------------------------------------- 167 // generate addr, use addr to query DCache and DTLB 168 val s0_valid = Wire(Bool()) 169 val s0_dcache_ready = Wire(Bool()) 170 val s0_kill = Wire(Bool()) 171 val s0_vaddr = Wire(UInt(VAddrBits.W)) 172 val s0_mask = Wire(UInt((VLEN/8).W)) 173 val s0_uop = Wire(new DynInst) 174 val s0_has_rob_entry = Wire(Bool()) 175 val s0_mshrid = Wire(UInt()) 176 val s0_try_l2l = Wire(Bool()) 177 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 178 val s0_isFirstIssue = Wire(Bool()) 179 val s0_fast_rep = Wire(Bool()) 180 val s0_ld_rep = Wire(Bool()) 181 val s0_l2l_fwd = Wire(Bool()) 182 val s0_sched_idx = Wire(UInt()) 183 val s0_can_go = s1_ready 184 val s0_fire = s0_valid && s0_dcache_ready && s0_can_go 185 val s0_out = Wire(new LqWriteBundle) 186 // vector 187 val s0_isvec = WireInit(false.B) 188 val s0_vecActive = WireInit(true.B) 189 // val s0_flowPtr = WireInit(0.U.asTypeOf(new VsFlowPtr)) 190 val s0_isLastElem = WireInit(false.B) 191 192 // load flow select/gen 193 // src0: super load replayed by LSQ (cache miss replay) (io.ldu_io.replay) 194 // src1: fast load replay (io.ldu_io.fast_rep_in) 195 // src2: load replayed by LSQ (io.ldu_io.replay) 196 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 197 // src4: int read / software prefetch first issue from RS (io.in) 198 // src5: vec read first issue from RS (TODO) 199 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 200 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 201 // priority: high to low 202 val s0_ld_flow = FuType.isLoad(s0_uop.fuType) || FuType.isVLoad(s0_uop.fuType) 203 val s0_rep_stall = io.lsin.valid && isAfter(io.ldu_io.replay.bits.uop.robIdx, io.lsin.bits.uop.robIdx) 204 val s0_super_ld_rep_valid = io.ldu_io.replay.valid && io.ldu_io.replay.bits.forward_tlDchannel 205 val s0_ld_fast_rep_valid = io.ldu_io.fast_rep_in.valid 206 val s0_ld_rep_valid = io.ldu_io.replay.valid && !io.ldu_io.replay.bits.forward_tlDchannel && !s0_rep_stall 207 val s0_high_conf_prf_valid = io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence > 0.U 208 val s0_int_iss_valid = io.lsin.valid // int flow first issue or software prefetch 209 val s0_vec_iss_valid = io.vec_stu_io.in.valid 210 val s0_l2l_fwd_valid = io.ldu_io.l2l_fwd_in.valid && io.ldu_io.ld_fast_match 211 val s0_low_conf_prf_valid = io.ldu_io.prefetch_req.valid && io.ldu_io.prefetch_req.bits.confidence === 0.U 212 dontTouch(s0_super_ld_rep_valid) 213 dontTouch(s0_ld_fast_rep_valid) 214 dontTouch(s0_ld_rep_valid) 215 dontTouch(s0_high_conf_prf_valid) 216 dontTouch(s0_int_iss_valid) 217 dontTouch(s0_vec_iss_valid) 218 dontTouch(s0_l2l_fwd_valid) 219 dontTouch(s0_low_conf_prf_valid) 220 221 // load flow source ready 222 val s0_super_ld_rep_ready = WireInit(true.B) 223 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 224 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 225 !s0_ld_fast_rep_valid 226 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 227 !s0_ld_fast_rep_valid && 228 !s0_ld_rep_valid 229 230 val s0_int_iss_ready = !s0_super_ld_rep_valid && 231 !s0_ld_fast_rep_valid && 232 !s0_ld_rep_valid && 233 !s0_high_conf_prf_valid 234 235 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 236 !s0_ld_fast_rep_valid && 237 !s0_ld_rep_valid && 238 !s0_high_conf_prf_valid && 239 !s0_int_iss_valid 240 241 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 242 !s0_ld_fast_rep_valid && 243 !s0_ld_rep_valid && 244 !s0_high_conf_prf_valid && 245 !s0_int_iss_valid && 246 !s0_vec_iss_valid 247 248 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 249 !s0_ld_fast_rep_valid && 250 !s0_ld_rep_valid && 251 !s0_high_conf_prf_valid && 252 !s0_int_iss_valid && 253 !s0_vec_iss_valid && 254 !s0_l2l_fwd_valid 255 dontTouch(s0_super_ld_rep_ready) 256 dontTouch(s0_ld_fast_rep_ready) 257 dontTouch(s0_ld_rep_ready) 258 dontTouch(s0_high_conf_prf_ready) 259 dontTouch(s0_int_iss_ready) 260 dontTouch(s0_vec_iss_ready) 261 dontTouch(s0_l2l_fwd_ready) 262 dontTouch(s0_low_conf_prf_ready) 263 264 // load flow source select (OH) 265 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 266 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 267 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 268 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 269 s0_low_conf_prf_ready && s0_low_conf_prf_valid 270 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 271 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 272 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 273 dontTouch(s0_super_ld_rep_select) 274 dontTouch(s0_ld_fast_rep_select) 275 dontTouch(s0_ld_rep_select) 276 dontTouch(s0_hw_prf_select) 277 dontTouch(s0_int_iss_select) 278 dontTouch(s0_vec_iss_select) 279 dontTouch(s0_l2l_fwd_select) 280 281 s0_valid := (s0_super_ld_rep_valid || 282 s0_ld_fast_rep_valid || 283 s0_ld_rep_valid || 284 s0_high_conf_prf_valid || 285 s0_int_iss_valid || 286 s0_vec_iss_valid || 287 s0_l2l_fwd_valid || 288 s0_low_conf_prf_valid) && !s0_kill 289 290 // which is S0's out is ready and dcache is ready 291 val s0_try_ptr_chasing = s0_l2l_fwd_select 292 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.ldu_io.dcache.req.ready 293 val s0_ptr_chasing_vaddr = io.ldu_io.l2l_fwd_in.data(5, 0) +& io.ldu_io.ld_fast_imm(5, 0) 294 val s0_ptr_chasing_canceled = WireInit(false.B) 295 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 296 297 // prefetch related ctrl signal 298 val s0_prf = Wire(Bool()) 299 val s0_prf_rd = Wire(Bool()) 300 val s0_prf_wr = Wire(Bool()) 301 val s0_hw_prf = s0_hw_prf_select 302 303 io.canAcceptLowConfPrefetch := s0_low_conf_prf_ready && io.ldu_io.dcache.req.ready 304 io.canAcceptHighConfPrefetch := s0_high_conf_prf_ready && io.ldu_io.dcache.req.ready 305 306 if (StorePrefetchL1Enabled) { 307 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, io.stu_io.dcache.req.ready) 308 } else { 309 s0_dcache_ready := Mux(s0_ld_flow, io.ldu_io.dcache.req.ready, true.B) 310 } 311 312 // query DTLB 313 io.tlb.req.valid := s0_valid && s0_dcache_ready 314 io.tlb.req.bits.cmd := Mux(s0_prf, 315 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 316 Mux(s0_ld_flow, TlbCmd.read, TlbCmd.write) 317 ) 318 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.paddr, s0_vaddr) 319 io.tlb.req.bits.size := Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1, 0), LSUOpType.size(s0_uop.fuOpType)) // may broken if use it in feature 320 io.tlb.req.bits.kill := s0_kill 321 io.tlb.req.bits.memidx.is_ld := s0_ld_flow 322 io.tlb.req.bits.memidx.is_st := !s0_ld_flow 323 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 324 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 325 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 326 io.tlb.req.bits.debug.pc := s0_uop.pc 327 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 328 329 // query DCache 330 // for load 331 io.ldu_io.dcache.req.valid := s0_valid && s0_dcache_ready && s0_ld_flow 332 io.ldu_io.dcache.req.bits.cmd := Mux(s0_prf_rd, MemoryOpConstants.M_PFR, 333 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD)) 334 io.ldu_io.dcache.req.bits.vaddr := s0_vaddr 335 io.ldu_io.dcache.req.bits.mask := s0_mask 336 io.ldu_io.dcache.req.bits.data := DontCare 337 io.ldu_io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 338 io.ldu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 339 io.ldu_io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 340 io.ldu_io.dcache.req.bits.replayCarry := s0_rep_carry 341 io.ldu_io.dcache.req.bits.id := DontCare // TODO: update cache meta 342 io.ldu_io.dcache.pf_source := Mux(s0_hw_prf_select, io.ldu_io.prefetch_req.bits.pf_source.value, L1_HW_PREFETCH_NULL) 343 io.ldu_io.dcache.is128Req := is128Bit(io.vec_stu_io.in.bits.alignedType) && io.vec_stu_io.in.valid && s0_vec_iss_select 344 345 // for store 346 io.stu_io.dcache.req.valid := s0_valid && s0_dcache_ready && !s0_ld_flow && !s0_prf 347 io.stu_io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 348 io.stu_io.dcache.req.bits.vaddr := s0_vaddr 349 io.stu_io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, STORE_SOURCE.U) 350 351 // load flow priority mux 352 def fromNullSource() = { 353 s0_vaddr := 0.U 354 s0_mask := 0.U 355 s0_uop := 0.U.asTypeOf(new DynInst) 356 s0_try_l2l := false.B 357 s0_has_rob_entry := false.B 358 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 359 s0_mshrid := 0.U 360 s0_isFirstIssue := false.B 361 s0_fast_rep := false.B 362 s0_ld_rep := false.B 363 s0_l2l_fwd := false.B 364 s0_prf := false.B 365 s0_prf_rd := false.B 366 s0_prf_wr := false.B 367 s0_sched_idx := 0.U 368 } 369 370 def fromFastReplaySource(src: LqWriteBundle) = { 371 s0_vaddr := src.vaddr 372 s0_mask := src.mask 373 s0_uop := src.uop 374 s0_try_l2l := false.B 375 s0_has_rob_entry := src.hasROBEntry 376 s0_rep_carry := src.rep_info.rep_carry 377 s0_mshrid := src.rep_info.mshr_id 378 s0_isFirstIssue := false.B 379 s0_fast_rep := true.B 380 s0_ld_rep := src.isLoadReplay 381 s0_l2l_fwd := false.B 382 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 383 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 384 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 385 s0_sched_idx := src.schedIndex 386 } 387 388 def fromNormalReplaySource(src: LsPipelineBundle) = { 389 s0_vaddr := src.vaddr 390 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 391 s0_uop := src.uop 392 s0_try_l2l := false.B 393 s0_has_rob_entry := true.B 394 s0_rep_carry := src.replayCarry 395 s0_mshrid := src.mshrid 396 s0_isFirstIssue := false.B 397 s0_fast_rep := false.B 398 s0_ld_rep := true.B 399 s0_l2l_fwd := false.B 400 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 401 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 402 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 403 s0_sched_idx := src.schedIndex 404 } 405 406 def fromPrefetchSource(src: L1PrefetchReq) = { 407 s0_vaddr := src.getVaddr() 408 s0_mask := 0.U 409 s0_uop := DontCare 410 s0_try_l2l := false.B 411 s0_has_rob_entry := false.B 412 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 413 s0_mshrid := 0.U 414 s0_isFirstIssue := false.B 415 s0_fast_rep := false.B 416 s0_ld_rep := false.B 417 s0_l2l_fwd := false.B 418 s0_prf := true.B 419 s0_prf_rd := !src.is_store 420 s0_prf_wr := src.is_store 421 s0_sched_idx := 0.U 422 } 423 424 def fromIntIssueSource(src: MemExuInput) = { 425 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 426 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 427 s0_uop := src.uop 428 s0_try_l2l := false.B 429 s0_has_rob_entry := true.B 430 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 431 s0_mshrid := 0.U 432 s0_isFirstIssue := true.B 433 s0_fast_rep := false.B 434 s0_ld_rep := false.B 435 s0_l2l_fwd := false.B 436 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 437 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 438 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 439 s0_sched_idx := 0.U 440 } 441 442 def fromVecIssueSource(src: VecPipeBundle) = { 443 // For now, vector port handles only vector store flows 444 s0_vaddr := src.vaddr 445 s0_mask := src.mask 446 s0_uop := src.uop 447 s0_try_l2l := false.B 448 s0_has_rob_entry := true.B 449 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 450 s0_mshrid := 0.U 451 // s0_isFirstIssue := src.isFirstIssue 452 s0_fast_rep := false.B 453 s0_ld_rep := false.B 454 s0_l2l_fwd := false.B 455 s0_prf := false.B 456 s0_prf_rd := false.B 457 s0_prf_wr := false.B 458 s0_sched_idx := 0.U 459 460 s0_isvec := true.B 461 s0_vecActive := io.vec_stu_io.in.bits.vecActive 462 // s0_flowPtr := io.vec_stu_io.in.bits.flowPtr 463 // s0_isLastElem := io.vec_stu_io.in.bits.isLastElem 464 } 465 466 def fromLoadToLoadSource(src: LoadToLoadIO) = { 467 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 468 s0_mask := genVWmask(s0_vaddr, io.ldu_io.ld_fast_fuOpType(1, 0)) 469 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 470 // Assume the pointer chasing is always ld. 471 s0_uop.fuOpType := io.ldu_io.ld_fast_fuOpType 472 s0_try_l2l := true.B 473 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing 474 // because these signals will be updated in S1 475 s0_has_rob_entry := false.B 476 s0_mshrid := 0.U 477 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 478 s0_isFirstIssue := true.B 479 s0_fast_rep := false.B 480 s0_ld_rep := false.B 481 s0_l2l_fwd := true.B 482 s0_prf := false.B 483 s0_prf_rd := false.B 484 s0_prf_wr := false.B 485 s0_sched_idx := 0.U 486 } 487 488 // set default 489 s0_uop := DontCare 490 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.ldu_io.replay.bits) } 491 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.ldu_io.fast_rep_in.bits) } 492 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.ldu_io.replay.bits) } 493 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.ldu_io.prefetch_req.bits) } 494 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.lsin.bits) } 495 .elsewhen (s0_vec_iss_select) { fromVecIssueSource(io.vec_stu_io.in.bits) } 496 .otherwise { 497 if (EnableLoadToLoadForward) { 498 fromLoadToLoadSource(io.ldu_io.l2l_fwd_in) 499 } else { 500 fromNullSource() 501 } 502 } 503 504 // address align check 505 val s0_addr_aligned = LookupTree(Mux(s0_isvec, io.vec_stu_io.in.bits.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 506 "b00".U -> true.B, //b 507 "b01".U -> (s0_vaddr(0) === 0.U), //h 508 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 509 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 510 ))// may broken if use it in feature 511 512 // accept load flow if dcache ready (tlb is always ready) 513 // TODO: prefetch need writeback to loadQueueFlag 514 s0_out := DontCare 515 s0_out.vaddr := s0_vaddr 516 s0_out.mask := s0_mask 517 s0_out.uop := s0_uop 518 s0_out.isFirstIssue := s0_isFirstIssue 519 s0_out.hasROBEntry := s0_has_rob_entry 520 s0_out.isPrefetch := s0_prf 521 s0_out.isHWPrefetch := s0_hw_prf 522 s0_out.isFastReplay := s0_fast_rep 523 s0_out.isLoadReplay := s0_ld_rep 524 s0_out.isFastPath := s0_l2l_fwd 525 s0_out.mshrid := s0_mshrid 526 s0_out.isvec := s0_isvec 527 s0_out.isLastElem := s0_isLastElem 528 s0_out.vecActive := s0_vecActive 529 // s0_out.sflowPtr := s0_flowPtr 530 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned && s0_ld_flow 531 s0_out.uop.exceptionVec(storeAddrMisaligned) := !s0_addr_aligned && !s0_ld_flow 532 s0_out.forward_tlDchannel := s0_super_ld_rep_select 533 when(io.tlb.req.valid && s0_isFirstIssue) { 534 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 535 }.otherwise{ 536 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 537 } 538 s0_out.schedIndex := s0_sched_idx 539 540 // load fast replay 541 io.ldu_io.fast_rep_in.ready := (s0_can_go && io.ldu_io.dcache.req.ready && s0_ld_fast_rep_ready) 542 543 // load flow source ready 544 // cache missed load has highest priority 545 // always accept cache missed load flow from load replay queue 546 io.ldu_io.replay.ready := (s0_can_go && io.ldu_io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 547 548 // accept load flow from rs when: 549 // 1) there is no lsq-replayed load 550 // 2) there is no fast replayed load 551 // 3) there is no high confidence prefetch request 552 io.lsin.ready := (s0_can_go && 553 Mux(FuType.isLoad(io.lsin.bits.uop.fuType), io.ldu_io.dcache.req.ready, 554 (if (StorePrefetchL1Enabled) io.stu_io.dcache.req.ready else true.B)) && s0_int_iss_ready) 555 io.vec_stu_io.in.ready := s0_can_go && io.ldu_io.dcache.req.ready && s0_vec_iss_ready 556 557 558 // for hw prefetch load flow feedback, to be added later 559 // io.prefetch_in.ready := s0_hw_prf_select 560 561 // dcache replacement extra info 562 // TODO: should prefetch load update replacement? 563 io.ldu_io.dcache.replacementUpdated := Mux(s0_ld_rep_select || s0_super_ld_rep_select, io.ldu_io.replay.bits.replacementUpdated, false.B) 564 565 io.stu_io.prefetch_req.ready := s1_ready && io.stu_io.dcache.req.ready && !io.lsin.valid 566 567 // load debug 568 XSDebug(io.ldu_io.dcache.req.fire && s0_ld_flow, 569 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 570 ) 571 XSDebug(s0_valid && s0_ld_flow, 572 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lqIdx ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 573 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 574 575 // store debug 576 XSDebug(io.stu_io.dcache.req.fire && !s0_ld_flow, 577 p"[DCACHE STORE REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 578 ) 579 XSDebug(s0_valid && !s0_ld_flow, 580 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, sqIdx ${Hexadecimal(s0_out.uop.sqIdx.asUInt)}, " + 581 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 582 583 584 // Pipeline 585 // -------------------------------------------------------------------------------- 586 // stage 1 587 // -------------------------------------------------------------------------------- 588 // TLB resp (send paddr to dcache) 589 val s1_valid = RegInit(false.B) 590 val s1_in = Wire(new LqWriteBundle) 591 val s1_out = Wire(new LqWriteBundle) 592 val s1_kill = Wire(Bool()) 593 val s1_can_go = s2_ready 594 val s1_fire = s1_valid && !s1_kill && s1_can_go 595 val s1_ld_flow = RegNext(s0_ld_flow) 596 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 597 val s1_isLastElem = RegEnable(s0_out.isLastElem, false.B, s0_fire) 598 599 s1_ready := !s1_valid || s1_kill || s2_ready 600 when (s0_fire) { s1_valid := true.B } 601 .elsewhen (s1_fire) { s1_valid := false.B } 602 .elsewhen (s1_kill) { s1_valid := false.B } 603 s1_in := RegEnable(s0_out, s0_fire) 604 605 val s1_fast_rep_dly_err = RegNext(io.ldu_io.fast_rep_in.bits.delayedLoadError) 606 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 607 val s1_l2l_fwd_dly_err = RegNext(io.ldu_io.l2l_fwd_in.dly_ld_err) 608 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 609 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 610 val s1_vaddr_hi = Wire(UInt()) 611 val s1_vaddr_lo = Wire(UInt()) 612 val s1_vaddr = Wire(UInt()) 613 val s1_paddr_dup_lsu = Wire(UInt()) 614 val s1_paddr_dup_dcache = Wire(UInt()) 615 val s1_ld_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 616 val s1_st_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR // af & pf exception were modified below. 617 val s1_exception = (s1_ld_flow && s1_ld_exception) || (!s1_ld_flow && s1_st_exception) 618 val s1_tlb_miss = io.tlb.resp.bits.miss 619 val s1_prf = s1_in.isPrefetch 620 val s1_hw_prf = s1_in.isHWPrefetch 621 val s1_sw_prf = s1_prf && !s1_hw_prf 622 val s1_tlb_memidx = io.tlb.resp.bits.memidx 623 624 // mmio cbo decoder 625 val s1_mmio_cbo = (s1_in.uop.fuOpType === LSUOpType.cbo_clean || 626 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 627 s1_in.uop.fuOpType === LSUOpType.cbo_inval) && !s1_ld_flow && !s1_prf 628 val s1_mmio = s1_mmio_cbo 629 630 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 631 s1_vaddr_lo := s1_in.vaddr(5, 0) 632 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 633 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 634 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 635 636 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && 637 s1_tlb_memidx.idx === s1_in.uop.lqIdx.value && s1_ld_flow) { 638 // printf("Load idx = %d\n", s1_tlb_memidx.idx) 639 s1_out.uop.debugInfo.tlbRespTime := GTimer() 640 } .elsewhen(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && 641 s1_tlb_memidx.idx === s1_out.uop.sqIdx.value && !s1_ld_flow) { 642 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 643 s1_out.uop.debugInfo.tlbRespTime := GTimer() 644 } 645 646 io.tlb.req_kill := s1_kill 647 io.tlb.resp.ready := true.B 648 649 io.ldu_io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 650 io.ldu_io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 651 io.ldu_io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception 652 653 // store to load forwarding 654 io.ldu_io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 655 io.ldu_io.sbuffer.vaddr := s1_vaddr 656 io.ldu_io.sbuffer.paddr := s1_paddr_dup_lsu 657 io.ldu_io.sbuffer.uop := s1_in.uop 658 io.ldu_io.sbuffer.sqIdx := s1_in.uop.sqIdx 659 io.ldu_io.sbuffer.mask := s1_in.mask 660 io.ldu_io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 661 662 io.ldu_io.vec_forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 663 io.ldu_io.vec_forward.vaddr := s1_vaddr 664 io.ldu_io.vec_forward.paddr := s1_paddr_dup_lsu 665 io.ldu_io.vec_forward.uop := s1_in.uop 666 io.ldu_io.vec_forward.sqIdx := s1_in.uop.sqIdx 667 io.ldu_io.vec_forward.mask := s1_in.mask 668 io.ldu_io.vec_forward.pc := s1_in.uop.pc // FIXME: remove it 669 670 io.ldu_io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_fast_rep_kill || s1_prf || !s1_ld_flow) 671 io.ldu_io.lsq.forward.vaddr := s1_vaddr 672 io.ldu_io.lsq.forward.paddr := s1_paddr_dup_lsu 673 io.ldu_io.lsq.forward.uop := s1_in.uop 674 io.ldu_io.lsq.forward.sqIdx := s1_in.uop.sqIdx 675 io.ldu_io.lsq.forward.sqIdxMask := 0.U 676 io.ldu_io.lsq.forward.mask := s1_in.mask 677 io.ldu_io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 678 679 // st-ld violation query 680 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 681 io.ldu_io.stld_nuke_query(w).valid && // query valid 682 isAfter(s1_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 683 // TODO: Fix me when vector instruction 684 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 685 (s1_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 686 })).asUInt.orR && !s1_tlb_miss && s1_ld_flow 687 688 s1_out := s1_in 689 s1_out.vaddr := s1_vaddr 690 s1_out.paddr := s1_paddr_dup_lsu 691 s1_out.tlbMiss := s1_tlb_miss 692 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 693 s1_out.rep_info.debug := s1_in.uop.debugInfo 694 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 695 s1_out.lateKill := s1_late_kill 696 697 // trigger 698 val storeTrigger = Module(new StoreTrigger) 699 storeTrigger.io.fromCsrTrigger.tdataVec := io.fromCsrTrigger.tdataVec 700 storeTrigger.io.fromCsrTrigger.tEnableVec := io.fromCsrTrigger.tEnableVec 701 storeTrigger.io.fromCsrTrigger.triggerCanRaiseBpExp := io.fromCsrTrigger.triggerCanRaiseBpExp 702 storeTrigger.io.fromStore.vaddr := s1_in.vaddr 703 704 when (s1_ld_flow) { 705 when (!s1_late_kill) { 706 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 707 // af & pf exception were modified 708 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld 709 s1_out.uop.exceptionVec(loadGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.ld 710 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld 711 } .otherwise { 712 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B 713 s1_out.uop.exceptionVec(loadAccessFault) := s1_late_kill 714 } 715 } .otherwise { 716 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st 717 s1_out.uop.exceptionVec(storeGuestPageFault) := io.tlb.resp.bits.excp(0).gpf.st 718 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st 719 s1_out.uop.trigger.backendHit := storeTrigger.io.toStore.triggerHitVec 720 s1_out.uop.trigger.backendCanFire := storeTrigger.io.toStore.triggerCanFireVec 721 s1_out.uop.exceptionVec(breakPoint) := storeTrigger.io.toStore.breakPointExp 722 } 723 724 // pointer chasing 725 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 726 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 727 val s1_fu_op_type_not_ld = WireInit(false.B) 728 val s1_not_fast_match = WireInit(false.B) 729 val s1_addr_mismatch = WireInit(false.B) 730 val s1_addr_misaligned = WireInit(false.B) 731 val s1_ptr_chasing_canceled = WireInit(false.B) 732 val s1_cancel_ptr_chasing = WireInit(false.B) 733 734 s1_kill := s1_late_kill || 735 s1_cancel_ptr_chasing || 736 s1_in.uop.robIdx.needFlush(io.redirect) || 737 RegEnable(s0_kill, false.B, io.lsin.valid || io.ldu_io.replay.valid || io.ldu_io.l2l_fwd_in.valid || io.ldu_io.fast_rep_in.valid || io.vec_stu_io.in.valid) 738 739 if (EnableLoadToLoadForward) { 740 // Sometimes, we need to cancel the load-load forwarding. 741 // These can be put at S0 if timing is bad at S1. 742 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 743 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ldu_io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 744 // Case 1: the address is misaligned, kill s1 745 s1_addr_misaligned := LookupTree(s1_in.uop.fuOpType(1, 0), List( 746 "b00".U -> false.B, //b 747 "b01".U -> (s1_vaddr(0) =/= 0.U), //h 748 "b10".U -> (s1_vaddr(1, 0) =/= 0.U), //w 749 "b11".U -> (s1_vaddr(2, 0) =/= 0.U) //d 750 )) 751 // Case 2: this load-load uop is cancelled 752 s1_ptr_chasing_canceled := !io.lsin.valid || FuType.isStore(io.lsin.bits.uop.fuType) 753 754 when (s1_try_ptr_chasing) { 755 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled 756 757 s1_in.uop := io.lsin.bits.uop 758 s1_in.isFirstIssue := io.lsin.bits.isFirstIssue 759 s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) 760 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 761 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 762 763 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 764 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 765 s1_in.uop.debugInfo.tlbRespTime := GTimer() 766 } 767 when (!s1_cancel_ptr_chasing) { 768 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.ldu_io.replay.fire && !io.ldu_io.fast_rep_in.fire && !(s0_high_conf_prf_valid && io.canAcceptHighConfPrefetch) 769 when (s1_try_ptr_chasing) { 770 io.lsin.ready := true.B 771 } 772 } 773 } 774 775 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 776 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 777 // to enable load-load, sqIdxMask must be calculated based on lsin.uop 778 // If the timing here is not OK, load-load forwarding has to be disabled. 779 // Or we calculate sqIdxMask at RS?? 780 io.ldu_io.lsq.forward.sqIdxMask := s1_sqIdx_mask 781 if (EnableLoadToLoadForward) { 782 when (s1_try_ptr_chasing) { 783 io.ldu_io.lsq.forward.sqIdxMask := UIntToMask(io.lsin.bits.uop.sqIdx.value, StoreQueueSize) 784 } 785 } 786 787 io.ldu_io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel && s1_ld_flow 788 io.ldu_io.forward_mshr.mshrid := s1_out.mshrid 789 io.ldu_io.forward_mshr.paddr := s1_out.paddr 790 791 io.ldu_io.wakeup.valid := s0_fire && s0_ld_flow && (s0_super_ld_rep_select || s0_ld_fast_rep_select || s0_ld_rep_select || s0_int_iss_select) 792 io.ldu_io.wakeup.bits := s0_uop 793 794 io.stu_io.dcache.s1_kill := s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect) 795 io.stu_io.dcache.s1_paddr := s1_paddr_dup_dcache 796 797 798 // load debug 799 XSDebug(s1_valid && s1_ld_flow, 800 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 801 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 802 803 // store debug 804 XSDebug(s1_valid && !s1_ld_flow, 805 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.sqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 806 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 807 808 // store out 809 io.stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && !s1_isvec 810 io.stu_io.lsq.bits := s1_out 811 io.stu_io.lsq.bits.miss := s1_tlb_miss 812 813 io.vec_stu_io.lsq.valid := s1_valid && !s1_ld_flow && !s1_prf && s1_isvec 814 io.vec_stu_io.lsq.bits := s1_out 815 io.vec_stu_io.lsq.bits.miss := s1_tlb_miss 816 io.vec_stu_io.lsq.bits.isLastElem := s1_isLastElem 817 818 io.stu_io.st_mask_out.valid := s1_valid && !s1_ld_flow && !s1_prf 819 io.stu_io.st_mask_out.bits.mask := s1_out.mask 820 io.stu_io.st_mask_out.bits.sqIdx := s1_out.uop.sqIdx 821 822 io.stu_io.issue.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf && !s1_isvec 823 io.stu_io.issue.bits := RegEnable(io.lsin.bits, io.lsin.fire) 824 825 // st-ld violation dectect request 826 io.stu_io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_ld_flow && !s1_prf 827 io.stu_io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 828 io.stu_io.stld_nuke_query.bits.paddr := s1_paddr_dup_lsu 829 io.stu_io.stld_nuke_query.bits.mask := s1_in.mask 830 831 // Pipeline 832 // -------------------------------------------------------------------------------- 833 // stage 2 834 // -------------------------------------------------------------------------------- 835 // s2: DCache resp 836 val s2_valid = RegInit(false.B) 837 val s2_in = Wire(new LqWriteBundle) 838 val s2_out = Wire(new LqWriteBundle) 839 val s2_kill = Wire(Bool()) 840 val s2_can_go = s3_ready 841 val s2_fire = s2_valid && !s2_kill && s2_can_go 842 val s2_isvec = RegEnable(s1_isvec, false.B, s1_fire) 843 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 844 val s2_paddr = RegEnable(s1_paddr_dup_lsu, s1_fire) 845 846 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 847 s2_ready := !s2_valid || s2_kill || s3_ready 848 when (s1_fire) { s2_valid := true.B } 849 .elsewhen (s2_fire) { s2_valid := false.B } 850 .elsewhen (s2_kill) { s2_valid := false.B } 851 s2_in := RegEnable(s1_out, s1_fire) 852 853 val s2_pmp = WireInit(io.pmp) 854 855 val s2_prf = s2_in.isPrefetch 856 val s2_hw_prf = s2_in.isHWPrefetch 857 val s2_ld_flow = RegEnable(s1_ld_flow, s1_fire) 858 859 // exception that may cause load addr to be invalid / illegal 860 // if such exception happen, that inst and its exception info 861 // will be force writebacked to rob 862 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 863 when (s2_ld_flow) { 864 when (!s2_in.lateKill) { 865 s2_exception_vec(loadAccessFault) := (s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld) && s2_vecActive 866 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 867 when (s2_prf || s2_in.tlbMiss) { 868 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 869 } 870 } 871 } .otherwise { 872 s2_exception_vec(storeAccessFault) := s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st 873 when (s2_prf || s2_in.tlbMiss) { 874 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 875 } 876 } 877 val s2_ld_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR && s2_ld_flow 878 val s2_st_exception = ExceptionNO.selectByFu(s2_exception_vec, StaCfg).asUInt.orR && !s2_ld_flow 879 val s2_exception = s2_ld_exception || s2_st_exception 880 881 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.ldu_io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 882 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.ldu_io.forward_mshr.forward() 883 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 884 885 // writeback access fault caused by ecc error / bus error 886 // * ecc data error is slow to generate, so we will not use it until load stage 3 887 // * in load stage 3, an extra signal io.load_error will be used to 888 val s2_actually_mmio = s2_pmp.mmio 889 val s2_ld_mmio = !s2_prf && 890 s2_actually_mmio && 891 !s2_exception && 892 !s2_in.tlbMiss && 893 s2_ld_flow 894 val s2_st_mmio = !s2_prf && 895 (RegNext(s1_mmio) || s2_pmp.mmio) && 896 !s2_exception && 897 !s2_in.tlbMiss && 898 !s2_ld_flow 899 val s2_st_atomic = !s2_prf && 900 (RegNext(s1_mmio) || s2_pmp.atomic) && 901 !s2_exception && 902 !s2_in.tlbMiss && 903 !s2_ld_flow 904 val s2_full_fwd = Wire(Bool()) 905 val s2_mem_amb = s2_in.uop.storeSetHit && 906 io.ldu_io.lsq.forward.addrInvalid 907 908 val s2_tlb_miss = s2_in.tlbMiss 909 val s2_fwd_fail = io.ldu_io.lsq.forward.dataInvalid || io.ldu_io.vec_forward.dataInvalid 910 val s2_dcache_miss = io.ldu_io.dcache.resp.bits.miss && 911 !s2_fwd_frm_d_chan_or_mshr && 912 !s2_full_fwd 913 914 val s2_mq_nack = io.ldu_io.dcache.s2_mq_nack && 915 !s2_fwd_frm_d_chan_or_mshr && 916 !s2_full_fwd 917 918 val s2_bank_conflict = io.ldu_io.dcache.s2_bank_conflict && 919 !s2_fwd_frm_d_chan_or_mshr && 920 !s2_full_fwd 921 922 val s2_wpu_pred_fail = io.ldu_io.dcache.s2_wpu_pred_fail && 923 !s2_fwd_frm_d_chan_or_mshr && 924 !s2_full_fwd 925 926 val s2_rar_nack = io.ldu_io.lsq.ldld_nuke_query.req.valid && 927 !io.ldu_io.lsq.ldld_nuke_query.req.ready 928 929 val s2_raw_nack = io.ldu_io.lsq.stld_nuke_query.req.valid && 930 !io.ldu_io.lsq.stld_nuke_query.req.ready 931 932 // st-ld violation query 933 // NeedFastRecovery Valid when 934 // 1. Fast recovery query request Valid. 935 // 2. Load instruction is younger than requestors(store instructions). 936 // 3. Physical address match. 937 // 4. Data contains. 938 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 939 io.ldu_io.stld_nuke_query(w).valid && // query valid 940 isAfter(s2_in.uop.robIdx, io.ldu_io.stld_nuke_query(w).bits.robIdx) && // older store 941 // TODO: Fix me when vector instruction 942 (s2_in.paddr(PAddrBits-1, 3) === io.ldu_io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 943 (s2_in.mask & io.ldu_io.stld_nuke_query(w).bits.mask).orR // data mask contain 944 })).asUInt.orR && s2_ld_flow || s2_in.rep_info.nuke 945 946 val s2_cache_handled = io.ldu_io.dcache.resp.bits.handled 947 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 948 io.ldu_io.dcache.resp.bits.tag_error 949 950 val s2_troublem = !s2_exception && 951 !s2_ld_mmio && 952 !s2_prf && 953 !s2_in.lateKill && 954 s2_ld_flow 955 956 io.ldu_io.dcache.resp.ready := true.B 957 io.stu_io.dcache.resp.ready := true.B 958 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_ld_mmio || s2_prf || s2_in.lateKill) && s2_ld_flow 959 assert(!(s2_valid && (s2_dcache_should_resp && !io.ldu_io.dcache.resp.valid)), "DCache response got lost") 960 961 // fast replay require 962 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 963 val s2_nuke_fast_rep = !s2_mq_nack && 964 !s2_dcache_miss && 965 !s2_bank_conflict && 966 !s2_wpu_pred_fail && 967 !s2_rar_nack && 968 !s2_raw_nack && 969 s2_nuke 970 971 val s2_fast_rep = !s2_mem_amb && 972 !s2_tlb_miss && 973 !s2_fwd_fail && 974 (s2_dcache_fast_rep || s2_nuke_fast_rep) && 975 s2_troublem 976 977 // need allocate new entry 978 val s2_can_query = !s2_mem_amb && 979 !s2_tlb_miss && 980 !s2_fwd_fail && 981 !s2_dcache_fast_rep && 982 s2_troublem 983 984 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 985 986 // ld-ld violation require 987 io.ldu_io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 988 io.ldu_io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 989 io.ldu_io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 990 io.ldu_io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 991 io.ldu_io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 992 993 // st-ld violation require 994 io.ldu_io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 995 io.ldu_io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 996 io.ldu_io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 997 io.ldu_io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 998 io.ldu_io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 999 1000 // merge forward result 1001 // lsq has higher priority than sbuffer 1002 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 1003 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 1004 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.ldu_io.lsq.forward.dataInvalid && !io.ldu_io.vec_forward.dataInvalid 1005 // generate XLEN/8 Muxs 1006 for (i <- 0 until VLEN / 8) { 1007 s2_fwd_mask(i) := io.ldu_io.lsq.forward.forwardMask(i) || io.ldu_io.sbuffer.forwardMask(i) || io.ldu_io.vec_forward.forwardMask(i) 1008 s2_fwd_data(i) := Mux( 1009 io.ldu_io.lsq.forward.forwardMask(i), 1010 io.ldu_io.lsq.forward.forwardData(i), 1011 Mux( 1012 io.ldu_io.vec_forward.forwardMask(i), 1013 io.ldu_io.vec_forward.forwardData(i), 1014 io.ldu_io.sbuffer.forwardData(i) 1015 ) 1016 ) 1017 } 1018 1019 XSDebug(s2_fire && s2_ld_flow, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 1020 s2_in.uop.pc, 1021 io.ldu_io.lsq.forward.forwardData.asUInt, io.ldu_io.lsq.forward.forwardMask.asUInt, 1022 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 1023 ) 1024 1025 // 1026 s2_out := s2_in 1027 s2_out.data := 0.U // data will be generated in load s3 1028 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception && s2_ld_flow 1029 s2_out.mmio := s2_ld_mmio || s2_st_mmio 1030 s2_out.atomic := s2_st_atomic 1031 s2_out.uop.flushPipe := false.B 1032 s2_out.uop.exceptionVec := s2_exception_vec 1033 s2_out.forwardMask := s2_fwd_mask 1034 s2_out.forwardData := s2_fwd_data 1035 s2_out.handledByMSHR := s2_cache_handled 1036 s2_out.miss := s2_dcache_miss && s2_troublem 1037 s2_out.feedbacked := io.feedback_fast.valid && !io.feedback_fast.bits.hit 1038 1039 // Generate replay signal caused by: 1040 // * st-ld violation check 1041 // * tlb miss 1042 // * dcache replay 1043 // * forward data invalid 1044 // * dcache miss 1045 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 1046 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 1047 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 1048 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 1049 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 1050 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 1051 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 1052 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 1053 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 1054 s2_out.rep_info.nuke := s2_nuke && s2_troublem 1055 s2_out.rep_info.full_fwd := s2_data_fwded 1056 s2_out.rep_info.data_inv_sq_idx := Mux(io.ldu_io.vec_forward.dataInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.dataInvalidSqIdx) 1057 s2_out.rep_info.addr_inv_sq_idx := Mux(io.ldu_io.vec_forward.addrInvalid, s2_out.uop.sqIdx, io.ldu_io.lsq.forward.addrInvalidSqIdx) 1058 s2_out.rep_info.rep_carry := io.ldu_io.dcache.resp.bits.replayCarry 1059 s2_out.rep_info.mshr_id := io.ldu_io.dcache.resp.bits.mshr_id 1060 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 1061 s2_out.rep_info.debug := s2_in.uop.debugInfo 1062 s2_out.rep_info.tlb_id := io.ldu_io.tlb_hint.id 1063 s2_out.rep_info.tlb_full := io.ldu_io.tlb_hint.full 1064 1065 // if forward fail, replay this inst from fetch 1066 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 1067 // if ld-ld violation is detected, replay from this inst from fetch 1068 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_ld_mmio && !s2_is_prefetch && !s2_in.tlbMiss 1069 // io.out.bits.uop.replayInst := false.B 1070 1071 // to be removed 1072 val s2_ld_need_fb = !s2_in.isLoadReplay && // already feedbacked 1073 io.ldu_io.lq_rep_full && // LoadQueueReplay is full 1074 s2_out.rep_info.need_rep && // need replay 1075 !s2_exception && // no exception is triggered 1076 !s2_hw_prf && // not hardware prefetch 1077 !s2_isvec 1078 val s2_st_need_fb = !s2_ld_flow && !s2_hw_prf && !s2_isvec 1079 io.feedback_fast.valid := s2_valid && (s2_ld_need_fb || s2_st_need_fb) 1080 io.feedback_fast.bits.hit := Mux(s2_ld_flow, false.B, !s2_tlb_miss) 1081 io.feedback_fast.bits.flushState := s2_in.ptwBack 1082 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 1083 io.feedback_fast.bits.sourceType := Mux(s2_ld_flow, RSFeedbackType.lrqFull, RSFeedbackType.tlbMiss) 1084 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 1085 1086 val s2_vec_feedback = Wire(Valid(new VSFQFeedback)) 1087 s2_vec_feedback.valid := s2_valid && !s2_ld_flow && !s2_hw_prf && s2_isvec 1088 // s2_vec_feedback.bits.flowPtr := s2_out.sflowPtr 1089 s2_vec_feedback.bits.hit := !s2_tlb_miss 1090 s2_vec_feedback.bits.sourceType := RSFeedbackType.tlbMiss 1091 s2_vec_feedback.bits.paddr := s2_paddr 1092 s2_vec_feedback.bits.mmio := s2_st_mmio 1093 s2_vec_feedback.bits.atomic := s2_st_mmio 1094 s2_vec_feedback.bits.exceptionVec := s2_exception_vec 1095 1096 io.stu_io.lsq_replenish := s2_out 1097 io.stu_io.lsq_replenish.miss := io.ldu_io.dcache.resp.fire && io.ldu_io.dcache.resp.bits.miss 1098 1099 io.ldu_io.ldCancel.ld1Cancel := false.B 1100 1101 // fast wakeup 1102 io.ldu_io.fast_uop.valid := RegNext( 1103 !io.ldu_io.dcache.s1_disable_fast_wakeup && 1104 s1_valid && 1105 !s1_kill && 1106 !io.tlb.resp.bits.miss && 1107 !io.ldu_io.lsq.forward.dataInvalidFast 1108 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_ld_mmio && s2_ld_flow) && !s2_isvec 1109 io.ldu_io.fast_uop.bits := RegNext(s1_out.uop) 1110 1111 // 1112 io.ldu_io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, false.B, s1_fire) 1113 1114 // prefetch train 1115 io.s0_prefetch_spec := s0_fire 1116 io.s1_prefetch_spec := s1_fire 1117 io.prefetch_train.valid := s2_valid && !s2_actually_mmio && !s2_in.tlbMiss 1118 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 1119 io.prefetch_train.bits.miss := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.miss, io.stu_io.dcache.resp.bits.miss) // TODO: use trace with bank conflict? 1120 io.prefetch_train.bits.meta_prefetch := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_prefetch, false.B) 1121 io.prefetch_train.bits.meta_access := Mux(s2_ld_flow, io.ldu_io.dcache.resp.bits.meta_access, false.B) 1122 1123 io.prefetch_train_l1.valid := s2_valid && !s2_actually_mmio && s2_ld_flow 1124 io.prefetch_train_l1.bits.fromLsPipelineBundle(s2_in) 1125 io.prefetch_train_l1.bits.miss := io.ldu_io.dcache.resp.bits.miss 1126 io.prefetch_train_l1.bits.meta_prefetch := io.ldu_io.dcache.resp.bits.meta_prefetch 1127 io.prefetch_train_l1.bits.meta_access := io.ldu_io.dcache.resp.bits.meta_access 1128 if (env.FPGAPlatform){ 1129 io.ldu_io.dcache.s0_pc := DontCare 1130 io.ldu_io.dcache.s1_pc := DontCare 1131 io.ldu_io.dcache.s2_pc := DontCare 1132 }else{ 1133 io.ldu_io.dcache.s0_pc := s0_out.uop.pc 1134 io.ldu_io.dcache.s1_pc := s1_out.uop.pc 1135 io.ldu_io.dcache.s2_pc := s2_out.uop.pc 1136 } 1137 io.ldu_io.dcache.s2_kill := s2_pmp.ld || s2_actually_mmio || s2_kill 1138 io.stu_io.dcache.s2_kill := s2_pmp.st || s2_actually_mmio || s2_kill 1139 io.stu_io.dcache.s2_pc := s2_out.uop.pc 1140 1141 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready && s1_ld_flow 1142 val s2_ld_valid_dup = RegInit(0.U(6.W)) 1143 s2_ld_valid_dup := 0x0.U(6.W) 1144 when (s1_ld_left_fire && !s1_out.isHWPrefetch && s1_ld_flow) { s2_ld_valid_dup := 0x3f.U(6.W) } 1145 when (s1_kill || s1_out.isHWPrefetch || !s1_ld_flow) { s2_ld_valid_dup := 0x0.U(6.W) } 1146 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch) || RegNext(!s1_ld_flow))) 1147 1148 // Pipeline 1149 // -------------------------------------------------------------------------------- 1150 // stage 3 1151 // -------------------------------------------------------------------------------- 1152 // writeback and update load queue 1153 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 1154 val s3_in = RegEnable(s2_out, s2_fire) 1155 val s3_out = Wire(Valid(new MemExuOutput)) 1156 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, false.B, s2_fire) 1157 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 1158 val s3_fast_rep = Wire(Bool()) 1159 val s3_ld_flow = RegNext(s2_ld_flow) 1160 val s3_troublem = RegNext(s2_troublem) 1161 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 1162 val s3_isvec = RegNext(s2_isvec) 1163 s3_ready := !s3_valid || s3_kill || sx_can_go 1164 1165 // forwrad last beat 1166 val (s3_fwd_frm_d_chan, s3_fwd_data_frm_d_chan) = io.ldu_io.tl_d_channel.forward(s2_valid && s2_out.forward_tlDchannel, s2_out.mshrid, s2_out.paddr) 1167 val s3_fwd_data_valid = RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1168 val s3_fwd_frm_d_chan_valid = (s3_fwd_frm_d_chan && s3_fwd_data_valid) && s3_ld_flow 1169 1170 1171 // s3 load fast replay 1172 io.ldu_io.fast_rep_out.valid := s3_valid && 1173 s3_fast_rep && 1174 !s3_in.uop.robIdx.needFlush(io.redirect) && 1175 s3_ld_flow && 1176 !s3_isvec 1177 io.ldu_io.fast_rep_out.bits := s3_in 1178 1179 io.ldu_io.lsq.ldin.valid := s3_valid && 1180 (!s3_fast_rep || !io.ldu_io.fast_rep_out.ready) && 1181 !s3_in.feedbacked && 1182 !s3_in.lateKill && 1183 s3_ld_flow 1184 io.ldu_io.lsq.ldin.bits := s3_in 1185 io.ldu_io.lsq.ldin.bits.miss := s3_in.miss && !s3_fwd_frm_d_chan_valid 1186 1187 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1188 io.ldu_io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1189 io.ldu_io.lsq.ldin.bits.replacementUpdated := io.ldu_io.dcache.resp.bits.replacementUpdated 1190 io.ldu_io.lsq.ldin.bits.missDbUpdated := RegNext(s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated) 1191 1192 val s3_dly_ld_err = 1193 if (EnableAccurateLoadError) { 1194 (s3_in.lateKill || io.ldu_io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1195 } else { 1196 WireInit(false.B) 1197 } 1198 io.ldu_io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1199 io.ldu_io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1200 io.ldu_io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1201 1202 val s3_vp_match_fail = RegNext(io.ldu_io.lsq.forward.matchInvalid || io.ldu_io.sbuffer.matchInvalid) && s3_troublem 1203 val s3_ldld_rep_inst = 1204 io.ldu_io.lsq.ldld_nuke_query.resp.valid && 1205 io.ldu_io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1206 RegNext(io.csrCtrl.ldld_vio_check_enable) 1207 1208 val s3_rep_info = WireInit(s3_in.rep_info) 1209 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && !s3_fwd_frm_d_chan_valid && s3_troublem 1210 val s3_rep_frm_fetch = s3_vp_match_fail 1211 val s3_flushPipe = s3_ldld_rep_inst 1212 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1213 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1214 !s3_in.uop.exceptionVec(loadAddrMisaligned) && 1215 s3_troublem 1216 1217 val s3_ld_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR && s3_ld_flow 1218 val s3_st_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, StaCfg).asUInt.orR && !s3_ld_flow 1219 val s3_exception = s3_ld_exception || s3_st_exception 1220 when ((s3_ld_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1221 io.ldu_io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1222 } .otherwise { 1223 io.ldu_io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1224 } 1225 1226 // Int flow, if hit, will be writebacked at s3 1227 s3_out.valid := s3_valid && 1228 (!s3_ld_flow && !s3_in.feedbacked || !io.ldu_io.lsq.ldin.bits.rep_info.need_rep) && !s3_in.mmio 1229 s3_out.bits.uop := s3_in.uop 1230 s3_out.bits.uop.exceptionVec(loadAccessFault) := (s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault)) && s3_ld_flow 1231 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1232 s3_out.bits.data := s3_in.data 1233 s3_out.bits.debug.isMMIO := s3_in.mmio 1234 s3_out.bits.debug.isPerfCnt := false.B 1235 s3_out.bits.debug.paddr := s3_in.paddr 1236 s3_out.bits.debug.vaddr := s3_in.vaddr 1237 1238 when (s3_force_rep) { 1239 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1240 } 1241 1242 io.ldu_io.rollback.valid := s3_valid && (s3_rep_frm_fetch || s3_flushPipe) && !s3_exception && s3_ld_flow 1243 io.ldu_io.rollback.bits := DontCare 1244 io.ldu_io.rollback.bits.isRVC := s3_out.bits.uop.preDecodeInfo.isRVC 1245 io.ldu_io.rollback.bits.robIdx := s3_out.bits.uop.robIdx 1246 io.ldu_io.rollback.bits.ftqIdx := s3_out.bits.uop.ftqPtr 1247 io.ldu_io.rollback.bits.ftqOffset := s3_out.bits.uop.ftqOffset 1248 io.ldu_io.rollback.bits.level := Mux(s3_rep_frm_fetch, RedirectLevel.flush, RedirectLevel.flushAfter) 1249 io.ldu_io.rollback.bits.cfiUpdate.target := s3_out.bits.uop.pc 1250 io.ldu_io.rollback.bits.debug_runahead_checkpoint_id := s3_out.bits.uop.debugInfo.runahead_checkpoint_id 1251 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1252 io.ldu_io.lsq.ldin.bits.uop := s3_out.bits.uop 1253 1254 val s3_revoke = s3_exception || io.ldu_io.lsq.ldin.bits.rep_info.need_rep 1255 io.ldu_io.lsq.ldld_nuke_query.revoke := s3_revoke 1256 io.ldu_io.lsq.stld_nuke_query.revoke := s3_revoke 1257 1258 // feedback slow 1259 s3_fast_rep := RegNext(s2_fast_rep) && 1260 !s3_in.feedbacked && 1261 !s3_in.lateKill && 1262 !s3_rep_frm_fetch && 1263 !s3_exception 1264 1265 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.ldu_io.fast_rep_out.ready) && !s3_in.feedbacked 1266 1267 // 1268 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting && s3_ld_flow 1269 io.feedback_slow.bits.hit := !io.ldu_io.lsq.ldin.bits.rep_info.need_rep || io.ldu_io.lsq.ldin.ready 1270 io.feedback_slow.bits.flushState := s3_in.ptwBack 1271 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1272 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1273 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1274 1275 io.vec_stu_io.feedbackSlow.valid := RegNext(s2_vec_feedback.valid && !s2_out.uop.robIdx.needFlush(io.redirect)) 1276 io.vec_stu_io.feedbackSlow.bits := RegNext(s2_vec_feedback.bits) 1277 1278 io.ldu_io.ldCancel.ld2Cancel := s3_valid && s3_ld_flow && ( // is load 1279 io.ldu_io.lsq.ldin.bits.rep_info.need_rep || s3_in.mmio // exe fail or is mmio 1280 ) 1281 1282 // data from dcache hit 1283 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1284 s3_ld_raw_data_frm_cache.respDcacheData := io.ldu_io.dcache.resp.bits.data_delayed 1285 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1286 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1287 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1288 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1289 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, false.B, s2_valid) || s3_fwd_frm_d_chan_valid 1290 s3_ld_raw_data_frm_cache.forwardData_D := Mux(s3_fwd_frm_d_chan_valid, s3_fwd_data_frm_d_chan, RegEnable(s2_fwd_data_frm_d_chan, s2_valid)) 1291 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, false.B, s2_valid) 1292 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1293 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1294 1295 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1296 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1297 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1298 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1299 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1300 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1301 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1302 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1303 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1304 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1305 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1306 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1307 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1308 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1309 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1310 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1311 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1312 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1313 )) 1314 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1315 1316 // FIXME: add 1 cycle delay ? 1317 io.ldout.bits := s3_out.bits 1318 io.ldout.bits.data := s3_ld_data_frm_cache 1319 io.ldout.valid := s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) && s3_ld_flow && !s3_isvec 1320 1321 // for uncache 1322 io.ldu_io.lsq.uncache.ready := true.B 1323 1324 // fast load to load forward 1325 if (EnableLoadToLoadForward) { 1326 io.ldu_io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill && s3_ld_flow 1327 io.ldu_io.l2l_fwd_out.data := s3_ld_data_frm_cache 1328 io.ldu_io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1329 } else { 1330 io.ldu_io.l2l_fwd_out.valid := false.B 1331 io.ldu_io.l2l_fwd_out.data := DontCare 1332 io.ldu_io.l2l_fwd_out.dly_ld_err := DontCare 1333 } 1334 1335 // hybrid unit writeback to rob 1336 // delay params 1337 val SelectGroupSize = RollbackGroupSize 1338 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 1339 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 1340 val TotalDelayCycles = TotalSelectCycles - 2 1341 1342 // writeback 1343 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 1344 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 1345 val sx_in = Wire(Vec(TotalDelayCycles + 1, new MemExuOutput)) 1346 1347 sx_can_go := sx_ready.head 1348 for (i <- 0 until TotalDelayCycles + 1) { 1349 if (i == 0) { 1350 sx_valid(i) := s3_valid && 1351 !s3_ld_flow && 1352 !s3_in.feedbacked && 1353 !s3_in.mmio 1354 sx_in(i) := s3_out.bits 1355 sx_ready(i) := !s3_valid(i) || sx_in(i).uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 1356 } else { 1357 val cur_kill = sx_in(i).uop.robIdx.needFlush(io.redirect) 1358 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1359 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 1360 val prev_fire = sx_valid(i-1) && !sx_in(i-1).uop.robIdx.needFlush(io.redirect) && sx_ready(i) 1361 1362 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 1363 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 1364 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), sx_valid_can_go) 1365 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 1366 } 1367 } 1368 1369 val sx_last_valid = sx_valid.takeRight(1).head 1370 val sx_last_ready = sx_ready.takeRight(1).head 1371 val sx_last_in = sx_in.takeRight(1).head 1372 1373 sx_last_ready := !sx_last_valid || sx_last_in.uop.robIdx.needFlush(io.redirect) || io.stout.ready 1374 io.stout.valid := sx_last_valid && !sx_last_in.uop.robIdx.needFlush(io.redirect) && FuType.isStore(sx_last_in.uop.fuType) 1375 io.stout.bits := sx_last_in 1376 1377 // trigger 1378 val ld_trigger = FuType.isLoad(io.ldout.bits.uop.fuType) 1379 val last_valid_data = RegEnable(io.ldout.bits.data, io.stout.fire) 1380 val hit_ld_addr_trig_hit_vec = Wire(Vec(TriggerNum, Bool())) 1381 val lq_ld_addr_trig_hit_vec = RegNext(io.ldu_io.lsq.trigger.lqLoadAddrTriggerHitVec) 1382 (0 until TriggerNum).map{i => { 1383 val tdata2 = RegNext(RegNext(io.ldu_io.trigger(i).tdata2)) 1384 val matchType = RegNext(RegNext(io.ldu_io.trigger(i).matchType)) 1385 val tEnable = RegNext(RegNext(io.ldu_io.trigger(i).tEnable)) 1386 1387 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s3_in.vaddr), tdata2, matchType, tEnable) 1388 io.ldu_io.trigger(i).addrHit := Mux(io.ldout.valid && ld_trigger, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1389 }} 1390 io.ldu_io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1391 1392 // FIXME: please move this part to LoadQueueReplay 1393 io.ldu_io.debug_ls := DontCare 1394 io.stu_io.debug_ls := DontCare 1395 io.stu_io.debug_ls.s1_isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch && !s1_ld_flow 1396 io.stu_io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 1397 1398 // Topdown 1399 io.ldu_io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1400 io.ldu_io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1401 io.ldu_io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1402 io.ldu_io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1403 io.ldu_io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1404 io.ldu_io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1405 io.ldu_io.lsTopdownInfo.s2.first_real_miss := io.ldu_io.dcache.resp.bits.real_miss 1406 io.ldu_io.lsTopdownInfo.s2.cache_miss_en := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated 1407 1408 // perf cnt 1409 XSPerfAccumulate("s0_in_valid", io.lsin.valid) 1410 XSPerfAccumulate("s0_in_block", io.lsin.valid && !io.lsin.fire) 1411 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1412 XSPerfAccumulate("s0_lsq_fire_first_issue", io.ldu_io.replay.fire) 1413 XSPerfAccumulate("s0_ldu_fire_first_issue", io.lsin.fire && s0_isFirstIssue) 1414 XSPerfAccumulate("s0_fast_replay_issue", io.ldu_io.fast_rep_in.fire) 1415 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1416 XSPerfAccumulate("s0_stall_ld_dcache", s0_valid && !io.ldu_io.dcache.req.ready) 1417 XSPerfAccumulate("s0_stall_st_dcache", s0_valid && !io.stu_io.dcache.req.ready) 1418 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12)) 1419 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12)) 1420 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1421 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.lsin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1422 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1423 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1424 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1425 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.ldu_io.prefetch_req.valid && !s0_hw_prf_select) 1426 XSPerfAccumulate("s0_hardware_prefetch_total", io.ldu_io.prefetch_req.valid) 1427 1428 XSPerfAccumulate("s1_in_valid", s1_valid) 1429 XSPerfAccumulate("s1_in_fire", s1_fire) 1430 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1431 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1432 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1433 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1434 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1435 1436 XSPerfAccumulate("s2_in_valid", s2_valid) 1437 XSPerfAccumulate("s2_in_fire", s2_fire) 1438 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1439 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.ldu_io.dcache.resp.bits.miss) 1440 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1441 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.ldu_io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1442 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1443 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1444 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1445 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1446 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1447 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1448 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && io.ldu_io.dcache.s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1449 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss) // prefetch req miss in l1 1450 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.ldu_io.dcache.resp.bits.miss) // prefetch req hit in l1 1451 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.ldu_io.dcache.resp.bits.miss && !io.ldu_io.dcache.s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1452 XSPerfAccumulate("s2_forward_req", s2_fire && s2_in.forward_tlDchannel) 1453 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fire && s2_fwd_frm_d_chan && s2_fwd_data_valid) 1454 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fire && s2_fwd_frm_mshr && s2_fwd_data_valid) 1455 1456 XSPerfAccumulate("s3_fwd_frm_d_chan", s3_valid && s3_fwd_frm_d_chan_valid) 1457 1458 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1459 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1460 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1461 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1462 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1463 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1464 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1465 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1466 1467 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1468 // hardware performance counter 1469 val perfEvents = Seq( 1470 ("load_s0_in_fire ", s0_fire ), 1471 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1472 ("stall_dcache ", s0_valid && s0_can_go && !io.ldu_io.dcache.req.ready ), 1473 ("load_s1_in_fire ", s0_fire ), 1474 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1475 ("load_s2_in_fire ", s1_fire ), 1476 ("load_s2_dcache_miss ", s2_fire && io.ldu_io.dcache.resp.bits.miss ), 1477 ) 1478 generatePerfEvent() 1479}