1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants} 8import xiangshan.backend.LSUOpType 9 10class AtomicsUnit extends XSModule with MemoryOpConstants{ 11 val io = IO(new Bundle() { 12 val in = Flipped(Decoupled(new ExuInput)) 13 val out = Decoupled(new ExuOutput) 14 val dcache = new DCacheWordIO 15 val dtlb = new TlbRequestIO 16 val flush_sbuffer = new SbufferFlushBundle 17 val tlbFeedback = ValidIO(new TlbFeedback) 18 val redirect = Flipped(ValidIO(new Redirect)) 19 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 20 }) 21 22 //------------------------------------------------------- 23 // Atomics Memory Accsess FSM 24 //------------------------------------------------------- 25 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 26 val state = RegInit(s_invalid) 27 val in = Reg(new ExuInput()) 28 val atom_override_xtval = RegInit(false.B) 29 // paddr after translation 30 val paddr = Reg(UInt()) 31 // dcache response data 32 val resp_data = Reg(UInt()) 33 val is_lrsc_valid = Reg(Bool()) 34 35 io.exceptionAddr.valid := atom_override_xtval 36 io.exceptionAddr.bits := in.src1 37 38 // assign default value to output signals 39 io.in.ready := false.B 40 io.out.valid := false.B 41 io.out.bits := DontCare 42 43 io.dcache.req.valid := false.B 44 io.dcache.req.bits := DontCare 45 io.dcache.resp.ready := false.B 46 47 io.dtlb.req.valid := false.B 48 io.dtlb.req.bits := DontCare 49 io.dtlb.resp.ready := false.B 50 51 io.flush_sbuffer.valid := false.B 52 53 XSDebug("state: %d\n", state) 54 55 when (state === s_invalid) { 56 io.in.ready := true.B 57 when (io.in.fire()) { 58 in := io.in.bits 59 state := s_tlb 60 } 61 } 62 63 // Send TLB feedback to store issue queue 64 // we send feedback right after we receives request 65 // also, we always treat amo as tlb hit 66 // since we will continue polling tlb all by ourself 67 io.tlbFeedback.valid := RegNext(io.in.fire()) 68 io.tlbFeedback.bits.hit := true.B 69 io.tlbFeedback.bits.roqIdx := in.uop.roqIdx 70 71 72 // tlb translation, manipulating signals && deal with exception 73 when (state === s_tlb) { 74 // send req to dtlb 75 // keep firing until tlb hit 76 io.dtlb.req.valid := true.B 77 io.dtlb.req.bits.vaddr := in.src1 78 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 79 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 80 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.read, TlbCmd.write) 81 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 82 io.dtlb.req.bits.debug.lsroqIdx := in.uop.lsroqIdx // FIXME: need update 83 io.dtlb.resp.ready := true.B 84 85 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 86 // exception handling 87 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 88 "b00".U -> true.B, //b 89 "b01".U -> (in.src1(0) === 0.U), //h 90 "b10".U -> (in.src1(1,0) === 0.U), //w 91 "b11".U -> (in.src1(2,0) === 0.U) //d 92 )) 93 in.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 94 in.uop.cf.exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 95 in.uop.cf.exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 96 val exception = !addrAligned || io.dtlb.resp.bits.excp.pf.st || io.dtlb.resp.bits.excp.pf.ld 97 when (exception) { 98 // check for exceptions 99 // if there are exceptions, no need to execute it 100 state := s_finish 101 atom_override_xtval := true.B 102 } .otherwise { 103 paddr := io.dtlb.resp.bits.paddr 104 state := s_flush_sbuffer_req 105 } 106 } 107 } 108 109 110 when (state === s_flush_sbuffer_req) { 111 io.flush_sbuffer.valid := true.B 112 state := s_flush_sbuffer_resp 113 } 114 115 when (state === s_flush_sbuffer_resp) { 116 when (io.flush_sbuffer.empty) { 117 state := s_cache_req 118 } 119 } 120 121 when (state === s_cache_req) { 122 io.dcache.req.valid := true.B 123 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 124 LSUOpType.lr_w -> M_XLR, 125 LSUOpType.sc_w -> M_XSC, 126 LSUOpType.amoswap_w -> M_XA_SWAP, 127 LSUOpType.amoadd_w -> M_XA_ADD, 128 LSUOpType.amoxor_w -> M_XA_XOR, 129 LSUOpType.amoand_w -> M_XA_AND, 130 LSUOpType.amoor_w -> M_XA_OR, 131 LSUOpType.amomin_w -> M_XA_MIN, 132 LSUOpType.amomax_w -> M_XA_MAX, 133 LSUOpType.amominu_w -> M_XA_MINU, 134 LSUOpType.amomaxu_w -> M_XA_MAXU, 135 136 LSUOpType.lr_d -> M_XLR, 137 LSUOpType.sc_d -> M_XSC, 138 LSUOpType.amoswap_d -> M_XA_SWAP, 139 LSUOpType.amoadd_d -> M_XA_ADD, 140 LSUOpType.amoxor_d -> M_XA_XOR, 141 LSUOpType.amoand_d -> M_XA_AND, 142 LSUOpType.amoor_d -> M_XA_OR, 143 LSUOpType.amomin_d -> M_XA_MIN, 144 LSUOpType.amomax_d -> M_XA_MAX, 145 LSUOpType.amominu_d -> M_XA_MINU, 146 LSUOpType.amomaxu_d -> M_XA_MAXU 147 )) 148 149 io.dcache.req.bits.addr := paddr 150 io.dcache.req.bits.data := genWdata(in.src2, in.uop.ctrl.fuOpType(1,0)) 151 // TODO: atomics do need mask: fix mask 152 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 153 io.dcache.req.bits.meta.id := DontCare 154 io.dcache.req.bits.meta.paddr := paddr 155 io.dcache.req.bits.meta.tlb_miss := false.B 156 io.dcache.req.bits.meta.replay := false.B 157 158 when(io.dcache.req.fire()){ 159 state := s_cache_resp 160 } 161 } 162 163 when (state === s_cache_resp) { 164 io.dcache.resp.ready := true.B 165 when(io.dcache.resp.fire()) { 166 is_lrsc_valid := io.dcache.resp.bits.meta.id 167 val rdata = io.dcache.resp.bits.data 168 val rdataSel = LookupTree(paddr(2, 0), List( 169 "b000".U -> rdata(63, 0), 170 "b001".U -> rdata(63, 8), 171 "b010".U -> rdata(63, 16), 172 "b011".U -> rdata(63, 24), 173 "b100".U -> rdata(63, 32), 174 "b101".U -> rdata(63, 40), 175 "b110".U -> rdata(63, 48), 176 "b111".U -> rdata(63, 56) 177 )) 178 179 resp_data := LookupTree(in.uop.ctrl.fuOpType, List( 180 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 181 LSUOpType.sc_w -> rdata, 182 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 183 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 184 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 185 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 186 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 187 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 188 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 189 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 190 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 191 192 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 193 LSUOpType.sc_d -> rdata, 194 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 195 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 196 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 197 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 198 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 199 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 200 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 201 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 202 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 203 )) 204 205 state := s_finish 206 } 207 } 208 209 when (state === s_finish) { 210 io.out.valid := true.B 211 io.out.bits.uop := in.uop 212 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 213 io.out.bits.data := resp_data 214 io.out.bits.redirectValid := false.B 215 io.out.bits.redirect := DontCare 216 io.out.bits.brUpdate := DontCare 217 io.out.bits.debug.isMMIO := AddressSpace.isMMIO(paddr) 218 when (io.out.fire()) { 219 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 220 state := s_invalid 221 } 222 } 223 224 when(io.redirect.valid){ 225 atom_override_xtval := false.B 226 } 227} 228