1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.cache.{AtomicWordIO, HasDCacheParameters, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 27import difftest._ 28import xiangshan.ExceptionNO._ 29import xiangshan.backend.fu.PMPRespBundle 30import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 31import xiangshan.backend.fu.util.SdtrigExt 32 33class AtomicsUnit(implicit p: Parameters) extends XSModule 34 with MemoryOpConstants 35 with HasDCacheParameters 36 with SdtrigExt{ 37 val io = IO(new Bundle() { 38 val hartId = Input(UInt(8.W)) 39 val in = Flipped(Decoupled(new MemExuInput)) 40 val storeDataIn = Flipped(Valid(new MemExuOutput)) // src2 from rs 41 val out = Decoupled(new MemExuOutput) 42 val dcache = new AtomicWordIO 43 val dtlb = new TlbRequestIO(2) 44 val pmpResp = Flipped(new PMPRespBundle()) 45 val flush_sbuffer = new SbufferFlushBundle 46 val feedbackSlow = ValidIO(new RSFeedback) 47 val redirect = Flipped(ValidIO(new Redirect)) 48 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 49 val csrCtrl = Flipped(new CustomCSRCtrlIO) 50 }) 51 52 //------------------------------------------------------- 53 // Atomics Memory Accsess FSM 54 //------------------------------------------------------- 55 val s_invalid :: s_tlb_and_flush_sbuffer_req :: s_pm :: s_wait_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_cache_resp_latch :: s_finish :: Nil = Enum(8) 56 val state = RegInit(s_invalid) 57 val out_valid = RegInit(false.B) 58 val data_valid = RegInit(false.B) 59 val in = Reg(new MemExuInput()) 60 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 61 val atom_override_xtval = RegInit(false.B) 62 val have_sent_first_tlb_req = RegInit(false.B) 63 val isLr = in.uop.fuOpType === LSUOpType.lr_w || in.uop.fuOpType === LSUOpType.lr_d 64 // paddr after translation 65 val paddr = Reg(UInt()) 66 val vaddr = in.src(0) 67 val is_mmio = Reg(Bool()) 68 69 // dcache response data 70 val resp_data = Reg(UInt()) 71 val resp_data_wire = WireInit(0.U) 72 val is_lrsc_valid = Reg(Bool()) 73 // sbuffer is empty or not 74 val sbuffer_empty = io.flush_sbuffer.empty 75 76 77 // Difftest signals 78 val paddr_reg = Reg(UInt(64.W)) 79 val data_reg = Reg(UInt(64.W)) 80 val mask_reg = Reg(UInt(8.W)) 81 val fuop_reg = Reg(UInt(8.W)) 82 83 io.exceptionAddr.valid := atom_override_xtval 84 io.exceptionAddr.bits := in.src(0) 85 86 // assign default value to output signals 87 io.in.ready := false.B 88 89 io.dcache.req.valid := false.B 90 io.dcache.req.bits := DontCare 91 92 io.dtlb.req.valid := false.B 93 io.dtlb.req.bits := DontCare 94 io.dtlb.req_kill := false.B 95 io.dtlb.resp.ready := true.B 96 97 io.flush_sbuffer.valid := false.B 98 99 XSDebug("state: %d\n", state) 100 101 when (state === s_invalid) { 102 io.in.ready := true.B 103 when (io.in.fire) { 104 in := io.in.bits 105 in.src(1) := in.src(1) // leave src2 unchanged 106 state := s_tlb_and_flush_sbuffer_req 107 have_sent_first_tlb_req := false.B 108 } 109 } 110 111 when (io.storeDataIn.fire) { 112 in.src(1) := io.storeDataIn.bits.data 113 data_valid := true.B 114 } 115 116 assert(!(io.storeDataIn.fire && data_valid), "atomic unit re-receive data") 117 118 // Send TLB feedback to store issue queue 119 // we send feedback right after we receives request 120 // also, we always treat amo as tlb hit 121 // since we will continue polling tlb all by ourself 122 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 123 io.feedbackSlow.bits.hit := true.B 124 io.feedbackSlow.bits.robIdx := RegEnable(io.in.bits.uop.robIdx, io.in.valid) 125 io.feedbackSlow.bits.flushState := DontCare 126 io.feedbackSlow.bits.sourceType := DontCare 127 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 128 129 // tlb translation, manipulating signals && deal with exception 130 // at the same time, flush sbuffer 131 when (state === s_tlb_and_flush_sbuffer_req) { 132 // send req to dtlb 133 // keep firing until tlb hit 134 io.dtlb.req.valid := true.B 135 io.dtlb.req.bits.vaddr := in.src(0) 136 io.dtlb.resp.ready := true.B 137 io.dtlb.req.bits.cmd := Mux(isLr, TlbCmd.atom_read, TlbCmd.atom_write) 138 io.dtlb.req.bits.debug.pc := in.uop.pc 139 io.dtlb.req.bits.debug.isFirstIssue := false.B 140 io.out.bits.uop.debugInfo.tlbFirstReqTime := GTimer() // FIXME lyq: it will be always assigned 141 142 // send req to sbuffer to flush it if it is not empty 143 io.flush_sbuffer.valid := Mux(sbuffer_empty, false.B, true.B) 144 145 // do not accept tlb resp in the first cycle 146 // this limition is for hw prefetcher 147 // when !have_sent_first_tlb_req, tlb resp may come from hw prefetch 148 have_sent_first_tlb_req := true.B 149 150 when(io.dtlb.resp.fire && have_sent_first_tlb_req){ 151 paddr := io.dtlb.resp.bits.paddr(0) 152 // exception handling 153 val addrAligned = LookupTree(in.uop.fuOpType(1,0), List( 154 "b00".U -> true.B, //b 155 "b01".U -> (in.src(0)(0) === 0.U), //h 156 "b10".U -> (in.src(0)(1,0) === 0.U), //w 157 "b11".U -> (in.src(0)(2,0) === 0.U) //d 158 )) 159 exceptionVec(loadAddrMisaligned) := !addrAligned && isLr 160 exceptionVec(storeAddrMisaligned) := !addrAligned && !isLr 161 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st 162 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld 163 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st 164 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld 165 166 when (!io.dtlb.resp.bits.miss) { 167 io.out.bits.uop.debugInfo.tlbRespTime := GTimer() 168 when (!addrAligned) { 169 // NOTE: when addrAligned, do not need to wait tlb actually 170 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 171 // if there are exceptions, no need to execute it 172 state := s_finish 173 out_valid := true.B 174 atom_override_xtval := true.B 175 } .otherwise { 176 state := s_pm 177 } 178 } 179 } 180 } 181 182 when (state === s_pm) { 183 val pmp = WireInit(io.pmpResp) 184 is_mmio := pmp.mmio 185 186 // NOTE: only handle load/store exception here, if other exception happens, don't send here 187 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 188 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 189 val exception_pa = pmp.st || pmp.ld 190 when (exception_va || exception_pa) { 191 state := s_finish 192 out_valid := true.B 193 atom_override_xtval := true.B 194 }.otherwise { 195 // if sbuffer has been flushed, go to query dcache, otherwise wait for sbuffer. 196 state := Mux(sbuffer_empty, s_cache_req, s_wait_flush_sbuffer_resp); 197 } 198 // update storeAccessFault bit 199 exceptionVec(loadAccessFault) := exceptionVec(loadAccessFault) || pmp.ld && isLr 200 exceptionVec(storeAccessFault) := exceptionVec(storeAccessFault) || pmp.st || pmp.ld && !isLr 201 } 202 203 when (state === s_wait_flush_sbuffer_resp) { 204 when (sbuffer_empty) { 205 state := s_cache_req 206 } 207 } 208 209 when (state === s_cache_req) { 210 val pipe_req = io.dcache.req.bits 211 pipe_req := DontCare 212 213 pipe_req.cmd := LookupTree(in.uop.fuOpType, List( 214 LSUOpType.lr_w -> M_XLR, 215 LSUOpType.sc_w -> M_XSC, 216 LSUOpType.amoswap_w -> M_XA_SWAP, 217 LSUOpType.amoadd_w -> M_XA_ADD, 218 LSUOpType.amoxor_w -> M_XA_XOR, 219 LSUOpType.amoand_w -> M_XA_AND, 220 LSUOpType.amoor_w -> M_XA_OR, 221 LSUOpType.amomin_w -> M_XA_MIN, 222 LSUOpType.amomax_w -> M_XA_MAX, 223 LSUOpType.amominu_w -> M_XA_MINU, 224 LSUOpType.amomaxu_w -> M_XA_MAXU, 225 226 LSUOpType.lr_d -> M_XLR, 227 LSUOpType.sc_d -> M_XSC, 228 LSUOpType.amoswap_d -> M_XA_SWAP, 229 LSUOpType.amoadd_d -> M_XA_ADD, 230 LSUOpType.amoxor_d -> M_XA_XOR, 231 LSUOpType.amoand_d -> M_XA_AND, 232 LSUOpType.amoor_d -> M_XA_OR, 233 LSUOpType.amomin_d -> M_XA_MIN, 234 LSUOpType.amomax_d -> M_XA_MAX, 235 LSUOpType.amominu_d -> M_XA_MINU, 236 LSUOpType.amomaxu_d -> M_XA_MAXU 237 )) 238 pipe_req.miss := false.B 239 pipe_req.probe := false.B 240 pipe_req.probe_need_data := false.B 241 pipe_req.source := AMO_SOURCE.U 242 pipe_req.addr := get_block_addr(paddr) 243 pipe_req.vaddr := get_block_addr(in.src(0)) // vaddr 244 pipe_req.word_idx := get_word(paddr) 245 pipe_req.amo_data := genWdata(in.src(1), in.uop.fuOpType(1,0)) 246 pipe_req.amo_mask := genWmask(paddr, in.uop.fuOpType(1,0)) 247 248 io.dcache.req.valid := Mux( 249 io.dcache.req.bits.cmd === M_XLR, 250 !io.dcache.block_lr, // block lr to survive in lr storm 251 data_valid // wait until src(1) is ready 252 ) 253 254 when(io.dcache.req.fire){ 255 state := s_cache_resp 256 paddr_reg := paddr 257 data_reg := io.dcache.req.bits.amo_data 258 mask_reg := io.dcache.req.bits.amo_mask 259 fuop_reg := in.uop.fuOpType 260 } 261 } 262 263 val dcache_resp_data = Reg(UInt()) 264 val dcache_resp_id = Reg(UInt()) 265 val dcache_resp_error = Reg(Bool()) 266 267 when (state === s_cache_resp) { 268 // when not miss 269 // everything is OK, simply send response back to sbuffer 270 // when miss and not replay 271 // wait for missQueue to handling miss and replaying our request 272 // when miss and replay 273 // req missed and fail to enter missQueue, manually replay it later 274 // TODO: add assertions: 275 // 1. add a replay delay counter? 276 // 2. when req gets into MissQueue, it should not miss any more 277 when(io.dcache.resp.fire) { 278 when(io.dcache.resp.bits.miss) { 279 when(io.dcache.resp.bits.replay) { 280 state := s_cache_req 281 } 282 } .otherwise { 283 dcache_resp_data := io.dcache.resp.bits.data 284 dcache_resp_id := io.dcache.resp.bits.id 285 dcache_resp_error := io.dcache.resp.bits.error 286 state := s_cache_resp_latch 287 } 288 } 289 } 290 291 when (state === s_cache_resp_latch) { 292 is_lrsc_valid := dcache_resp_id 293 val rdataSel = LookupTree(paddr(2, 0), List( 294 "b000".U -> dcache_resp_data(63, 0), 295 "b001".U -> dcache_resp_data(63, 8), 296 "b010".U -> dcache_resp_data(63, 16), 297 "b011".U -> dcache_resp_data(63, 24), 298 "b100".U -> dcache_resp_data(63, 32), 299 "b101".U -> dcache_resp_data(63, 40), 300 "b110".U -> dcache_resp_data(63, 48), 301 "b111".U -> dcache_resp_data(63, 56) 302 )) 303 304 resp_data_wire := LookupTree(in.uop.fuOpType, List( 305 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 306 LSUOpType.sc_w -> dcache_resp_data, 307 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 308 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 309 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 310 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 311 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 312 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 313 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 314 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 315 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 316 317 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 318 LSUOpType.sc_d -> dcache_resp_data, 319 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 320 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 321 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 322 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 323 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 324 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 325 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 326 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 327 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 328 )) 329 330 when (dcache_resp_error && io.csrCtrl.cache_error_enable) { 331 exceptionVec(loadAccessFault) := isLr 332 exceptionVec(storeAccessFault) := !isLr 333 assert(!exceptionVec(loadAccessFault)) 334 assert(!exceptionVec(storeAccessFault)) 335 } 336 337 resp_data := resp_data_wire 338 state := s_finish 339 out_valid := true.B 340 } 341 342 io.out.valid := out_valid 343 XSError((state === s_finish) =/= out_valid, "out_valid reg error\n") 344 io.out.bits := DontCare 345 io.out.bits.uop := in.uop 346 io.out.bits.uop.exceptionVec := exceptionVec 347 io.out.bits.data := resp_data 348 io.out.bits.debug.isMMIO := is_mmio 349 io.out.bits.debug.paddr := paddr 350 when (io.out.fire) { 351 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.pc, io.dcache.resp.bits.data) 352 state := s_invalid 353 out_valid := false.B 354 } 355 356 when (state === s_finish) { 357 data_valid := false.B 358 } 359 360 when (io.redirect.valid) { 361 atom_override_xtval := false.B 362 } 363 364 // atomic trigger 365 val csrCtrl = io.csrCtrl 366 val tdata = Reg(Vec(TriggerNum, new MatchTriggerIO)) 367 val tEnableVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) 368 tEnableVec := csrCtrl.mem_trigger.tEnableVec 369 when(csrCtrl.mem_trigger.tUpdate.valid) { 370 tdata(csrCtrl.mem_trigger.tUpdate.bits.addr) := csrCtrl.mem_trigger.tUpdate.bits.tdata 371 } 372 373 val frontendTriggerTimingVec = in.uop.trigger.frontendTiming 374 val frontendTriggerChainVec = in.uop.trigger.frontendChain 375 val frontendTriggerHitVec = in.uop.trigger.frontendHit 376 377 val backendTriggerTimingVec = tdata.map(_.timing) 378 val backendTriggerChainVec = tdata.map(_.chain) 379 val backendTriggerHitVec = WireInit(VecInit(Seq.fill(TriggerNum)(false.B))) 380 381 val triggerTimingVec = VecInit(backendTriggerTimingVec.zip(frontendTriggerTimingVec).map { case (b, f) => b || f }) 382 val triggerChainVec = VecInit(backendTriggerChainVec.zip(frontendTriggerChainVec).map { case (b, f) => b || f }) 383 val triggerHitVec = Reg(Vec(TriggerNum, Bool())) 384 triggerHitVec := VecInit(backendTriggerHitVec.zip(frontendTriggerHitVec).map { case (b, f) => b || f }) 385 386 val triggerCanFireVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) 387 when(state === s_cache_req) { 388 // store trigger 389 val store_hit = Wire(Vec(TriggerNum, Bool())) 390 for (j <- 0 until TriggerNum) { 391 store_hit(j) := !tdata(j).select && TriggerCmp( 392 vaddr, 393 tdata(j).tdata2, 394 tdata(j).matchType, 395 tEnableVec(j) && tdata(j).store 396 ) 397 } 398 // load trigger 399 val load_hit = Wire(Vec(TriggerNum, Bool())) 400 for (j <- 0 until TriggerNum) { 401 load_hit(j) := !tdata(j).select && TriggerCmp( 402 vaddr, 403 tdata(j).tdata2, 404 tdata(j).matchType, 405 tEnableVec(j) && tdata(j).load 406 ) 407 } 408 backendTriggerHitVec := store_hit.zip(load_hit).map { case (sh, lh) => sh || lh } 409 // triggerCanFireVec will update at T+1 410 TriggerCheckCanFire(TriggerNum, triggerCanFireVec, triggerHitVec, triggerTimingVec, triggerChainVec) 411 } 412 413 // addr trigger do cmp at s_cache_req 414 // trigger result is used at s_finish 415 // thus we can delay it safely 416 io.out.bits.uop.trigger.backendHit := triggerHitVec 417 io.out.bits.uop.trigger.backendCanFire := triggerCanFireVec 418 419 if (env.EnableDifftest) { 420 val difftest = DifftestModule(new DiffAtomicEvent) 421 difftest.coreid := io.hartId 422 difftest.valid := state === s_cache_resp_latch 423 difftest.addr := paddr_reg 424 difftest.data := data_reg 425 difftest.mask := mask_reg 426 difftest.fuop := fuop_reg 427 difftest.out := resp_data_wire 428 } 429 430 if (env.EnableDifftest || env.AlwaysBasicDiff) { 431 val uop = io.out.bits.uop 432 val difftest = DifftestModule(new DiffLrScEvent) 433 difftest.coreid := io.hartId 434 difftest.valid := io.out.fire && 435 (uop.fuOpType === LSUOpType.sc_d || uop.fuOpType === LSUOpType.sc_w) 436 difftest.success := is_lrsc_valid 437 } 438} 439