1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.cache.{AtomicWordIO, HasDCacheParameters, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 27import difftest._ 28import xiangshan.ExceptionNO._ 29import xiangshan.backend.fu.PMPRespBundle 30import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 31import xiangshan.backend.fu.NewCSR.TriggerUtil 32import xiangshan.backend.fu.util.SdtrigExt 33 34class AtomicsUnit(implicit p: Parameters) extends XSModule 35 with MemoryOpConstants 36 with HasDCacheParameters 37 with SdtrigExt{ 38 val io = IO(new Bundle() { 39 val hartId = Input(UInt(hartIdLen.W)) 40 val in = Flipped(Decoupled(new MemExuInput)) 41 val storeDataIn = Flipped(Valid(new MemExuOutput)) // src2 from rs 42 val out = Decoupled(new MemExuOutput) 43 val dcache = new AtomicWordIO 44 val dtlb = new TlbRequestIO(2) 45 val pmpResp = Flipped(new PMPRespBundle()) 46 val flush_sbuffer = new SbufferFlushBundle 47 val feedbackSlow = ValidIO(new RSFeedback) 48 val redirect = Flipped(ValidIO(new Redirect)) 49 val exceptionAddr = ValidIO(new Bundle { 50 val vaddr = UInt(VAddrBits.W) 51 val gpaddr = UInt(GPAddrBits.W) 52 }) 53 val csrCtrl = Flipped(new CustomCSRCtrlIO) 54 }) 55 56 //------------------------------------------------------- 57 // Atomics Memory Accsess FSM 58 //------------------------------------------------------- 59 val s_invalid :: s_tlb_and_flush_sbuffer_req :: s_pm :: s_wait_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_cache_resp_latch :: s_finish :: Nil = Enum(8) 60 val state = RegInit(s_invalid) 61 val out_valid = RegInit(false.B) 62 val data_valid = RegInit(false.B) 63 val in = Reg(new MemExuInput()) 64 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 65 val atom_override_xtval = RegInit(false.B) 66 val have_sent_first_tlb_req = RegInit(false.B) 67 val isLr = in.uop.fuOpType === LSUOpType.lr_w || in.uop.fuOpType === LSUOpType.lr_d 68 // paddr after translation 69 val paddr = Reg(UInt()) 70 val gpaddr = Reg(UInt()) 71 val vaddr = in.src(0) 72 val is_mmio = Reg(Bool()) 73 74 // dcache response data 75 val resp_data = Reg(UInt()) 76 val resp_data_wire = WireInit(0.U) 77 val is_lrsc_valid = Reg(Bool()) 78 // sbuffer is empty or not 79 val sbuffer_empty = io.flush_sbuffer.empty 80 81 82 // Difftest signals 83 val paddr_reg = Reg(UInt(64.W)) 84 val data_reg = Reg(UInt(64.W)) 85 val mask_reg = Reg(UInt(8.W)) 86 val fuop_reg = Reg(UInt(8.W)) 87 88 io.exceptionAddr.valid := atom_override_xtval 89 io.exceptionAddr.bits.vaddr := in.src(0) 90 io.exceptionAddr.bits.gpaddr := gpaddr 91 92 // assign default value to output signals 93 io.in.ready := false.B 94 95 io.dcache.req.valid := false.B 96 io.dcache.req.bits := DontCare 97 98 io.dtlb.req.valid := false.B 99 io.dtlb.req.bits := DontCare 100 io.dtlb.req_kill := false.B 101 io.dtlb.resp.ready := true.B 102 103 io.flush_sbuffer.valid := false.B 104 105 XSDebug("state: %d\n", state) 106 107 when (state === s_invalid) { 108 io.in.ready := true.B 109 when (io.in.fire) { 110 in := io.in.bits 111 in.src(1) := in.src(1) // leave src2 unchanged 112 state := s_tlb_and_flush_sbuffer_req 113 have_sent_first_tlb_req := false.B 114 } 115 } 116 117 when (io.storeDataIn.fire) { 118 in.src(1) := io.storeDataIn.bits.data 119 data_valid := true.B 120 } 121 122 assert(!(io.storeDataIn.fire && data_valid), "atomic unit re-receive data") 123 124 // Send TLB feedback to store issue queue 125 // we send feedback right after we receives request 126 // also, we always treat amo as tlb hit 127 // since we will continue polling tlb all by ourself 128 io.feedbackSlow.valid := GatedValidRegNext(GatedValidRegNext(io.in.valid)) 129 io.feedbackSlow.bits.hit := true.B 130 io.feedbackSlow.bits.robIdx := RegEnable(io.in.bits.uop.robIdx, io.in.valid) 131 io.feedbackSlow.bits.sqIdx := RegEnable(io.in.bits.uop.sqIdx, io.in.valid) 132 io.feedbackSlow.bits.lqIdx := RegEnable(io.in.bits.uop.lqIdx, io.in.valid) 133 io.feedbackSlow.bits.flushState := DontCare 134 io.feedbackSlow.bits.sourceType := DontCare 135 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 136 137 // tlb translation, manipulating signals && deal with exception 138 // at the same time, flush sbuffer 139 when (state === s_tlb_and_flush_sbuffer_req) { 140 // send req to dtlb 141 // keep firing until tlb hit 142 io.dtlb.req.valid := true.B 143 io.dtlb.req.bits.vaddr := in.src(0) 144 io.dtlb.resp.ready := true.B 145 io.dtlb.req.bits.cmd := Mux(isLr, TlbCmd.atom_read, TlbCmd.atom_write) 146 io.dtlb.req.bits.debug.pc := in.uop.pc 147 io.dtlb.req.bits.debug.robIdx := in.uop.robIdx 148 io.dtlb.req.bits.debug.isFirstIssue := false.B 149 io.out.bits.uop.debugInfo.tlbFirstReqTime := GTimer() // FIXME lyq: it will be always assigned 150 151 // send req to sbuffer to flush it if it is not empty 152 io.flush_sbuffer.valid := Mux(sbuffer_empty, false.B, true.B) 153 154 // do not accept tlb resp in the first cycle 155 // this limition is for hw prefetcher 156 // when !have_sent_first_tlb_req, tlb resp may come from hw prefetch 157 have_sent_first_tlb_req := true.B 158 159 when(io.dtlb.resp.fire && have_sent_first_tlb_req){ 160 paddr := io.dtlb.resp.bits.paddr(0) 161 gpaddr := io.dtlb.resp.bits.gpaddr(0) 162 // exception handling 163 val addrAligned = LookupTree(in.uop.fuOpType(1,0), List( 164 "b00".U -> true.B, //b 165 "b01".U -> (in.src(0)(0) === 0.U), //h 166 "b10".U -> (in.src(0)(1,0) === 0.U), //w 167 "b11".U -> (in.src(0)(2,0) === 0.U) //d 168 )) 169 exceptionVec(loadAddrMisaligned) := !addrAligned && isLr 170 exceptionVec(storeAddrMisaligned) := !addrAligned && !isLr 171 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp(0).pf.st 172 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp(0).pf.ld 173 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp(0).af.st 174 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp(0).af.ld 175 exceptionVec(storeGuestPageFault) := io.dtlb.resp.bits.excp(0).gpf.st 176 exceptionVec(loadGuestPageFault) := io.dtlb.resp.bits.excp(0).gpf.ld 177 178 when (!io.dtlb.resp.bits.miss) { 179 io.out.bits.uop.debugInfo.tlbRespTime := GTimer() 180 when (!addrAligned) { 181 // NOTE: when addrAligned, do not need to wait tlb actually 182 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 183 // if there are exceptions, no need to execute it 184 state := s_finish 185 out_valid := true.B 186 atom_override_xtval := true.B 187 } .otherwise { 188 state := s_pm 189 } 190 } 191 } 192 } 193 194 when (state === s_pm) { 195 val pmp = WireInit(io.pmpResp) 196 is_mmio := pmp.mmio 197 198 // NOTE: only handle load/store exception here, if other exception happens, don't send here 199 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 200 exceptionVec(storeGuestPageFault) || exceptionVec(loadGuestPageFault) || 201 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 202 val exception_pa = pmp.st || pmp.ld || pmp.mmio 203 when (exception_va || exception_pa) { 204 state := s_finish 205 out_valid := true.B 206 atom_override_xtval := true.B 207 }.otherwise { 208 // if sbuffer has been flushed, go to query dcache, otherwise wait for sbuffer. 209 state := Mux(sbuffer_empty, s_cache_req, s_wait_flush_sbuffer_resp); 210 } 211 // update storeAccessFault bit 212 exceptionVec(loadAccessFault) := exceptionVec(loadAccessFault) || (pmp.ld || pmp.mmio) && isLr 213 exceptionVec(storeAccessFault) := exceptionVec(storeAccessFault) || pmp.st || (pmp.ld || pmp.mmio) && !isLr 214 } 215 216 when (state === s_wait_flush_sbuffer_resp) { 217 when (sbuffer_empty) { 218 state := s_cache_req 219 } 220 } 221 222 when (state === s_cache_req) { 223 val pipe_req = io.dcache.req.bits 224 pipe_req := DontCare 225 226 pipe_req.cmd := LookupTree(in.uop.fuOpType, List( 227 LSUOpType.lr_w -> M_XLR, 228 LSUOpType.sc_w -> M_XSC, 229 LSUOpType.amoswap_w -> M_XA_SWAP, 230 LSUOpType.amoadd_w -> M_XA_ADD, 231 LSUOpType.amoxor_w -> M_XA_XOR, 232 LSUOpType.amoand_w -> M_XA_AND, 233 LSUOpType.amoor_w -> M_XA_OR, 234 LSUOpType.amomin_w -> M_XA_MIN, 235 LSUOpType.amomax_w -> M_XA_MAX, 236 LSUOpType.amominu_w -> M_XA_MINU, 237 LSUOpType.amomaxu_w -> M_XA_MAXU, 238 239 LSUOpType.lr_d -> M_XLR, 240 LSUOpType.sc_d -> M_XSC, 241 LSUOpType.amoswap_d -> M_XA_SWAP, 242 LSUOpType.amoadd_d -> M_XA_ADD, 243 LSUOpType.amoxor_d -> M_XA_XOR, 244 LSUOpType.amoand_d -> M_XA_AND, 245 LSUOpType.amoor_d -> M_XA_OR, 246 LSUOpType.amomin_d -> M_XA_MIN, 247 LSUOpType.amomax_d -> M_XA_MAX, 248 LSUOpType.amominu_d -> M_XA_MINU, 249 LSUOpType.amomaxu_d -> M_XA_MAXU 250 )) 251 pipe_req.miss := false.B 252 pipe_req.probe := false.B 253 pipe_req.probe_need_data := false.B 254 pipe_req.source := AMO_SOURCE.U 255 pipe_req.addr := get_block_addr(paddr) 256 pipe_req.vaddr := get_block_addr(in.src(0)) // vaddr 257 pipe_req.word_idx := get_word(paddr) 258 pipe_req.amo_data := genWdata(in.src(1), in.uop.fuOpType(1,0)) 259 pipe_req.amo_mask := genWmask(paddr, in.uop.fuOpType(1,0)) 260 261 io.dcache.req.valid := Mux( 262 io.dcache.req.bits.cmd === M_XLR, 263 !io.dcache.block_lr, // block lr to survive in lr storm 264 data_valid // wait until src(1) is ready 265 ) 266 267 when(io.dcache.req.fire){ 268 state := s_cache_resp 269 paddr_reg := paddr 270 data_reg := io.dcache.req.bits.amo_data 271 mask_reg := io.dcache.req.bits.amo_mask 272 fuop_reg := in.uop.fuOpType 273 } 274 } 275 276 val dcache_resp_data = Reg(UInt()) 277 val dcache_resp_id = Reg(UInt()) 278 val dcache_resp_error = Reg(Bool()) 279 280 when (state === s_cache_resp) { 281 // when not miss 282 // everything is OK, simply send response back to sbuffer 283 // when miss and not replay 284 // wait for missQueue to handling miss and replaying our request 285 // when miss and replay 286 // req missed and fail to enter missQueue, manually replay it later 287 // TODO: add assertions: 288 // 1. add a replay delay counter? 289 // 2. when req gets into MissQueue, it should not miss any more 290 when(io.dcache.resp.fire) { 291 when(io.dcache.resp.bits.miss) { 292 when(io.dcache.resp.bits.replay) { 293 state := s_cache_req 294 } 295 } .otherwise { 296 dcache_resp_data := io.dcache.resp.bits.data 297 dcache_resp_id := io.dcache.resp.bits.id 298 dcache_resp_error := io.dcache.resp.bits.error 299 state := s_cache_resp_latch 300 } 301 } 302 } 303 304 when (state === s_cache_resp_latch) { 305 is_lrsc_valid := dcache_resp_id 306 val rdataSel = LookupTree(paddr(2, 0), List( 307 "b000".U -> dcache_resp_data(63, 0), 308 "b001".U -> dcache_resp_data(63, 8), 309 "b010".U -> dcache_resp_data(63, 16), 310 "b011".U -> dcache_resp_data(63, 24), 311 "b100".U -> dcache_resp_data(63, 32), 312 "b101".U -> dcache_resp_data(63, 40), 313 "b110".U -> dcache_resp_data(63, 48), 314 "b111".U -> dcache_resp_data(63, 56) 315 )) 316 317 resp_data_wire := LookupTree(in.uop.fuOpType, List( 318 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 319 LSUOpType.sc_w -> dcache_resp_data, 320 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 321 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 322 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 323 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 324 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 325 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 326 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 327 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 328 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 329 330 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 331 LSUOpType.sc_d -> dcache_resp_data, 332 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 333 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 334 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 335 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 336 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 337 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 338 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 339 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 340 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 341 )) 342 343 when (dcache_resp_error && io.csrCtrl.cache_error_enable) { 344 exceptionVec(loadAccessFault) := isLr 345 exceptionVec(storeAccessFault) := !isLr 346 assert(!exceptionVec(loadAccessFault)) 347 assert(!exceptionVec(storeAccessFault)) 348 } 349 350 resp_data := resp_data_wire 351 state := s_finish 352 out_valid := true.B 353 } 354 355 io.out.valid := out_valid 356 XSError((state === s_finish) =/= out_valid, "out_valid reg error\n") 357 io.out.bits := DontCare 358 io.out.bits.uop := in.uop 359 io.out.bits.uop.exceptionVec := exceptionVec 360 io.out.bits.data := resp_data 361 io.out.bits.debug.isMMIO := is_mmio 362 io.out.bits.debug.paddr := paddr 363 when (io.out.fire) { 364 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.pc, io.dcache.resp.bits.data) 365 state := s_invalid 366 out_valid := false.B 367 } 368 369 when (state === s_finish) { 370 data_valid := false.B 371 } 372 373 when (io.redirect.valid) { 374 atom_override_xtval := false.B 375 } 376 377 // atomic trigger 378 val csrCtrl = io.csrCtrl 379 val tdata = Reg(Vec(TriggerNum, new MatchTriggerIO)) 380 val tEnableVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) 381 tEnableVec := csrCtrl.mem_trigger.tEnableVec 382 when(csrCtrl.mem_trigger.tUpdate.valid) { 383 tdata(csrCtrl.mem_trigger.tUpdate.bits.addr) := csrCtrl.mem_trigger.tUpdate.bits.tdata 384 } 385 386 val debugMode = csrCtrl.mem_trigger.debugMode 387 val triggerCanRaiseBpExp = csrCtrl.mem_trigger.triggerCanRaiseBpExp 388 val backendTriggerTimingVec = VecInit(tdata.map(_.timing)) 389 val backendTriggerChainVec = VecInit(tdata.map(_.chain)) 390 val backendTriggerHitVec = WireInit(VecInit(Seq.fill(TriggerNum)(false.B))) 391 val backendTriggerCanFireVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) 392 393 when(state === s_cache_req) { 394 // store trigger 395 val store_hit = Wire(Vec(TriggerNum, Bool())) 396 for (j <- 0 until TriggerNum) { 397 store_hit(j) := !tdata(j).select && !debugMode && TriggerCmp( 398 vaddr, 399 tdata(j).tdata2, 400 tdata(j).matchType, 401 tEnableVec(j) && tdata(j).store 402 ) 403 } 404 // load trigger 405 val load_hit = Wire(Vec(TriggerNum, Bool())) 406 for (j <- 0 until TriggerNum) { 407 load_hit(j) := !tdata(j).select && !debugMode && TriggerCmp( 408 vaddr, 409 tdata(j).tdata2, 410 tdata(j).matchType, 411 tEnableVec(j) && tdata(j).load 412 ) 413 } 414 backendTriggerHitVec := store_hit.zip(load_hit).map { case (sh, lh) => sh || lh } 415 // triggerCanFireVec will update at T+1 416 TriggerCheckCanFire(TriggerNum, backendTriggerCanFireVec, backendTriggerHitVec, backendTriggerTimingVec, backendTriggerChainVec) 417 } 418 419 val actionVec = VecInit(tdata.map(_.action)) 420 val triggerAction = Wire(TriggerAction()) 421 TriggerUtil.triggerActionGen(triggerAction, backendTriggerCanFireVec, actionVec, triggerCanRaiseBpExp) 422 423 // addr trigger do cmp at s_cache_req 424 // trigger result is used at s_finish 425 // thus we can delay it safely 426 io.out.bits.uop.exceptionVec(breakPoint) := TriggerAction.isExp(triggerAction) 427 io.out.bits.uop.trigger := triggerAction 428 429 430 if (env.EnableDifftest) { 431 val difftest = DifftestModule(new DiffAtomicEvent) 432 difftest.coreid := io.hartId 433 difftest.valid := state === s_cache_resp_latch 434 difftest.addr := paddr_reg 435 difftest.data := data_reg 436 difftest.mask := mask_reg 437 difftest.fuop := fuop_reg 438 difftest.out := resp_data_wire 439 } 440 441 if (env.EnableDifftest || env.AlwaysBasicDiff) { 442 val uop = io.out.bits.uop 443 val difftest = DifftestModule(new DiffLrScEvent) 444 difftest.coreid := io.hartId 445 difftest.valid := io.out.fire && 446 (uop.fuOpType === LSUOpType.sc_d || uop.fuOpType === LSUOpType.sc_w) 447 difftest.success := is_lrsc_valid 448 } 449} 450