1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache.{DCacheWordIOWithVaddr, MemoryOpConstants} 25import xiangshan.cache.mmu.{TlbRequestIO, TlbCmd} 26import difftest._ 27 28class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 29 val io = IO(new Bundle() { 30 val in = Flipped(Decoupled(new ExuInput)) 31 val storeDataIn = Flipped(Valid(new StoreDataBundle)) // src2 from rs 32 val out = Decoupled(new ExuOutput) 33 val dcache = new DCacheWordIOWithVaddr 34 val dtlb = new TlbRequestIO 35 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 36 val flush_sbuffer = new SbufferFlushBundle 37 val rsFeedback = ValidIO(new RSFeedback) 38 val redirect = Flipped(ValidIO(new Redirect)) 39 val flush = Input(Bool()) 40 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 41 }) 42 43 //------------------------------------------------------- 44 // Atomics Memory Accsess FSM 45 //------------------------------------------------------- 46 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 47 val state = RegInit(s_invalid) 48 val data_valid = RegInit(false.B) 49 val in = Reg(new ExuInput()) 50 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 51 val atom_override_xtval = RegInit(false.B) 52 // paddr after translation 53 val paddr = Reg(UInt()) 54 val is_mmio = Reg(Bool()) 55 // dcache response data 56 val resp_data = Reg(UInt()) 57 val resp_data_wire = WireInit(0.U) 58 val is_lrsc_valid = Reg(Bool()) 59 60 // Difftest signals 61 val paddr_reg = Reg(UInt(64.W)) 62 val data_reg = Reg(UInt(64.W)) 63 val mask_reg = Reg(UInt(8.W)) 64 val fuop_reg = Reg(UInt(8.W)) 65 66 io.exceptionAddr.valid := atom_override_xtval 67 io.exceptionAddr.bits := in.src(0) 68 69 // assign default value to output signals 70 io.in.ready := false.B 71 io.out.valid := false.B 72 io.out.bits := DontCare 73 74 io.dcache.req.valid := false.B 75 io.dcache.req.bits := DontCare 76 io.dcache.resp.ready := false.B 77 78 io.dtlb.req.valid := false.B 79 io.dtlb.req.bits := DontCare 80 io.dtlb.resp.ready := false.B 81 82 io.flush_sbuffer.valid := false.B 83 84 XSDebug("state: %d\n", state) 85 86 when (state === s_invalid) { 87 io.in.ready := true.B 88 when (io.in.fire()) { 89 in := io.in.bits 90 in.src(1) := in.src(1) // leave src2 unchanged 91 state := s_tlb 92 } 93 } 94 95 when (io.storeDataIn.fire()) { 96 in.src(1) := io.storeDataIn.bits.data 97 data_valid := true.B 98 } 99 100 assert(!(io.storeDataIn.fire() && data_valid), "atomic unit re-receive data") 101 102 // Send TLB feedback to store issue queue 103 // we send feedback right after we receives request 104 // also, we always treat amo as tlb hit 105 // since we will continue polling tlb all by ourself 106 io.rsFeedback.valid := RegNext(RegNext(io.in.valid)) 107 io.rsFeedback.bits.hit := true.B 108 io.rsFeedback.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 109 io.rsFeedback.bits.flushState := DontCare 110 io.rsFeedback.bits.sourceType := DontCare 111 112 // tlb translation, manipulating signals && deal with exception 113 when (state === s_tlb) { 114 // send req to dtlb 115 // keep firing until tlb hit 116 io.dtlb.req.valid := true.B 117 io.dtlb.req.bits.vaddr := in.src(0) 118 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 119 io.dtlb.resp.ready := true.B 120 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 121 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 122 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 123 io.dtlb.req.bits.debug.isFirstIssue := false.B 124 125 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 126 // exception handling 127 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 128 "b00".U -> true.B, //b 129 "b01".U -> (in.src(0)(0) === 0.U), //h 130 "b10".U -> (in.src(0)(1,0) === 0.U), //w 131 "b11".U -> (in.src(0)(2,0) === 0.U) //d 132 )) 133 exceptionVec(storeAddrMisaligned) := !addrAligned 134 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 135 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 136 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 137 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 138 val exception = !addrAligned || 139 io.dtlb.resp.bits.excp.pf.st || 140 io.dtlb.resp.bits.excp.pf.ld || 141 io.dtlb.resp.bits.excp.af.st || 142 io.dtlb.resp.bits.excp.af.ld 143 is_mmio := io.dtlb.resp.bits.mmio 144 when (exception) { 145 // check for exceptions 146 // if there are exceptions, no need to execute it 147 state := s_finish 148 atom_override_xtval := true.B 149 } .otherwise { 150 paddr := io.dtlb.resp.bits.paddr 151 state := s_flush_sbuffer_req 152 } 153 } 154 } 155 156 157 when (state === s_flush_sbuffer_req) { 158 io.flush_sbuffer.valid := true.B 159 state := s_flush_sbuffer_resp 160 } 161 162 when (state === s_flush_sbuffer_resp) { 163 when (io.flush_sbuffer.empty) { 164 state := s_cache_req 165 } 166 } 167 168 when (state === s_cache_req) { 169 io.dcache.req.valid := true.B 170 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 171 LSUOpType.lr_w -> M_XLR, 172 LSUOpType.sc_w -> M_XSC, 173 LSUOpType.amoswap_w -> M_XA_SWAP, 174 LSUOpType.amoadd_w -> M_XA_ADD, 175 LSUOpType.amoxor_w -> M_XA_XOR, 176 LSUOpType.amoand_w -> M_XA_AND, 177 LSUOpType.amoor_w -> M_XA_OR, 178 LSUOpType.amomin_w -> M_XA_MIN, 179 LSUOpType.amomax_w -> M_XA_MAX, 180 LSUOpType.amominu_w -> M_XA_MINU, 181 LSUOpType.amomaxu_w -> M_XA_MAXU, 182 183 LSUOpType.lr_d -> M_XLR, 184 LSUOpType.sc_d -> M_XSC, 185 LSUOpType.amoswap_d -> M_XA_SWAP, 186 LSUOpType.amoadd_d -> M_XA_ADD, 187 LSUOpType.amoxor_d -> M_XA_XOR, 188 LSUOpType.amoand_d -> M_XA_AND, 189 LSUOpType.amoor_d -> M_XA_OR, 190 LSUOpType.amomin_d -> M_XA_MIN, 191 LSUOpType.amomax_d -> M_XA_MAX, 192 LSUOpType.amominu_d -> M_XA_MINU, 193 LSUOpType.amomaxu_d -> M_XA_MAXU 194 )) 195 196 io.dcache.req.bits.addr := paddr 197 io.dcache.req.bits.vaddr := in.src(0) // vaddr 198 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 199 // TODO: atomics do need mask: fix mask 200 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 201 io.dcache.req.bits.id := DontCare 202 203 when(io.dcache.req.fire()){ 204 state := s_cache_resp 205 paddr_reg := io.dcache.req.bits.addr 206 data_reg := io.dcache.req.bits.data 207 mask_reg := io.dcache.req.bits.mask 208 fuop_reg := in.uop.ctrl.fuOpType 209 } 210 } 211 212 when (state === s_cache_resp) { 213 io.dcache.resp.ready := data_valid 214 when(io.dcache.resp.fire()) { 215 is_lrsc_valid := io.dcache.resp.bits.id 216 val rdata = io.dcache.resp.bits.data 217 val rdataSel = LookupTree(paddr(2, 0), List( 218 "b000".U -> rdata(63, 0), 219 "b001".U -> rdata(63, 8), 220 "b010".U -> rdata(63, 16), 221 "b011".U -> rdata(63, 24), 222 "b100".U -> rdata(63, 32), 223 "b101".U -> rdata(63, 40), 224 "b110".U -> rdata(63, 48), 225 "b111".U -> rdata(63, 56) 226 )) 227 228 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 229 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 230 LSUOpType.sc_w -> rdata, 231 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 232 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 233 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 234 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 235 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 236 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 237 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 238 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 239 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 240 241 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 242 LSUOpType.sc_d -> rdata, 243 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 244 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 245 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 246 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 247 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 248 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 249 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 250 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 251 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 252 )) 253 254 resp_data := resp_data_wire 255 state := s_finish 256 } 257 } 258 259 when (state === s_finish) { 260 io.out.valid := true.B 261 io.out.bits.uop := in.uop 262 io.out.bits.uop.cf.exceptionVec := exceptionVec 263 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 264 io.out.bits.data := resp_data 265 io.out.bits.redirectValid := false.B 266 io.out.bits.redirect := DontCare 267 io.out.bits.debug.isMMIO := is_mmio 268 io.out.bits.debug.paddr := paddr 269 when (io.out.fire()) { 270 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 271 state := s_invalid 272 } 273 data_valid := false.B 274 } 275 276 when(io.redirect.valid || io.flush){ 277 atom_override_xtval := false.B 278 } 279 280 if (!env.FPGAPlatform) { 281 val difftest = Module(new DifftestAtomicEvent) 282 difftest.io.clock := clock 283 difftest.io.coreid := hardId.U 284 difftest.io.atomicResp := io.dcache.resp.fire() 285 difftest.io.atomicAddr := paddr_reg 286 difftest.io.atomicData := data_reg 287 difftest.io.atomicMask := mask_reg 288 difftest.io.atomicFuop := fuop_reg 289 difftest.io.atomicOut := resp_data_wire 290 } 291} 292