1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache.{DCacheWordIO, TlbRequestIO, TlbCmd, MemoryOpConstants} 8import xiangshan.backend.LSUOpType 9 10class AtomicsUnit extends XSModule with MemoryOpConstants{ 11 val io = IO(new Bundle() { 12 val in = Flipped(Decoupled(new ExuInput)) 13 val out = Decoupled(new ExuOutput) 14 val dcache = new DCacheWordIO 15 val dtlb = new TlbRequestIO 16 val flush_sbuffer = new SbufferFlushBundle 17 val tlbFeedback = ValidIO(new TlbFeedback) 18 val redirect = Flipped(ValidIO(new Redirect)) 19 val flush = Input(Bool()) 20 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 21 }) 22 23 //------------------------------------------------------- 24 // Atomics Memory Accsess FSM 25 //------------------------------------------------------- 26 val s_invalid :: s_tlb :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(7) 27 val state = RegInit(s_invalid) 28 val in = Reg(new ExuInput()) 29 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 30 val atom_override_xtval = RegInit(false.B) 31 // paddr after translation 32 val paddr = Reg(UInt()) 33 val is_mmio = Reg(Bool()) 34 // dcache response data 35 val resp_data = Reg(UInt()) 36 val is_lrsc_valid = Reg(Bool()) 37 38 io.exceptionAddr.valid := atom_override_xtval 39 io.exceptionAddr.bits := in.src1 40 41 // assign default value to output signals 42 io.in.ready := false.B 43 io.out.valid := false.B 44 io.out.bits := DontCare 45 46 io.dcache.req.valid := false.B 47 io.dcache.req.bits := DontCare 48 io.dcache.resp.ready := false.B 49 50 io.dtlb.req.valid := false.B 51 io.dtlb.req.bits := DontCare 52 io.dtlb.resp.ready := false.B 53 54 io.flush_sbuffer.valid := false.B 55 56 XSDebug("state: %d\n", state) 57 58 when (state === s_invalid) { 59 io.in.ready := true.B 60 when (io.in.fire()) { 61 in := io.in.bits 62 state := s_tlb 63 } 64 } 65 66 // Send TLB feedback to store issue queue 67 // we send feedback right after we receives request 68 // also, we always treat amo as tlb hit 69 // since we will continue polling tlb all by ourself 70 io.tlbFeedback.valid := RegNext(RegNext(io.in.valid)) 71 io.tlbFeedback.bits.hit := true.B 72 io.tlbFeedback.bits.roqIdx := in.uop.roqIdx 73 74 // tlb translation, manipulating signals && deal with exception 75 when (state === s_tlb) { 76 // send req to dtlb 77 // keep firing until tlb hit 78 io.dtlb.req.valid := true.B 79 io.dtlb.req.bits.vaddr := in.src1 80 io.dtlb.req.bits.roqIdx := in.uop.roqIdx 81 io.dtlb.resp.ready := true.B 82 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 83 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 84 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 85 86 when(io.dtlb.resp.fire && !io.dtlb.resp.bits.miss){ 87 // exception handling 88 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 89 "b00".U -> true.B, //b 90 "b01".U -> (in.src1(0) === 0.U), //h 91 "b10".U -> (in.src1(1,0) === 0.U), //w 92 "b11".U -> (in.src1(2,0) === 0.U) //d 93 )) 94 exceptionVec(storeAddrMisaligned) := !addrAligned 95 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 96 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 97 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 98 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 99 val exception = !addrAligned || 100 io.dtlb.resp.bits.excp.pf.st || 101 io.dtlb.resp.bits.excp.pf.ld || 102 io.dtlb.resp.bits.excp.af.st || 103 io.dtlb.resp.bits.excp.af.ld 104 is_mmio := io.dtlb.resp.bits.mmio 105 when (exception) { 106 // check for exceptions 107 // if there are exceptions, no need to execute it 108 state := s_finish 109 atom_override_xtval := true.B 110 } .otherwise { 111 paddr := io.dtlb.resp.bits.paddr 112 state := s_flush_sbuffer_req 113 } 114 } 115 } 116 117 118 when (state === s_flush_sbuffer_req) { 119 io.flush_sbuffer.valid := true.B 120 state := s_flush_sbuffer_resp 121 } 122 123 when (state === s_flush_sbuffer_resp) { 124 when (io.flush_sbuffer.empty) { 125 state := s_cache_req 126 } 127 } 128 129 when (state === s_cache_req) { 130 io.dcache.req.valid := true.B 131 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 132 LSUOpType.lr_w -> M_XLR, 133 LSUOpType.sc_w -> M_XSC, 134 LSUOpType.amoswap_w -> M_XA_SWAP, 135 LSUOpType.amoadd_w -> M_XA_ADD, 136 LSUOpType.amoxor_w -> M_XA_XOR, 137 LSUOpType.amoand_w -> M_XA_AND, 138 LSUOpType.amoor_w -> M_XA_OR, 139 LSUOpType.amomin_w -> M_XA_MIN, 140 LSUOpType.amomax_w -> M_XA_MAX, 141 LSUOpType.amominu_w -> M_XA_MINU, 142 LSUOpType.amomaxu_w -> M_XA_MAXU, 143 144 LSUOpType.lr_d -> M_XLR, 145 LSUOpType.sc_d -> M_XSC, 146 LSUOpType.amoswap_d -> M_XA_SWAP, 147 LSUOpType.amoadd_d -> M_XA_ADD, 148 LSUOpType.amoxor_d -> M_XA_XOR, 149 LSUOpType.amoand_d -> M_XA_AND, 150 LSUOpType.amoor_d -> M_XA_OR, 151 LSUOpType.amomin_d -> M_XA_MIN, 152 LSUOpType.amomax_d -> M_XA_MAX, 153 LSUOpType.amominu_d -> M_XA_MINU, 154 LSUOpType.amomaxu_d -> M_XA_MAXU 155 )) 156 157 io.dcache.req.bits.addr := paddr 158 io.dcache.req.bits.data := genWdata(in.src2, in.uop.ctrl.fuOpType(1,0)) 159 // TODO: atomics do need mask: fix mask 160 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 161 io.dcache.req.bits.meta.id := DontCare 162 io.dcache.req.bits.meta.paddr := paddr 163 io.dcache.req.bits.meta.tlb_miss := false.B 164 io.dcache.req.bits.meta.replay := false.B 165 166 when(io.dcache.req.fire()){ 167 state := s_cache_resp 168 } 169 } 170 171 when (state === s_cache_resp) { 172 io.dcache.resp.ready := true.B 173 when(io.dcache.resp.fire()) { 174 is_lrsc_valid := io.dcache.resp.bits.meta.id 175 val rdata = io.dcache.resp.bits.data 176 val rdataSel = LookupTree(paddr(2, 0), List( 177 "b000".U -> rdata(63, 0), 178 "b001".U -> rdata(63, 8), 179 "b010".U -> rdata(63, 16), 180 "b011".U -> rdata(63, 24), 181 "b100".U -> rdata(63, 32), 182 "b101".U -> rdata(63, 40), 183 "b110".U -> rdata(63, 48), 184 "b111".U -> rdata(63, 56) 185 )) 186 187 resp_data := LookupTree(in.uop.ctrl.fuOpType, List( 188 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 189 LSUOpType.sc_w -> rdata, 190 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 191 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 192 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 193 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 194 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 195 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 196 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 197 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 198 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 199 200 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 201 LSUOpType.sc_d -> rdata, 202 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 203 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 204 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 205 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 206 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 207 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 208 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 209 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 210 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 211 )) 212 213 state := s_finish 214 } 215 } 216 217 when (state === s_finish) { 218 io.out.valid := true.B 219 io.out.bits.uop := in.uop 220 io.out.bits.uop.cf.exceptionVec := exceptionVec 221 io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid 222 io.out.bits.data := resp_data 223 io.out.bits.redirectValid := false.B 224 io.out.bits.redirect := DontCare 225 io.out.bits.debug.isMMIO := is_mmio 226 when (io.out.fire()) { 227 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 228 state := s_invalid 229 } 230 } 231 232 when(io.redirect.valid || io.flush){ 233 atom_override_xtval := false.B 234 } 235}