1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache.{AtomicWordIO, MemoryOpConstants} 25import xiangshan.cache.mmu.{TlbCmd, TlbRequestIO} 26import difftest._ 27import xiangshan.ExceptionNO._ 28import xiangshan.backend.fu.PMPRespBundle 29 30class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstants{ 31 val io = IO(new Bundle() { 32 val hartId = Input(UInt(8.W)) 33 val in = Flipped(Decoupled(new ExuInput)) 34 val storeDataIn = Flipped(Valid(new ExuOutput)) // src2 from rs 35 val out = Decoupled(new ExuOutput) 36 val dcache = new AtomicWordIO 37 val dtlb = new TlbRequestIO 38 val pmpResp = Flipped(new PMPRespBundle()) 39 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 40 val flush_sbuffer = new SbufferFlushBundle 41 val feedbackSlow = ValidIO(new RSFeedback) 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val exceptionAddr = ValidIO(UInt(VAddrBits.W)) 44 val csrCtrl = Flipped(new CustomCSRCtrlIO) 45 }) 46 47 //------------------------------------------------------- 48 // Atomics Memory Accsess FSM 49 //------------------------------------------------------- 50 val s_invalid :: s_tlb :: s_pm :: s_flush_sbuffer_req :: s_flush_sbuffer_resp :: s_cache_req :: s_cache_resp :: s_finish :: Nil = Enum(8) 51 val state = RegInit(s_invalid) 52 val out_valid = RegInit(false.B) 53 val data_valid = RegInit(false.B) 54 val in = Reg(new ExuInput()) 55 val exceptionVec = RegInit(0.U.asTypeOf(ExceptionVec())) 56 val atom_override_xtval = RegInit(false.B) 57 val isLr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 58 // paddr after translation 59 val paddr = Reg(UInt()) 60 val vaddr = in.src(0) 61 val is_mmio = Reg(Bool()) 62 // pmp check 63 val static_pm = Reg(Valid(Bool())) // valid for static, bits for mmio 64 // dcache response data 65 val resp_data = Reg(UInt()) 66 val resp_data_wire = WireInit(0.U) 67 val is_lrsc_valid = Reg(Bool()) 68 69 70 // Difftest signals 71 val paddr_reg = Reg(UInt(64.W)) 72 val data_reg = Reg(UInt(64.W)) 73 val mask_reg = Reg(UInt(8.W)) 74 val fuop_reg = Reg(UInt(8.W)) 75 76 io.exceptionAddr.valid := atom_override_xtval 77 io.exceptionAddr.bits := in.src(0) 78 79 // assign default value to output signals 80 io.in.ready := false.B 81 82 io.dcache.req.valid := false.B 83 io.dcache.req.bits := DontCare 84 io.dcache.resp.ready := false.B 85 86 io.dtlb.req.valid := false.B 87 io.dtlb.req.bits := DontCare 88 io.dtlb.resp.ready := true.B 89 90 io.flush_sbuffer.valid := false.B 91 92 XSDebug("state: %d\n", state) 93 94 when (state === s_invalid) { 95 io.in.ready := true.B 96 when (io.in.fire) { 97 in := io.in.bits 98 in.src(1) := in.src(1) // leave src2 unchanged 99 state := s_tlb 100 } 101 } 102 103 when (io.storeDataIn.fire) { 104 in.src(1) := io.storeDataIn.bits.data 105 data_valid := true.B 106 } 107 108 assert(!(io.storeDataIn.fire && data_valid), "atomic unit re-receive data") 109 110 // Send TLB feedback to store issue queue 111 // we send feedback right after we receives request 112 // also, we always treat amo as tlb hit 113 // since we will continue polling tlb all by ourself 114 io.feedbackSlow.valid := RegNext(RegNext(io.in.valid)) 115 io.feedbackSlow.bits.hit := true.B 116 io.feedbackSlow.bits.rsIdx := RegEnable(io.rsIdx, io.in.valid) 117 io.feedbackSlow.bits.flushState := DontCare 118 io.feedbackSlow.bits.sourceType := DontCare 119 io.feedbackSlow.bits.dataInvalidSqIdx := DontCare 120 121 // tlb translation, manipulating signals && deal with exception 122 when (state === s_tlb) { 123 // send req to dtlb 124 // keep firing until tlb hit 125 io.dtlb.req.valid := true.B 126 io.dtlb.req.bits.vaddr := in.src(0) 127 val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d 128 io.dtlb.req.bits.cmd := Mux(is_lr, TlbCmd.atom_read, TlbCmd.atom_write) 129 io.dtlb.req.bits.debug.robIdx := in.uop.robIdx 130 io.dtlb.req.bits.debug.pc := in.uop.cf.pc 131 io.dtlb.req.bits.debug.isFirstIssue := false.B 132 133 when(io.dtlb.resp.fire){ 134 paddr := io.dtlb.resp.bits.paddr 135 // exception handling 136 val addrAligned = LookupTree(in.uop.ctrl.fuOpType(1,0), List( 137 "b00".U -> true.B, //b 138 "b01".U -> (in.src(0)(0) === 0.U), //h 139 "b10".U -> (in.src(0)(1,0) === 0.U), //w 140 "b11".U -> (in.src(0)(2,0) === 0.U) //d 141 )) 142 exceptionVec(storeAddrMisaligned) := !addrAligned 143 exceptionVec(storePageFault) := io.dtlb.resp.bits.excp.pf.st 144 exceptionVec(loadPageFault) := io.dtlb.resp.bits.excp.pf.ld 145 exceptionVec(storeAccessFault) := io.dtlb.resp.bits.excp.af.st 146 exceptionVec(loadAccessFault) := io.dtlb.resp.bits.excp.af.ld 147 static_pm := io.dtlb.resp.bits.static_pm 148 149 when (!io.dtlb.resp.bits.miss) { 150 when (!addrAligned) { 151 // NOTE: when addrAligned, do not need to wait tlb actually 152 // check for miss aligned exceptions, tlb exception are checked next cycle for timing 153 // if there are exceptions, no need to execute it 154 state := s_finish 155 out_valid := true.B 156 atom_override_xtval := true.B 157 } .otherwise { 158 state := s_pm 159 } 160 } 161 } 162 } 163 164 when (state === s_pm) { 165 val pmp = WireInit(io.pmpResp) 166 when (static_pm.valid) { 167 pmp.ld := false.B 168 pmp.st := false.B 169 pmp.instr := false.B 170 pmp.mmio := static_pm.bits 171 } 172 is_mmio := pmp.mmio 173 // NOTE: only handle load/store exception here, if other exception happens, don't send here 174 val exception_va = exceptionVec(storePageFault) || exceptionVec(loadPageFault) || 175 exceptionVec(storeAccessFault) || exceptionVec(loadAccessFault) 176 val exception_pa = pmp.st 177 when (exception_va || exception_pa) { 178 state := s_finish 179 out_valid := true.B 180 atom_override_xtval := true.B 181 }.otherwise { 182 state := s_flush_sbuffer_req 183 } 184 } 185 186 when (state === s_flush_sbuffer_req) { 187 io.flush_sbuffer.valid := true.B 188 state := s_flush_sbuffer_resp 189 } 190 191 when (state === s_flush_sbuffer_resp) { 192 when (io.flush_sbuffer.empty) { 193 state := s_cache_req 194 } 195 } 196 197 when (state === s_cache_req) { 198 io.dcache.req.valid := true.B 199 io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List( 200 LSUOpType.lr_w -> M_XLR, 201 LSUOpType.sc_w -> M_XSC, 202 LSUOpType.amoswap_w -> M_XA_SWAP, 203 LSUOpType.amoadd_w -> M_XA_ADD, 204 LSUOpType.amoxor_w -> M_XA_XOR, 205 LSUOpType.amoand_w -> M_XA_AND, 206 LSUOpType.amoor_w -> M_XA_OR, 207 LSUOpType.amomin_w -> M_XA_MIN, 208 LSUOpType.amomax_w -> M_XA_MAX, 209 LSUOpType.amominu_w -> M_XA_MINU, 210 LSUOpType.amomaxu_w -> M_XA_MAXU, 211 212 LSUOpType.lr_d -> M_XLR, 213 LSUOpType.sc_d -> M_XSC, 214 LSUOpType.amoswap_d -> M_XA_SWAP, 215 LSUOpType.amoadd_d -> M_XA_ADD, 216 LSUOpType.amoxor_d -> M_XA_XOR, 217 LSUOpType.amoand_d -> M_XA_AND, 218 LSUOpType.amoor_d -> M_XA_OR, 219 LSUOpType.amomin_d -> M_XA_MIN, 220 LSUOpType.amomax_d -> M_XA_MAX, 221 LSUOpType.amominu_d -> M_XA_MINU, 222 LSUOpType.amomaxu_d -> M_XA_MAXU 223 )) 224 225 io.dcache.req.bits.addr := paddr 226 io.dcache.req.bits.vaddr := in.src(0) // vaddr 227 io.dcache.req.bits.data := genWdata(in.src(1), in.uop.ctrl.fuOpType(1,0)) 228 // TODO: atomics do need mask: fix mask 229 io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0)) 230 io.dcache.req.bits.id := DontCare 231 232 when(io.dcache.req.fire){ 233 state := s_cache_resp 234 paddr_reg := io.dcache.req.bits.addr 235 data_reg := io.dcache.req.bits.data 236 mask_reg := io.dcache.req.bits.mask 237 fuop_reg := in.uop.ctrl.fuOpType 238 } 239 } 240 241 when (state === s_cache_resp) { 242 io.dcache.resp.ready := data_valid 243 when(io.dcache.resp.fire) { 244 is_lrsc_valid := io.dcache.resp.bits.id 245 val rdata = io.dcache.resp.bits.data 246 val rdataSel = LookupTree(paddr(2, 0), List( 247 "b000".U -> rdata(63, 0), 248 "b001".U -> rdata(63, 8), 249 "b010".U -> rdata(63, 16), 250 "b011".U -> rdata(63, 24), 251 "b100".U -> rdata(63, 32), 252 "b101".U -> rdata(63, 40), 253 "b110".U -> rdata(63, 48), 254 "b111".U -> rdata(63, 56) 255 )) 256 257 resp_data_wire := LookupTree(in.uop.ctrl.fuOpType, List( 258 LSUOpType.lr_w -> SignExt(rdataSel(31, 0), XLEN), 259 LSUOpType.sc_w -> rdata, 260 LSUOpType.amoswap_w -> SignExt(rdataSel(31, 0), XLEN), 261 LSUOpType.amoadd_w -> SignExt(rdataSel(31, 0), XLEN), 262 LSUOpType.amoxor_w -> SignExt(rdataSel(31, 0), XLEN), 263 LSUOpType.amoand_w -> SignExt(rdataSel(31, 0), XLEN), 264 LSUOpType.amoor_w -> SignExt(rdataSel(31, 0), XLEN), 265 LSUOpType.amomin_w -> SignExt(rdataSel(31, 0), XLEN), 266 LSUOpType.amomax_w -> SignExt(rdataSel(31, 0), XLEN), 267 LSUOpType.amominu_w -> SignExt(rdataSel(31, 0), XLEN), 268 LSUOpType.amomaxu_w -> SignExt(rdataSel(31, 0), XLEN), 269 270 LSUOpType.lr_d -> SignExt(rdataSel(63, 0), XLEN), 271 LSUOpType.sc_d -> rdata, 272 LSUOpType.amoswap_d -> SignExt(rdataSel(63, 0), XLEN), 273 LSUOpType.amoadd_d -> SignExt(rdataSel(63, 0), XLEN), 274 LSUOpType.amoxor_d -> SignExt(rdataSel(63, 0), XLEN), 275 LSUOpType.amoand_d -> SignExt(rdataSel(63, 0), XLEN), 276 LSUOpType.amoor_d -> SignExt(rdataSel(63, 0), XLEN), 277 LSUOpType.amomin_d -> SignExt(rdataSel(63, 0), XLEN), 278 LSUOpType.amomax_d -> SignExt(rdataSel(63, 0), XLEN), 279 LSUOpType.amominu_d -> SignExt(rdataSel(63, 0), XLEN), 280 LSUOpType.amomaxu_d -> SignExt(rdataSel(63, 0), XLEN) 281 )) 282 283 when (io.dcache.resp.bits.error && io.csrCtrl.cache_error_enable) { 284 exceptionVec(loadAccessFault) := isLr 285 exceptionVec(storeAccessFault) := !isLr 286 assert(!exceptionVec(loadAccessFault)) 287 assert(!exceptionVec(storeAccessFault)) 288 } 289 290 resp_data := resp_data_wire 291 state := s_finish 292 out_valid := true.B 293 } 294 } 295 296 io.out.valid := out_valid 297 XSError((state === s_finish) =/= out_valid, "out_valid reg error\n") 298 io.out.bits := DontCare 299 io.out.bits.uop := in.uop 300 io.out.bits.uop.cf.exceptionVec := exceptionVec 301 io.out.bits.data := resp_data 302 io.out.bits.redirectValid := false.B 303 io.out.bits.debug.isMMIO := is_mmio 304 io.out.bits.debug.paddr := paddr 305 when (io.out.fire) { 306 XSDebug("atomics writeback: pc %x data %x\n", io.out.bits.uop.cf.pc, io.dcache.resp.bits.data) 307 state := s_invalid 308 out_valid := false.B 309 } 310 311 when (state === s_finish) { 312 data_valid := false.B 313 } 314 315 when (io.redirect.valid) { 316 atom_override_xtval := false.B 317 } 318 319 // atomic trigger 320 val csrCtrl = io.csrCtrl 321 val tdata = Reg(Vec(6, new MatchTriggerIO)) 322 val tEnable = RegInit(VecInit(Seq.fill(6)(false.B))) 323 val en = csrCtrl.trigger_enable 324 tEnable := VecInit(en(2), en (3), en(7), en(4), en(5), en(9)) 325 when(csrCtrl.mem_trigger.t.valid) { 326 tdata(csrCtrl.mem_trigger.t.bits.addr) := csrCtrl.mem_trigger.t.bits.tdata 327 } 328 val lTriggerMapping = Map(0 -> 2, 1 -> 3, 2 -> 5) 329 val sTriggerMapping = Map(0 -> 0, 1 -> 1, 2 -> 4) 330 331 val backendTriggerHitReg = Reg(Vec(6, Bool())) 332 backendTriggerHitReg := VecInit(Seq.fill(6)(false.B)) 333 334 when(state === s_cache_req){ 335 // store trigger 336 val store_hit = Wire(Vec(3, Bool())) 337 for (j <- 0 until 3) { 338 store_hit(j) := !tdata(sTriggerMapping(j)).select && TriggerCmp( 339 vaddr, 340 tdata(sTriggerMapping(j)).tdata2, 341 tdata(sTriggerMapping(j)).matchType, 342 tEnable(sTriggerMapping(j)) 343 ) 344 backendTriggerHitReg(sTriggerMapping(j)) := store_hit(j) 345 } 346 347 when(tdata(0).chain) { 348 backendTriggerHitReg(0) := store_hit(0) && store_hit(1) 349 backendTriggerHitReg(1) := store_hit(0) && store_hit(1) 350 } 351 352 when(!in.uop.cf.trigger.backendEn(0)) { 353 backendTriggerHitReg(4) := false.B 354 } 355 356 // load trigger 357 val load_hit = Wire(Vec(3, Bool())) 358 for (j <- 0 until 3) { 359 360 val addrHit = TriggerCmp( 361 vaddr, 362 tdata(lTriggerMapping(j)).tdata2, 363 tdata(lTriggerMapping(j)).matchType, 364 tEnable(lTriggerMapping(j)) 365 ) 366 load_hit(j) := addrHit && !tdata(lTriggerMapping(j)).select 367 backendTriggerHitReg(lTriggerMapping(j)) := load_hit(j) 368 } 369 when(tdata(2).chain) { 370 backendTriggerHitReg(2) := load_hit(0) && load_hit(1) 371 backendTriggerHitReg(3) := load_hit(0) && load_hit(1) 372 } 373 when(!in.uop.cf.trigger.backendEn(1)) { 374 backendTriggerHitReg(5) := false.B 375 } 376 } 377 378 // addr trigger do cmp at s_cache_req 379 // trigger result is used at s_finish 380 // thus we can delay it safely 381 io.out.bits.uop.cf.trigger.backendHit := VecInit(Seq.fill(6)(false.B)) 382 when(isLr){ 383 // enable load trigger 384 io.out.bits.uop.cf.trigger.backendHit(2) := backendTriggerHitReg(2) 385 io.out.bits.uop.cf.trigger.backendHit(3) := backendTriggerHitReg(3) 386 io.out.bits.uop.cf.trigger.backendHit(5) := backendTriggerHitReg(5) 387 }.otherwise{ 388 // enable store trigger 389 io.out.bits.uop.cf.trigger.backendHit(0) := backendTriggerHitReg(0) 390 io.out.bits.uop.cf.trigger.backendHit(1) := backendTriggerHitReg(1) 391 io.out.bits.uop.cf.trigger.backendHit(4) := backendTriggerHitReg(4) 392 } 393 394 if (env.EnableDifftest) { 395 val difftest = Module(new DifftestAtomicEvent) 396 difftest.io.clock := clock 397 difftest.io.coreid := io.hartId 398 difftest.io.atomicResp := io.dcache.resp.fire 399 difftest.io.atomicAddr := paddr_reg 400 difftest.io.atomicData := data_reg 401 difftest.io.atomicMask := mask_reg 402 difftest.io.atomicFuop := fuop_reg 403 difftest.io.atomicOut := resp_data_wire 404 } 405 406 if (env.EnableDifftest || env.AlwaysBasicDiff) { 407 val uop = io.out.bits.uop 408 val difftest = Module(new DifftestLrScEvent) 409 difftest.io.clock := clock 410 difftest.io.coreid := io.hartId 411 difftest.io.valid := io.out.fire && 412 (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w) 413 difftest.io.success := is_lrsc_valid 414 } 415} 416