xref: /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala (revision 57bb43b5f11c3f1e89ac52f232fe73056b35d9bd) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem.mdp
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import utils._
24
25// 21264-like wait table, uses 2-bit counter
26class WaitTable(implicit p: Parameters) extends XSModule {
27  val io = IO(new Bundle {
28    // to decode
29    val raddr = Vec(DecodeWidth, Input(UInt(MemPredPCWidth.W))) // decode pc(VaddrBits-1, 1)
30    val rdata = Vec(DecodeWidth, Output(Bool())) // loadWaitBit
31    val update = Input(new MemPredUpdateReq) // RegNext should be added outside
32    val csrCtrl = Input(new CustomCSRCtrlIO)
33  })
34
35  require(DecodeWidth == RenameWidth)
36
37  val data = RegInit(VecInit(Seq.fill(WaitTableSize)(0.U(2.W))))
38  val resetCounter = RegInit(0.U(ResetTimeMax2Pow.W))
39  resetCounter := resetCounter + 1.U
40
41  // read ports
42  for (i <- 0 until DecodeWidth) {
43    io.rdata(i) := (data(io.raddr(i))(LWTUse2BitCounter.B.asUInt) || io.csrCtrl.no_spec_load) && !io.csrCtrl.lvpred_disable
44  }
45
46  // write port
47  when(io.update.valid){
48    data(io.update.waddr) := Cat(data(io.update.waddr)(0), true.B)
49  }
50
51  // reset period: ResetTimeMax2Pow
52  when(resetCounter(ResetTimeMax2Pow-1, ResetTimeMin2Pow)(RegNext(io.csrCtrl.lvpred_timeout))) {
53    for (j <- 0 until WaitTableSize) {
54      data(j) := 0.U
55    }
56    resetCounter:= 0.U
57  }
58
59  // debug
60  when (io.update.valid) {
61    XSDebug("%d: waittable update: pc %x data: %x\n", GTimer(), io.update.waddr, io.update.wdata)
62  }
63
64  XSPerfAccumulate("wait_table_bit_set", PopCount(data.map(d => d(1))))
65}
66