1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend._ 26import xiangshan.backend.fu.fpu._ 27import xiangshan.backend.rob.RobLsqIO 28import xiangshan.cache._ 29import xiangshan.cache.mmu._ 30import xiangshan.frontend.FtqPtr 31import xiangshan.ExceptionNO._ 32import xiangshan.mem.mdp._ 33import xiangshan.backend.Bundles.{DynInst, MemExuOutput, MemMicroOpRbExt} 34import xiangshan.backend.rob.RobPtr 35 36class LqPtr(implicit p: Parameters) extends CircularQueuePtr[LqPtr]( 37 p => p(XSCoreParamsKey).VirtualLoadQueueSize 38){ 39} 40 41object LqPtr { 42 def apply(f: Bool, v: UInt)(implicit p: Parameters): LqPtr = { 43 val ptr = Wire(new LqPtr) 44 ptr.flag := f 45 ptr.value := v 46 ptr 47 } 48} 49 50trait HasLoadHelper { this: XSModule => 51 def rdataHelper(uop: DynInst, rdata: UInt): UInt = { 52 val fpWen = uop.fpWen 53 LookupTree(uop.fuOpType, List( 54 LSUOpType.lb -> SignExt(rdata(7, 0) , XLEN), 55 LSUOpType.lh -> SignExt(rdata(15, 0), XLEN), 56 /* 57 riscv-spec-20191213: 12.2 NaN Boxing of Narrower Values 58 Any operation that writes a narrower result to an f register must write 59 all 1s to the uppermost FLEN−n bits to yield a legal NaN-boxed value. 60 */ 61 LSUOpType.lw -> Mux(fpWen, FPU.box(rdata, FPU.S), SignExt(rdata(31, 0), XLEN)), 62 LSUOpType.ld -> Mux(fpWen, FPU.box(rdata, FPU.D), SignExt(rdata(63, 0), XLEN)), 63 LSUOpType.lbu -> ZeroExt(rdata(7, 0) , XLEN), 64 LSUOpType.lhu -> ZeroExt(rdata(15, 0), XLEN), 65 LSUOpType.lwu -> ZeroExt(rdata(31, 0), XLEN), 66 67 // hypervisor 68 LSUOpType.hlvb -> SignExt(rdata(7, 0), XLEN), 69 LSUOpType.hlvh -> SignExt(rdata(15, 0), XLEN), 70 LSUOpType.hlvw -> SignExt(rdata(31, 0), XLEN), 71 LSUOpType.hlvd -> SignExt(rdata(63, 0), XLEN), 72 LSUOpType.hlvbu -> ZeroExt(rdata(7, 0), XLEN), 73 LSUOpType.hlvhu -> ZeroExt(rdata(15, 0), XLEN), 74 LSUOpType.hlvwu -> ZeroExt(rdata(31, 0), XLEN), 75 LSUOpType.hlvxhu -> ZeroExt(rdata(15, 0), XLEN), 76 LSUOpType.hlvxwu -> ZeroExt(rdata(31, 0), XLEN), 77 )) 78 } 79 80 def genRdataOH(uop: DynInst): UInt = { 81 val fuOpType = uop.fuOpType 82 val fpWen = uop.fpWen 83 val result = Cat( 84 (fuOpType === LSUOpType.lw && fpWen), 85 (fuOpType === LSUOpType.lh && fpWen), 86 (fuOpType === LSUOpType.lw && !fpWen) || (fuOpType === LSUOpType.hlvw), 87 (fuOpType === LSUOpType.lh && !fpWen) || (fuOpType === LSUOpType.hlvh), 88 (fuOpType === LSUOpType.lb) || (fuOpType === LSUOpType.hlvb), 89 (fuOpType === LSUOpType.ld) || (fuOpType === LSUOpType.hlvd), 90 (fuOpType === LSUOpType.lwu) || (fuOpType === LSUOpType.hlvwu) || (fuOpType === LSUOpType.hlvxwu), 91 (fuOpType === LSUOpType.lhu) || (fuOpType === LSUOpType.hlvhu) || (fuOpType === LSUOpType.hlvxhu), 92 (fuOpType === LSUOpType.lbu) || (fuOpType === LSUOpType.hlvbu), 93 ) 94 result 95 } 96 97 def newRdataHelper(select: UInt, rdata: UInt): UInt = { 98 XSError(PopCount(select) > 1.U, "data selector must be One-Hot!\n") 99 val selData = Seq( 100 ZeroExt(rdata(7, 0), XLEN), 101 ZeroExt(rdata(15, 0), XLEN), 102 ZeroExt(rdata(31, 0), XLEN), 103 rdata(63, 0), 104 SignExt(rdata(7, 0) , XLEN), 105 SignExt(rdata(15, 0) , XLEN), 106 SignExt(rdata(31, 0) , XLEN), 107 FPU.box(rdata, FPU.H), 108 FPU.box(rdata, FPU.S) 109 ) 110 Mux1H(select, selData) 111 } 112 113 def genDataSelectByOffset(addrOffset: UInt): Vec[Bool] = { 114 require(addrOffset.getWidth == 3) 115 VecInit((0 until 8).map{ case i => 116 addrOffset === i.U 117 }) 118 } 119 120 def rdataVecHelper(alignedType: UInt, rdata: UInt): UInt = { 121 LookupTree(alignedType, List( 122 "b00".U -> ZeroExt(rdata(7, 0), VLEN), 123 "b01".U -> ZeroExt(rdata(15, 0), VLEN), 124 "b10".U -> ZeroExt(rdata(31, 0), VLEN), 125 "b11".U -> ZeroExt(rdata(63, 0), VLEN) 126 )) 127 } 128} 129 130class LqEnqIO(implicit p: Parameters) extends MemBlockBundle { 131 val canAccept = Output(Bool()) 132 val sqCanAccept = Input(Bool()) 133 val needAlloc = Vec(LSQEnqWidth, Input(Bool())) 134 val req = Vec(LSQEnqWidth, Flipped(ValidIO(new DynInst))) 135 val resp = Vec(LSQEnqWidth, Output(new LqPtr)) 136} 137 138class LqTriggerIO(implicit p: Parameters) extends XSBundle { 139 val hitLoadAddrTriggerHitVec = Input(Vec(TriggerNum, Bool())) 140 val lqLoadAddrTriggerHitVec = Output(Vec(TriggerNum, Bool())) 141} 142 143class LoadQueueTopDownIO(implicit p: Parameters) extends XSBundle { 144 val robHeadVaddr = Flipped(Valid(UInt(VAddrBits.W))) 145 val robHeadTlbReplay = Output(Bool()) 146 val robHeadTlbMiss = Output(Bool()) 147 val robHeadLoadVio = Output(Bool()) 148 val robHeadLoadMSHR = Output(Bool()) 149 val robHeadMissInDTlb = Input(Bool()) 150 val robHeadOtherReplay = Output(Bool()) 151} 152 153class LoadQueue(implicit p: Parameters) extends XSModule 154 with HasDCacheParameters 155 with HasCircularQueuePtrHelper 156 with HasLoadHelper 157 with HasPerfEvents 158{ 159 val io = IO(new Bundle() { 160 val redirect = Flipped(Valid(new Redirect)) 161 val vecFeedback = Vec(VecLoadPipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO))) 162 val enq = new LqEnqIO 163 val ldu = new Bundle() { 164 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 165 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 166 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 167 } 168 val sta = new Bundle() { 169 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 170 } 171 val std = new Bundle() { 172 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput(isVector = true)))) // from store_s0, store data, send to sq from rs 173 } 174 val sq = new Bundle() { 175 val stAddrReadySqPtr = Input(new SqPtr) 176 val stAddrReadyVec = Input(Vec(StoreQueueSize, Bool())) 177 val stDataReadySqPtr = Input(new SqPtr) 178 val stDataReadyVec = Input(Vec(StoreQueueSize, Bool())) 179 val stIssuePtr = Input(new SqPtr) 180 val sqEmpty = Input(Bool()) 181 } 182 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 183 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 184 val ncOut = Vec(LoadPipelineWidth, DecoupledIO(new LsPipelineBundle)) 185 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 186 // val refill = Flipped(ValidIO(new Refill)) 187 val tl_d_channel = Input(new DcacheToLduForwardIO) 188 val release = Flipped(Valid(new Release)) 189 val nuke_rollback = Vec(StorePipelineWidth, Output(Valid(new Redirect))) 190 val nack_rollback = Vec(1, Output(Valid(new Redirect))) // uncachebuffer 191 val rob = Flipped(new RobLsqIO) 192 val uncache = new UncacheWordIO 193 val exceptionAddr = new ExceptionAddrIO 194 val flushFrmMaBuf = Input(Bool()) 195 val lqFull = Output(Bool()) 196 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 197 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 198 val lq_rep_full = Output(Bool()) 199 val tlbReplayDelayCycleCtrl = Vec(4, Input(UInt(ReSelectLen.W))) 200 val l2_hint = Input(Valid(new L2ToL1Hint())) 201 val tlb_hint = Flipped(new TlbHintIO) 202 val lqEmpty = Output(Bool()) 203 204 val lqDeqPtr = Output(new LqPtr) 205 206 val debugTopDown = new LoadQueueTopDownIO 207 }) 208 209 val loadQueueRAR = Module(new LoadQueueRAR) // read-after-read violation 210 val loadQueueRAW = Module(new LoadQueueRAW) // read-after-write violation 211 val loadQueueReplay = Module(new LoadQueueReplay) // enqueue if need replay 212 val virtualLoadQueue = Module(new VirtualLoadQueue) // control state 213 val exceptionBuffer = Module(new LqExceptionBuffer) // exception buffer 214 val uncacheBuffer = Module(new LoadQueueUncache) // uncache 215 /** 216 * LoadQueueRAR 217 */ 218 loadQueueRAR.io.redirect <> io.redirect 219 loadQueueRAR.io.vecFeedback <> io.vecFeedback 220 loadQueueRAR.io.release <> io.release 221 loadQueueRAR.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr 222 for (w <- 0 until LoadPipelineWidth) { 223 loadQueueRAR.io.query(w).req <> io.ldu.ldld_nuke_query(w).req // from load_s1 224 loadQueueRAR.io.query(w).resp <> io.ldu.ldld_nuke_query(w).resp // to load_s2 225 loadQueueRAR.io.query(w).revoke := io.ldu.ldld_nuke_query(w).revoke // from load_s3 226 } 227 228 /** 229 * LoadQueueRAW 230 */ 231 loadQueueRAW.io.redirect <> io.redirect 232 loadQueueRAW.io.vecFeedback <> io.vecFeedback 233 loadQueueRAW.io.storeIn <> io.sta.storeAddrIn 234 loadQueueRAW.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr 235 loadQueueRAW.io.stIssuePtr <> io.sq.stIssuePtr 236 for (w <- 0 until LoadPipelineWidth) { 237 loadQueueRAW.io.query(w).req <> io.ldu.stld_nuke_query(w).req // from load_s1 238 loadQueueRAW.io.query(w).resp <> io.ldu.stld_nuke_query(w).resp // to load_s2 239 loadQueueRAW.io.query(w).revoke := io.ldu.stld_nuke_query(w).revoke // from load_s3 240 } 241 242 /** 243 * VirtualLoadQueue 244 */ 245 virtualLoadQueue.io.redirect <> io.redirect 246 virtualLoadQueue.io.vecCommit <> io.vecFeedback 247 virtualLoadQueue.io.enq <> io.enq 248 virtualLoadQueue.io.ldin <> io.ldu.ldin // from load_s3 249 virtualLoadQueue.io.lqFull <> io.lqFull 250 virtualLoadQueue.io.lqDeq <> io.lqDeq 251 virtualLoadQueue.io.lqCancelCnt <> io.lqCancelCnt 252 virtualLoadQueue.io.lqEmpty <> io.lqEmpty 253 virtualLoadQueue.io.ldWbPtr <> io.lqDeqPtr 254 255 /** 256 * Load queue exception buffer 257 */ 258 exceptionBuffer.io.redirect <> io.redirect 259 for (i <- 0 until LoadPipelineWidth) { 260 exceptionBuffer.io.req(i).valid := io.ldu.ldin(i).valid && !io.ldu.ldin(i).bits.isvec // from load_s3 261 exceptionBuffer.io.req(i).bits := io.ldu.ldin(i).bits 262 } 263 // vlsu exception! 264 for (i <- 0 until VecLoadPipelineWidth) { 265 exceptionBuffer.io.req(LoadPipelineWidth + i).valid := io.vecFeedback(i).valid && io.vecFeedback(i).bits.feedback(VecFeedbacks.FLUSH) // have exception 266 exceptionBuffer.io.req(LoadPipelineWidth + i).bits := DontCare 267 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.vaddr := io.vecFeedback(i).bits.vaddr 268 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.fullva := io.vecFeedback(i).bits.vaddr 269 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.vaNeedExt := io.vecFeedback(i).bits.vaNeedExt 270 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.gpaddr := io.vecFeedback(i).bits.gpaddr 271 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.uopIdx := io.vecFeedback(i).bits.uopidx 272 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.robIdx := io.vecFeedback(i).bits.robidx 273 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.vpu.vstart := io.vecFeedback(i).bits.vstart 274 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.vpu.vl := io.vecFeedback(i).bits.vl 275 exceptionBuffer.io.req(LoadPipelineWidth + i).bits.uop.exceptionVec := io.vecFeedback(i).bits.exceptionVec 276 } 277 // mmio non-data error exception 278 exceptionBuffer.io.req(LoadPipelineWidth + VecLoadPipelineWidth) := uncacheBuffer.io.exception 279 exceptionBuffer.io.req(LoadPipelineWidth + VecLoadPipelineWidth).bits.vaNeedExt := true.B 280 exceptionBuffer.io.flushFrmMaBuf := io.flushFrmMaBuf 281 282 io.exceptionAddr <> exceptionBuffer.io.exceptionAddr 283 284 /** 285 * Load uncache buffer 286 */ 287 uncacheBuffer.io.redirect <> io.redirect 288 uncacheBuffer.io.mmioOut <> io.ldout 289 uncacheBuffer.io.ncOut <> io.ncOut 290 uncacheBuffer.io.mmioRawData <> io.ld_raw_data 291 uncacheBuffer.io.rob <> io.rob 292 uncacheBuffer.io.uncache <> io.uncache 293 294 for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) { 295 // from load_s3 296 val ldinBits = io.ldu.ldin(w).bits 297 buff.valid := io.ldu.ldin(w).valid && (ldinBits.nc || ldinBits.mmio) && !ldinBits.rep_info.need_rep 298 buff.bits := ldinBits 299 } 300 301 io.uncache.resp.ready := true.B 302 303 io.nuke_rollback := loadQueueRAW.io.rollback 304 io.nack_rollback(0) := uncacheBuffer.io.rollback 305 306 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 307 308 /** 309 * LoadQueueReplay 310 */ 311 loadQueueReplay.io.redirect <> io.redirect 312 loadQueueReplay.io.enq <> io.ldu.ldin // from load_s3 313 loadQueueReplay.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 314 loadQueueReplay.io.storeDataIn <> io.std.storeDataIn // from store_s0 315 loadQueueReplay.io.replay <> io.replay 316 //loadQueueReplay.io.refill <> io.refill 317 loadQueueReplay.io.tl_d_channel <> io.tl_d_channel 318 loadQueueReplay.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr 319 loadQueueReplay.io.stAddrReadyVec <> io.sq.stAddrReadyVec 320 loadQueueReplay.io.stDataReadySqPtr <> io.sq.stDataReadySqPtr 321 loadQueueReplay.io.stDataReadyVec <> io.sq.stDataReadyVec 322 loadQueueReplay.io.sqEmpty <> io.sq.sqEmpty 323 loadQueueReplay.io.lqFull <> io.lq_rep_full 324 loadQueueReplay.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr 325 loadQueueReplay.io.rarFull <> loadQueueRAR.io.lqFull 326 loadQueueReplay.io.rawFull <> loadQueueRAW.io.lqFull 327 loadQueueReplay.io.l2_hint <> io.l2_hint 328 loadQueueReplay.io.tlb_hint <> io.tlb_hint 329 loadQueueReplay.io.tlbReplayDelayCycleCtrl <> io.tlbReplayDelayCycleCtrl 330 // TODO: implement it! 331 loadQueueReplay.io.vecFeedback := io.vecFeedback 332 333 loadQueueReplay.io.debugTopDown <> io.debugTopDown 334 335 val full_mask = Cat(loadQueueRAR.io.lqFull, loadQueueRAW.io.lqFull, loadQueueReplay.io.lqFull) 336 XSPerfAccumulate("full_mask_000", full_mask === 0.U) 337 XSPerfAccumulate("full_mask_001", full_mask === 1.U) 338 XSPerfAccumulate("full_mask_010", full_mask === 2.U) 339 XSPerfAccumulate("full_mask_011", full_mask === 3.U) 340 XSPerfAccumulate("full_mask_100", full_mask === 4.U) 341 XSPerfAccumulate("full_mask_101", full_mask === 5.U) 342 XSPerfAccumulate("full_mask_110", full_mask === 6.U) 343 XSPerfAccumulate("full_mask_111", full_mask === 7.U) 344 XSPerfAccumulate("nuke_rollback", io.nuke_rollback.map(_.valid).reduce(_ || _).asUInt) 345 XSPerfAccumulate("nack_rollabck", io.nack_rollback.map(_.valid).reduce(_ || _).asUInt) 346 347 // perf cnt 348 val perfEvents = Seq(virtualLoadQueue, loadQueueRAR, loadQueueRAW, loadQueueReplay).flatMap(_.getPerfEvents) ++ 349 Seq( 350 ("full_mask_000", full_mask === 0.U), 351 ("full_mask_001", full_mask === 1.U), 352 ("full_mask_010", full_mask === 2.U), 353 ("full_mask_011", full_mask === 3.U), 354 ("full_mask_100", full_mask === 4.U), 355 ("full_mask_101", full_mask === 5.U), 356 ("full_mask_110", full_mask === 6.U), 357 ("full_mask_111", full_mask === 7.U), 358 ("nuke_rollback", io.nuke_rollback.map(_.valid).reduce(_ || _).asUInt), 359 ("nack_rollback", io.nack_rollback.map(_.valid).reduce(_ || _).asUInt) 360 ) 361 generatePerfEvent() 362 // end 363}