1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.fu.fpu.FPU 26import xiangshan.backend.rob.RobLsqIO 27import xiangshan.cache._ 28import xiangshan.frontend.FtqPtr 29import xiangshan.ExceptionNO._ 30import xiangshan.mem.mdp._ 31import xiangshan.backend.Bundles.{DynInst, MemExuOutput, MemMicroOpRbExt} 32import xiangshan.backend.rob.RobPtr 33 34class LqPtr(implicit p: Parameters) extends CircularQueuePtr[LqPtr]( 35 p => p(XSCoreParamsKey).VirtualLoadQueueSize 36){ 37} 38 39object LqPtr { 40 def apply(f: Bool, v: UInt)(implicit p: Parameters): LqPtr = { 41 val ptr = Wire(new LqPtr) 42 ptr.flag := f 43 ptr.value := v 44 ptr 45 } 46} 47 48trait HasLoadHelper { this: XSModule => 49 def rdataHelper(uop: DynInst, rdata: UInt): UInt = { 50 val fpWen = uop.fpWen 51 LookupTree(uop.fuOpType, List( 52 LSUOpType.lb -> SignExt(rdata(7, 0) , XLEN), 53 LSUOpType.lh -> SignExt(rdata(15, 0), XLEN), 54 /* 55 riscv-spec-20191213: 12.2 NaN Boxing of Narrower Values 56 Any operation that writes a narrower result to an f register must write 57 all 1s to the uppermost FLEN−n bits to yield a legal NaN-boxed value. 58 */ 59 LSUOpType.lw -> Mux(fpWen, FPU.box(rdata, FPU.S), SignExt(rdata(31, 0), XLEN)), 60 LSUOpType.ld -> Mux(fpWen, FPU.box(rdata, FPU.D), SignExt(rdata(63, 0), XLEN)), 61 LSUOpType.lbu -> ZeroExt(rdata(7, 0) , XLEN), 62 LSUOpType.lhu -> ZeroExt(rdata(15, 0), XLEN), 63 LSUOpType.lwu -> ZeroExt(rdata(31, 0), XLEN), 64 )) 65 } 66} 67 68class LqEnqIO(implicit p: Parameters) extends XSBundle { 69 private val LsExuCnt = backendParams.StaCnt + backendParams.LduCnt 70 val canAccept = Output(Bool()) 71 val sqCanAccept = Input(Bool()) 72 val needAlloc = Vec(LsExuCnt, Input(Bool())) 73 val req = Vec(LsExuCnt, Flipped(ValidIO(new DynInst))) 74 val resp = Vec(LsExuCnt, Output(new LqPtr)) 75} 76 77class LqTriggerIO(implicit p: Parameters) extends XSBundle { 78 val hitLoadAddrTriggerHitVec = Input(Vec(3, Bool())) 79 val lqLoadAddrTriggerHitVec = Output(Vec(3, Bool())) 80} 81 82class LoadQueueTopDownIO(implicit p: Parameters) extends XSBundle { 83 val robHeadVaddr = Flipped(Valid(UInt(VAddrBits.W))) 84 val robHeadTlbReplay = Output(Bool()) 85 val robHeadTlbMiss = Output(Bool()) 86 val robHeadLoadVio = Output(Bool()) 87 val robHeadLoadMSHR = Output(Bool()) 88 val robHeadMissInDTlb = Input(Bool()) 89 val robHeadOtherReplay = Output(Bool()) 90} 91 92class LoadQueue(implicit p: Parameters) extends XSModule 93 with HasDCacheParameters 94 with HasCircularQueuePtrHelper 95 with HasLoadHelper 96 with HasPerfEvents 97{ 98 val io = IO(new Bundle() { 99 val redirect = Flipped(Valid(new Redirect)) 100 val enq = new LqEnqIO 101 val ldu = new Bundle() { 102 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 103 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 104 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 105 } 106 val sta = new Bundle() { 107 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 108 } 109 val std = new Bundle() { 110 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput))) // from store_s0, store data, send to sq from rs 111 } 112 val sq = new Bundle() { 113 val stAddrReadySqPtr = Input(new SqPtr) 114 val stAddrReadyVec = Input(Vec(StoreQueueSize, Bool())) 115 val stDataReadySqPtr = Input(new SqPtr) 116 val stDataReadyVec = Input(Vec(StoreQueueSize, Bool())) 117 val stIssuePtr = Input(new SqPtr) 118 val sqEmpty = Input(Bool()) 119 } 120 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 121 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 122 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 123 val refill = Flipped(ValidIO(new Refill)) 124 val tl_d_channel = Input(new DcacheToLduForwardIO) 125 val release = Flipped(Valid(new Release)) 126 val rollback = Output(Valid(new Redirect)) 127 val rob = Flipped(new RobLsqIO) 128 val uncache = new UncacheWordIO 129 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 130 val exceptionAddr = new ExceptionAddrIO 131 val lqFull = Output(Bool()) 132 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 133 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 134 val lq_rep_full = Output(Bool()) 135 val tlbReplayDelayCycleCtrl = Vec(4, Input(UInt(ReSelectLen.W))) 136 val l2_hint = Input(Valid(new L2ToL1Hint())) 137 val lqEmpty = Output(Bool()) 138 val debugTopDown = new LoadQueueTopDownIO 139 }) 140 141 val loadQueueRAR = Module(new LoadQueueRAR) // read-after-read violation 142 val loadQueueRAW = Module(new LoadQueueRAW) // read-after-write violation 143 val loadQueueReplay = Module(new LoadQueueReplay) // enqueue if need replay 144 val virtualLoadQueue = Module(new VirtualLoadQueue) // control state 145 val exceptionBuffer = Module(new LqExceptionBuffer) // exception buffer 146 val uncacheBuffer = Module(new UncacheBuffer) // uncache buffer 147 148 /** 149 * LoadQueueRAR 150 */ 151 loadQueueRAR.io.redirect <> io.redirect 152 loadQueueRAR.io.release <> io.release 153 loadQueueRAR.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr 154 for (w <- 0 until LoadPipelineWidth) { 155 loadQueueRAR.io.query(w).req <> io.ldu.ldld_nuke_query(w).req // from load_s1 156 loadQueueRAR.io.query(w).resp <> io.ldu.ldld_nuke_query(w).resp // to load_s2 157 loadQueueRAR.io.query(w).revoke := io.ldu.ldld_nuke_query(w).revoke // from load_s3 158 } 159 160 /** 161 * LoadQueueRAW 162 */ 163 loadQueueRAW.io.redirect <> io.redirect 164 loadQueueRAW.io.storeIn <> io.sta.storeAddrIn 165 loadQueueRAW.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr 166 loadQueueRAW.io.stIssuePtr <> io.sq.stIssuePtr 167 for (w <- 0 until LoadPipelineWidth) { 168 loadQueueRAW.io.query(w).req <> io.ldu.stld_nuke_query(w).req // from load_s1 169 loadQueueRAW.io.query(w).resp <> io.ldu.stld_nuke_query(w).resp // to load_s2 170 loadQueueRAW.io.query(w).revoke := io.ldu.stld_nuke_query(w).revoke // from load_s3 171 } 172 173 /** 174 * VirtualLoadQueue 175 */ 176 virtualLoadQueue.io.redirect <> io.redirect 177 virtualLoadQueue.io.enq <> io.enq 178 virtualLoadQueue.io.ldin <> io.ldu.ldin // from load_s3 179 virtualLoadQueue.io.lqFull <> io.lqFull 180 virtualLoadQueue.io.lqDeq <> io.lqDeq 181 virtualLoadQueue.io.lqCancelCnt <> io.lqCancelCnt 182 virtualLoadQueue.io.lqEmpty <> io.lqEmpty 183 184 /** 185 * Load queue exception buffer 186 */ 187 exceptionBuffer.io.redirect <> io.redirect 188 for ((buff, w) <- exceptionBuffer.io.req.zipWithIndex) { 189 buff.valid := io.ldu.ldin(w).valid // from load_s3 190 buff.bits := io.ldu.ldin(w).bits 191 } 192 io.exceptionAddr <> exceptionBuffer.io.exceptionAddr 193 194 /** 195 * Load uncache buffer 196 */ 197 uncacheBuffer.io.redirect <> io.redirect 198 uncacheBuffer.io.ldout <> io.ldout 199 uncacheBuffer.io.ld_raw_data <> io.ld_raw_data 200 uncacheBuffer.io.rob <> io.rob 201 uncacheBuffer.io.uncache <> io.uncache 202 uncacheBuffer.io.trigger <> io.trigger 203 for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) { 204 buff.valid := io.ldu.ldin(w).valid // from load_s3 205 buff.bits := io.ldu.ldin(w).bits // from load_s3 206 } 207 208 // rollback 209 def selectOldest[T <: Redirect](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = { 210 assert(valid.length == bits.length) 211 if (valid.length == 0 || valid.length == 1) { 212 (valid, bits) 213 } else if (valid.length == 2) { 214 val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0))))) 215 for (i <- res.indices) { 216 res(i).valid := valid(i) 217 res(i).bits := bits(i) 218 } 219 val oldest = Mux(valid(0) && valid(1), Mux(isAfter(bits(0).robIdx, bits(1).robIdx), res(1), res(0)), Mux(valid(0) && !valid(1), res(0), res(1))) 220 (Seq(oldest.valid), Seq(oldest.bits)) 221 } else { 222 val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2)) 223 val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2))) 224 selectOldest(left._1 ++ right._1, left._2 ++ right._2) 225 } 226 } 227 228 val (rollbackSelV, rollbackSelBits) = selectOldest( 229 Seq(loadQueueRAW.io.rollback.valid, uncacheBuffer.io.rollback.valid), 230 Seq(loadQueueRAW.io.rollback.bits, uncacheBuffer.io.rollback.bits) 231 ) 232 io.rollback.valid := rollbackSelV.head 233 io.rollback.bits := rollbackSelBits.head 234 235 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 236 237 /** 238 * LoadQueueReplay 239 */ 240 loadQueueReplay.io.redirect <> io.redirect 241 loadQueueReplay.io.enq <> io.ldu.ldin // from load_s3 242 loadQueueReplay.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 243 loadQueueReplay.io.storeDataIn <> io.std.storeDataIn // from store_s0 244 loadQueueReplay.io.replay <> io.replay 245 loadQueueReplay.io.refill <> io.refill 246 loadQueueReplay.io.tl_d_channel <> io.tl_d_channel 247 loadQueueReplay.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr 248 loadQueueReplay.io.stAddrReadyVec <> io.sq.stAddrReadyVec 249 loadQueueReplay.io.stDataReadySqPtr <> io.sq.stDataReadySqPtr 250 loadQueueReplay.io.stDataReadyVec <> io.sq.stDataReadyVec 251 loadQueueReplay.io.sqEmpty <> io.sq.sqEmpty 252 loadQueueReplay.io.lqFull <> io.lq_rep_full 253 loadQueueReplay.io.ldWbPtr <> virtualLoadQueue.io.ldWbPtr 254 loadQueueReplay.io.rarFull <> loadQueueRAR.io.lqFull 255 loadQueueReplay.io.rawFull <> loadQueueRAW.io.lqFull 256 loadQueueReplay.io.l2_hint <> io.l2_hint 257 loadQueueReplay.io.tlbReplayDelayCycleCtrl <> io.tlbReplayDelayCycleCtrl 258 259 loadQueueReplay.io.debugTopDown <> io.debugTopDown 260 261 val full_mask = Cat(loadQueueRAR.io.lqFull, loadQueueRAW.io.lqFull, loadQueueReplay.io.lqFull) 262 XSPerfAccumulate("full_mask_000", full_mask === 0.U) 263 XSPerfAccumulate("full_mask_001", full_mask === 1.U) 264 XSPerfAccumulate("full_mask_010", full_mask === 2.U) 265 XSPerfAccumulate("full_mask_011", full_mask === 3.U) 266 XSPerfAccumulate("full_mask_100", full_mask === 4.U) 267 XSPerfAccumulate("full_mask_101", full_mask === 5.U) 268 XSPerfAccumulate("full_mask_110", full_mask === 6.U) 269 XSPerfAccumulate("full_mask_111", full_mask === 7.U) 270 XSPerfAccumulate("rollback", io.rollback.valid) 271 272 // perf cnt 273 val perfEvents = Seq(virtualLoadQueue, loadQueueRAR, loadQueueRAW, loadQueueReplay).flatMap(_.getPerfEvents) ++ 274 Seq( 275 ("full_mask_000", full_mask === 0.U), 276 ("full_mask_001", full_mask === 1.U), 277 ("full_mask_010", full_mask === 2.U), 278 ("full_mask_011", full_mask === 3.U), 279 ("full_mask_100", full_mask === 4.U), 280 ("full_mask_101", full_mask === 5.U), 281 ("full_mask_110", full_mask === 6.U), 282 ("full_mask_111", full_mask === 7.U), 283 ("rollback", io.rollback.valid) 284 ) 285 generatePerfEvent() 286 // end 287}