1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants} 9import xiangshan.backend.LSUOpType 10import xiangshan.mem._ 11import xiangshan.backend.roq.RoqPtr 12import xiangshan.backend.fu.fpu.boxF32ToF64 13 14 15class LqPtr extends CircularQueuePtr(LqPtr.LoadQueueSize) { } 16 17object LqPtr extends HasXSParameter { 18 def apply(f: Bool, v: UInt): LqPtr = { 19 val ptr = Wire(new LqPtr) 20 ptr.flag := f 21 ptr.value := v 22 ptr 23 } 24} 25 26 27// Load Queue 28class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper { 29 val io = IO(new Bundle() { 30 val enq = new Bundle() { 31 val canAccept = Output(Bool()) 32 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 33 val resp = Vec(RenameWidth, Output(new LqPtr)) 34 } 35 val brqRedirect = Input(Valid(new Redirect)) 36 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 37 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // FIXME: Valid() only 38 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback load 39 val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO)) 40 val commits = Flipped(new RoqCommitIO) 41 val rollback = Output(Valid(new Redirect)) // replay now starts from load instead of store 42 val dcache = new DCacheLineIO 43 val uncache = new DCacheWordIO 44 val roqDeqPtr = Input(new RoqPtr) 45 val exceptionAddr = new ExceptionAddrIO 46 // val refill = Flipped(Valid(new DCacheLineReq )) 47 }) 48 49 val uop = Reg(Vec(LoadQueueSize, new MicroOp)) 50 // val data = Reg(Vec(LoadQueueSize, new LsRoqEntry)) 51 val dataModule = Module(new LSQueueData(LoadQueueSize, LoadPipelineWidth)) 52 dataModule.io := DontCare 53 val allocated = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // lq entry has been allocated 54 val datavalid = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // data is valid 55 val writebacked = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // inst has been writebacked to CDB 56 val commited = Reg(Vec(LoadQueueSize, Bool())) // inst has been writebacked to CDB 57 val miss = Reg(Vec(LoadQueueSize, Bool())) // load inst missed, waiting for miss queue to accept miss request 58 val listening = Reg(Vec(LoadQueueSize, Bool())) // waiting for refill result 59 val pending = Reg(Vec(LoadQueueSize, Bool())) // mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of roq 60 61 val enqPtrExt = RegInit(0.U.asTypeOf(new LqPtr)) 62 val deqPtrExt = RegInit(0.U.asTypeOf(new LqPtr)) 63 val enqPtr = enqPtrExt.value 64 val deqPtr = deqPtrExt.value 65 val sameFlag = enqPtrExt.flag === deqPtrExt.flag 66 val isEmpty = enqPtr === deqPtr && sameFlag 67 val isFull = enqPtr === deqPtr && !sameFlag 68 val allowIn = !isFull 69 70 val loadCommit = (0 until CommitWidth).map(i => io.commits.valid(i) && !io.commits.isWalk && io.commits.uop(i).ctrl.commitType === CommitType.LOAD) 71 val mcommitIdx = (0 until CommitWidth).map(i => io.commits.uop(i).lqIdx.value) 72 73 val deqMask = UIntToMask(deqPtr, LoadQueueSize) 74 val enqMask = UIntToMask(enqPtr, LoadQueueSize) 75 val enqDeqMask1 = deqMask ^ enqMask 76 val enqDeqMask = Mux(sameFlag, enqDeqMask1, ~enqDeqMask1) 77 78 // Enqueue at dispatch 79 val validEntries = distanceBetween(enqPtrExt, deqPtrExt) 80 val firedDispatch = io.enq.req.map(_.valid) 81 io.enq.canAccept := validEntries <= (LoadQueueSize - RenameWidth).U 82 XSDebug(p"(ready, valid): ${io.enq.canAccept}, ${Binary(Cat(firedDispatch))}\n") 83 for (i <- 0 until RenameWidth) { 84 val offset = if (i == 0) 0.U else PopCount((0 until i).map(firedDispatch(_))) 85 val lqIdx = enqPtrExt + offset 86 val index = lqIdx.value 87 when(io.enq.req(i).valid) { 88 uop(index) := io.enq.req(i).bits 89 allocated(index) := true.B 90 datavalid(index) := false.B 91 writebacked(index) := false.B 92 commited(index) := false.B 93 miss(index) := false.B 94 listening(index) := false.B 95 pending(index) := false.B 96 } 97 io.enq.resp(i) := lqIdx 98 99 XSError(!io.enq.canAccept && io.enq.req(i).valid, "should not valid when not ready\n") 100 } 101 102 when(Cat(firedDispatch).orR) { 103 enqPtrExt := enqPtrExt + PopCount(firedDispatch) 104 XSInfo("dispatched %d insts to lq\n", PopCount(firedDispatch)) 105 } 106 107 // writeback load 108 (0 until LoadPipelineWidth).map(i => { 109 dataModule.io.wb(i).wen := false.B 110 when(io.loadIn(i).fire()) { 111 when(io.loadIn(i).bits.miss) { 112 XSInfo(io.loadIn(i).valid, "load miss write to lq idx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n", 113 io.loadIn(i).bits.uop.lqIdx.asUInt, 114 io.loadIn(i).bits.uop.cf.pc, 115 io.loadIn(i).bits.vaddr, 116 io.loadIn(i).bits.paddr, 117 io.loadIn(i).bits.data, 118 io.loadIn(i).bits.mask, 119 io.loadIn(i).bits.forwardData.asUInt, 120 io.loadIn(i).bits.forwardMask.asUInt, 121 io.loadIn(i).bits.mmio, 122 io.loadIn(i).bits.rollback, 123 io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 124 ) 125 }.otherwise { 126 XSInfo(io.loadIn(i).valid, "load hit write to cbd lqidx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n", 127 io.loadIn(i).bits.uop.lqIdx.asUInt, 128 io.loadIn(i).bits.uop.cf.pc, 129 io.loadIn(i).bits.vaddr, 130 io.loadIn(i).bits.paddr, 131 io.loadIn(i).bits.data, 132 io.loadIn(i).bits.mask, 133 io.loadIn(i).bits.forwardData.asUInt, 134 io.loadIn(i).bits.forwardMask.asUInt, 135 io.loadIn(i).bits.mmio, 136 io.loadIn(i).bits.rollback, 137 io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 138 ) 139 } 140 val loadWbIndex = io.loadIn(i).bits.uop.lqIdx.value 141 datavalid(loadWbIndex) := !io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 142 writebacked(loadWbIndex) := !io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 143 144 val loadWbData = Wire(new LsqEntry) 145 loadWbData.paddr := io.loadIn(i).bits.paddr 146 loadWbData.vaddr := io.loadIn(i).bits.vaddr 147 loadWbData.mask := io.loadIn(i).bits.mask 148 loadWbData.data := io.loadIn(i).bits.data // for mmio / misc / debug 149 loadWbData.mmio := io.loadIn(i).bits.mmio 150 loadWbData.fwdMask := io.loadIn(i).bits.forwardMask 151 loadWbData.fwdData := io.loadIn(i).bits.forwardData 152 loadWbData.exception := io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 153 dataModule.io.wbWrite(i, loadWbIndex, loadWbData) 154 dataModule.io.wb(i).wen := true.B 155 156 val dcacheMissed = io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 157 miss(loadWbIndex) := dcacheMissed && !io.loadIn(i).bits.uop.cf.exceptionVec.asUInt.orR 158 listening(loadWbIndex) := dcacheMissed 159 pending(loadWbIndex) := io.loadIn(i).bits.mmio && !io.loadIn(i).bits.uop.cf.exceptionVec.asUInt.orR 160 } 161 }) 162 163 // cache miss request 164 val inflightReqs = RegInit(VecInit(Seq.fill(cfg.nLoadMissEntries)(0.U.asTypeOf(new InflightBlockInfo)))) 165 val inflightReqFull = inflightReqs.map(req => req.valid).reduce(_&&_) 166 val reqBlockIndex = PriorityEncoder(~VecInit(inflightReqs.map(req => req.valid)).asUInt) 167 168 val missRefillSelVec = VecInit( 169 (0 until LoadQueueSize).map{ i => 170 val inflight = inflightReqs.map(req => req.valid && req.block_addr === get_block_addr(dataModule.io.rdata(i).paddr)).reduce(_||_) 171 allocated(i) && miss(i) && !inflight 172 }) 173 174 val missRefillSel = getFirstOne(missRefillSelVec, deqMask) 175 val missRefillBlockAddr = get_block_addr(dataModule.io.rdata(missRefillSel).paddr) 176 io.dcache.req.valid := missRefillSelVec.asUInt.orR 177 io.dcache.req.bits.cmd := MemoryOpConstants.M_XRD 178 io.dcache.req.bits.addr := missRefillBlockAddr 179 io.dcache.req.bits.data := DontCare 180 io.dcache.req.bits.mask := DontCare 181 182 io.dcache.req.bits.meta.id := DontCare 183 io.dcache.req.bits.meta.vaddr := DontCare // dataModule.io.rdata(missRefillSel).vaddr 184 io.dcache.req.bits.meta.paddr := missRefillBlockAddr 185 io.dcache.req.bits.meta.uop := uop(missRefillSel) 186 io.dcache.req.bits.meta.mmio := false.B // dataModule.io.rdata(missRefillSel).mmio 187 io.dcache.req.bits.meta.tlb_miss := false.B 188 io.dcache.req.bits.meta.mask := DontCare 189 io.dcache.req.bits.meta.replay := false.B 190 191 io.dcache.resp.ready := true.B 192 193 assert(!(dataModule.io.rdata(missRefillSel).mmio && io.dcache.req.valid)) 194 195 when(io.dcache.req.fire()) { 196 miss(missRefillSel) := false.B 197 listening(missRefillSel) := true.B 198 199 // mark this block as inflight 200 inflightReqs(reqBlockIndex).valid := true.B 201 inflightReqs(reqBlockIndex).block_addr := missRefillBlockAddr 202 assert(!inflightReqs(reqBlockIndex).valid) 203 } 204 205 when(io.dcache.resp.fire()) { 206 val inflight = inflightReqs.map(req => req.valid && req.block_addr === get_block_addr(io.dcache.resp.bits.meta.paddr)).reduce(_||_) 207 assert(inflight) 208 for (i <- 0 until cfg.nLoadMissEntries) { 209 when (inflightReqs(i).valid && inflightReqs(i).block_addr === get_block_addr(io.dcache.resp.bits.meta.paddr)) { 210 inflightReqs(i).valid := false.B 211 } 212 } 213 } 214 215 216 when(io.dcache.req.fire()){ 217 XSDebug("miss req: pc:0x%x roqIdx:%d lqIdx:%d (p)addr:0x%x vaddr:0x%x\n", 218 io.dcache.req.bits.meta.uop.cf.pc, io.dcache.req.bits.meta.uop.roqIdx.asUInt, io.dcache.req.bits.meta.uop.lqIdx.asUInt, 219 io.dcache.req.bits.addr, io.dcache.req.bits.meta.vaddr 220 ) 221 } 222 223 when(io.dcache.resp.fire()){ 224 XSDebug("miss resp: pc:0x%x roqIdx:%d lqIdx:%d (p)addr:0x%x data %x\n", 225 io.dcache.resp.bits.meta.uop.cf.pc, io.dcache.resp.bits.meta.uop.roqIdx.asUInt, io.dcache.resp.bits.meta.uop.lqIdx.asUInt, 226 io.dcache.resp.bits.meta.paddr, io.dcache.resp.bits.data 227 ) 228 } 229 230 // Refill 64 bit in a cycle 231 // Refill data comes back from io.dcache.resp 232 dataModule.io.refill.dcache := io.dcache.resp.bits 233 234 (0 until LoadQueueSize).map(i => { 235 val blockMatch = get_block_addr(dataModule.io.rdata(i).paddr) === io.dcache.resp.bits.meta.paddr 236 dataModule.io.refill.wen(i) := false.B 237 when(allocated(i) && listening(i) && blockMatch && io.dcache.resp.fire()) { 238 dataModule.io.refill.wen(i) := true.B 239 datavalid(i) := true.B 240 listening(i) := false.B 241 } 242 }) 243 244 // writeback up to 2 missed load insts to CDB 245 // just randomly pick 2 missed load (data refilled), write them back to cdb 246 val loadWbSelVec = VecInit((0 until LoadQueueSize).map(i => { 247 allocated(i) && datavalid(i) && !writebacked(i) 248 })).asUInt() // use uint instead vec to reduce verilog lines 249 val loadWbSel = Wire(Vec(StorePipelineWidth, UInt(log2Up(LoadQueueSize).W))) 250 val loadWbSelV= Wire(Vec(StorePipelineWidth, Bool())) 251 val lselvec0 = PriorityEncoderOH(loadWbSelVec) 252 val lselvec1 = PriorityEncoderOH(loadWbSelVec & (~lselvec0).asUInt) 253 loadWbSel(0) := OHToUInt(lselvec0) 254 loadWbSelV(0):= lselvec0.orR 255 loadWbSel(1) := OHToUInt(lselvec1) 256 loadWbSelV(1) := lselvec1.orR 257 (0 until StorePipelineWidth).map(i => { 258 // data select 259 val rdata = dataModule.io.rdata(loadWbSel(i)).data 260 val func = uop(loadWbSel(i)).ctrl.fuOpType 261 val raddr = dataModule.io.rdata(loadWbSel(i)).paddr 262 val rdataSel = LookupTree(raddr(2, 0), List( 263 "b000".U -> rdata(63, 0), 264 "b001".U -> rdata(63, 8), 265 "b010".U -> rdata(63, 16), 266 "b011".U -> rdata(63, 24), 267 "b100".U -> rdata(63, 32), 268 "b101".U -> rdata(63, 40), 269 "b110".U -> rdata(63, 48), 270 "b111".U -> rdata(63, 56) 271 )) 272 val rdataPartialLoad = LookupTree(func, List( 273 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 274 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 275 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 276 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 277 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 278 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 279 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN), 280 LSUOpType.flw -> boxF32ToF64(rdataSel(31, 0)) 281 )) 282 io.ldout(i).bits.uop := uop(loadWbSel(i)) 283 io.ldout(i).bits.uop.cf.exceptionVec := dataModule.io.rdata(loadWbSel(i)).exception.asBools 284 io.ldout(i).bits.uop.lqIdx := loadWbSel(i).asTypeOf(new LqPtr) 285 io.ldout(i).bits.data := rdataPartialLoad 286 io.ldout(i).bits.redirectValid := false.B 287 io.ldout(i).bits.redirect := DontCare 288 io.ldout(i).bits.brUpdate := DontCare 289 io.ldout(i).bits.debug.isMMIO := dataModule.io.rdata(loadWbSel(i)).mmio 290 io.ldout(i).bits.fflags := DontCare 291 io.ldout(i).valid := loadWbSelVec(loadWbSel(i)) && loadWbSelV(i) 292 when(io.ldout(i).fire()) { 293 writebacked(loadWbSel(i)) := true.B 294 XSInfo("load miss write to cbd roqidx %d lqidx %d pc 0x%x paddr %x data %x mmio %x\n", 295 io.ldout(i).bits.uop.roqIdx.asUInt, 296 io.ldout(i).bits.uop.lqIdx.asUInt, 297 io.ldout(i).bits.uop.cf.pc, 298 dataModule.io.rdata(loadWbSel(i)).paddr, 299 dataModule.io.rdata(loadWbSel(i)).data, 300 dataModule.io.rdata(loadWbSel(i)).mmio 301 ) 302 } 303 }) 304 305 // When load commited, mark it as !allocated, this entry will be recycled later 306 (0 until CommitWidth).map(i => { 307 when(loadCommit(i)) { 308 allocated(mcommitIdx(i)) := false.B 309 XSDebug("load commit %d: idx %d %x\n", i.U, mcommitIdx(i), uop(mcommitIdx(i)).cf.pc) 310 } 311 }) 312 deqPtrExt := deqPtrExt + PopCount(loadCommit) 313 314 def getFirstOne(mask: Vec[Bool], startMask: UInt) = { 315 val length = mask.length 316 val highBits = (0 until length).map(i => mask(i) & ~startMask(i)) 317 val highBitsUint = Cat(highBits.reverse) 318 PriorityEncoder(Mux(highBitsUint.orR(), highBitsUint, mask.asUInt)) 319 } 320 321 def getFirstOneWithFlag(mask: Vec[Bool], startMask: UInt, startFlag: Bool) = { 322 val length = mask.length 323 val highBits = (0 until length).map(i => mask(i) & ~startMask(i)) 324 val highBitsUint = Cat(highBits.reverse) 325 val changeDirection = !highBitsUint.orR() 326 val index = PriorityEncoder(Mux(!changeDirection, highBitsUint, mask.asUInt)) 327 LqPtr(startFlag ^ changeDirection, index) 328 } 329 330 def getOldestInTwo(valid: Seq[Bool], uop: Seq[MicroOp]) = { 331 assert(valid.length == uop.length) 332 assert(valid.length == 2) 333 Mux(valid(0) && valid(1), 334 Mux(isAfter(uop(0).roqIdx, uop(1).roqIdx), uop(1), uop(0)), 335 Mux(valid(0) && !valid(1), uop(0), uop(1))) 336 } 337 338 def getAfterMask(valid: Seq[Bool], uop: Seq[MicroOp]) = { 339 assert(valid.length == uop.length) 340 val length = valid.length 341 (0 until length).map(i => { 342 (0 until length).map(j => { 343 Mux(valid(i) && valid(j), 344 isAfter(uop(i).roqIdx, uop(j).roqIdx), 345 Mux(!valid(i), true.B, false.B)) 346 }) 347 }) 348 } 349 350 def rangeMask(start: LqPtr, end: LqPtr): UInt = { 351 val startMask = (1.U((LoadQueueSize + 1).W) << start.value).asUInt - 1.U 352 val endMask = (1.U((LoadQueueSize + 1).W) << end.value).asUInt - 1.U 353 val xorMask = startMask(LoadQueueSize - 1, 0) ^ endMask(LoadQueueSize - 1, 0) 354 Mux(start.flag === end.flag, xorMask, ~xorMask) 355 } 356 357 // ignore data forward 358 (0 until LoadPipelineWidth).foreach(i => { 359 io.forward(i).forwardMask := DontCare 360 io.forward(i).forwardData := DontCare 361 }) 362 363 // store backward query and rollback 364 def detectRollback(i: Int) = { 365 val startIndex = io.storeIn(i).bits.uop.lqIdx.value 366 val lqIdxMask = UIntToMask(startIndex, LoadQueueSize) 367 val xorMask = lqIdxMask ^ enqMask 368 val sameFlag = io.storeIn(i).bits.uop.lqIdx.flag === enqPtrExt.flag 369 val toEnqPtrMask = Mux(sameFlag, xorMask, ~xorMask) 370 371 // check if load already in lq needs to be rolledback 372 val lqViolationVec = RegNext(VecInit((0 until LoadQueueSize).map(j => { 373 val addrMatch = allocated(j) && 374 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === dataModule.io.rdata(j).paddr(PAddrBits - 1, 3) 375 val entryNeedCheck = toEnqPtrMask(j) && addrMatch && (datavalid(j) || listening(j) || miss(j)) 376 // TODO: update refilled data 377 val violationVec = (0 until 8).map(k => dataModule.io.rdata(j).mask(k) && io.storeIn(i).bits.mask(k)) 378 Cat(violationVec).orR() && entryNeedCheck 379 }))) 380 val lqViolation = lqViolationVec.asUInt().orR() 381 val lqViolationIndex = getFirstOne(lqViolationVec, RegNext(lqIdxMask)) 382 val lqViolationUop = uop(lqViolationIndex) 383 // lqViolationUop.lqIdx.flag := deqMask(lqViolationIndex) ^ deqPtrExt.flag 384 // lqViolationUop.lqIdx.value := lqViolationIndex 385 XSDebug(lqViolation, p"${Binary(Cat(lqViolationVec))}, $startIndex, $lqViolationIndex\n") 386 387 // when l/s writeback to roq together, check if rollback is needed 388 val wbViolationVec = RegNext(VecInit((0 until LoadPipelineWidth).map(j => { 389 io.loadIn(j).valid && 390 isAfter(io.loadIn(j).bits.uop.roqIdx, io.storeIn(i).bits.uop.roqIdx) && 391 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === io.loadIn(j).bits.paddr(PAddrBits - 1, 3) && 392 (io.storeIn(i).bits.mask & io.loadIn(j).bits.mask).orR 393 }))) 394 val wbViolation = wbViolationVec.asUInt().orR() 395 val wbViolationUop = getOldestInTwo(wbViolationVec, RegNext(VecInit(io.loadIn.map(_.bits.uop)))) 396 XSDebug(wbViolation, p"${Binary(Cat(wbViolationVec))}, $wbViolationUop\n") 397 398 // check if rollback is needed for load in l1 399 val l1ViolationVec = RegNext(VecInit((0 until LoadPipelineWidth).map(j => { 400 io.forward(j).valid && // L1 valid 401 isAfter(io.forward(j).uop.roqIdx, io.storeIn(i).bits.uop.roqIdx) && 402 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === io.forward(j).paddr(PAddrBits - 1, 3) && 403 (io.storeIn(i).bits.mask & io.forward(j).mask).orR 404 }))) 405 val l1Violation = l1ViolationVec.asUInt().orR() 406 val l1ViolationUop = getOldestInTwo(l1ViolationVec, RegNext(VecInit(io.forward.map(_.uop)))) 407 XSDebug(l1Violation, p"${Binary(Cat(l1ViolationVec))}, $l1ViolationUop\n") 408 409 val rollbackValidVec = Seq(lqViolation, wbViolation, l1Violation) 410 val rollbackUopVec = Seq(lqViolationUop, wbViolationUop, l1ViolationUop) 411 412 val mask = getAfterMask(rollbackValidVec, rollbackUopVec) 413 val oneAfterZero = mask(1)(0) 414 val rollbackUop = Mux(oneAfterZero && mask(2)(0), 415 rollbackUopVec(0), 416 Mux(!oneAfterZero && mask(2)(1), rollbackUopVec(1), rollbackUopVec(2))) 417 418 XSDebug( 419 l1Violation, 420 "need rollback (l4 load) pc %x roqidx %d target %x\n", 421 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, l1ViolationUop.roqIdx.asUInt 422 ) 423 XSDebug( 424 lqViolation, 425 "need rollback (ld wb before store) pc %x roqidx %d target %x\n", 426 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, lqViolationUop.roqIdx.asUInt 427 ) 428 XSDebug( 429 wbViolation, 430 "need rollback (ld/st wb together) pc %x roqidx %d target %x\n", 431 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, wbViolationUop.roqIdx.asUInt 432 ) 433 434 (RegNext(io.storeIn(i).valid) && Cat(rollbackValidVec).orR, rollbackUop) 435 } 436 437 // rollback check 438 val rollback = Wire(Vec(StorePipelineWidth, Valid(new MicroOp))) 439 for (i <- 0 until StorePipelineWidth) { 440 val detectedRollback = detectRollback(i) 441 rollback(i).valid := detectedRollback._1 442 rollback(i).bits := detectedRollback._2 443 } 444 445 def rollbackSel(a: Valid[MicroOp], b: Valid[MicroOp]): ValidIO[MicroOp] = { 446 Mux( 447 a.valid, 448 Mux( 449 b.valid, 450 Mux(isAfter(a.bits.roqIdx, b.bits.roqIdx), b, a), // a,b both valid, sel oldest 451 a // sel a 452 ), 453 b // sel b 454 ) 455 } 456 457 val rollbackSelected = ParallelOperation(rollback, rollbackSel) 458 val lastCycleRedirect = RegNext(io.brqRedirect) 459 460 io.rollback := DontCare 461 // Note that we use roqIdx - 1.U to flush the load instruction itself. 462 // Thus, here if last cycle's roqIdx equals to this cycle's roqIdx, it still triggers the redirect. 463 io.rollback.valid := rollbackSelected.valid && (!lastCycleRedirect.valid || !isAfter(rollbackSelected.bits.roqIdx, lastCycleRedirect.bits.roqIdx)) 464 465 io.rollback.bits.roqIdx := rollbackSelected.bits.roqIdx - 1.U 466 io.rollback.bits.isReplay := true.B 467 io.rollback.bits.isMisPred := false.B 468 io.rollback.bits.isException := false.B 469 io.rollback.bits.isFlushPipe := false.B 470 io.rollback.bits.target := rollbackSelected.bits.cf.pc 471 io.rollback.bits.brTag := rollbackSelected.bits.brTag 472 473 // Memory mapped IO / other uncached operations 474 475 // setup misc mem access req 476 // mask / paddr / data can be get from lq.data 477 val commitType = io.commits.uop(0).ctrl.commitType 478 io.uncache.req.valid := pending(deqPtr) && allocated(deqPtr) && 479 commitType === CommitType.LOAD && 480 io.roqDeqPtr === uop(deqPtr).roqIdx && 481 !io.commits.isWalk 482 483 io.uncache.req.bits.cmd := MemoryOpConstants.M_XRD 484 io.uncache.req.bits.addr := dataModule.io.rdata(deqPtr).paddr 485 io.uncache.req.bits.data := dataModule.io.rdata(deqPtr).data 486 io.uncache.req.bits.mask := dataModule.io.rdata(deqPtr).mask 487 488 io.uncache.req.bits.meta.id := DontCare // TODO: // FIXME 489 io.uncache.req.bits.meta.vaddr := DontCare 490 io.uncache.req.bits.meta.paddr := dataModule.io.rdata(deqPtr).paddr 491 io.uncache.req.bits.meta.uop := uop(deqPtr) 492 io.uncache.req.bits.meta.mmio := true.B // dataModule.io.rdata(deqPtr).mmio 493 io.uncache.req.bits.meta.tlb_miss := false.B 494 io.uncache.req.bits.meta.mask := dataModule.io.rdata(deqPtr).mask 495 io.uncache.req.bits.meta.replay := false.B 496 497 io.uncache.resp.ready := true.B 498 499 when (io.uncache.req.fire()) { 500 pending(deqPtr) := false.B 501 } 502 503 dataModule.io.uncache.wen := false.B 504 when(io.uncache.resp.fire()){ 505 datavalid(deqPtr) := true.B 506 dataModule.io.uncacheWrite(deqPtr, io.uncache.resp.bits.data(XLEN-1, 0)) 507 dataModule.io.uncache.wen := true.B 508 // TODO: write back exception info 509 } 510 511 when(io.uncache.req.fire()){ 512 XSDebug("uncache req: pc %x addr %x data %x op %x mask %x\n", 513 uop(deqPtr).cf.pc, 514 io.uncache.req.bits.addr, 515 io.uncache.req.bits.data, 516 io.uncache.req.bits.cmd, 517 io.uncache.req.bits.mask 518 ) 519 } 520 521 when(io.uncache.resp.fire()){ 522 XSDebug("uncache resp: data %x\n", io.dcache.resp.bits.data) 523 } 524 525 // Read vaddr for mem exception 526 io.exceptionAddr.vaddr := dataModule.io.rdata(io.exceptionAddr.lsIdx.lqIdx.value).vaddr 527 528 // misprediction recovery / exception redirect 529 // invalidate lq term using robIdx 530 val needCancel = Wire(Vec(LoadQueueSize, Bool())) 531 for (i <- 0 until LoadQueueSize) { 532 needCancel(i) := uop(i).roqIdx.needFlush(io.brqRedirect) && allocated(i) && !commited(i) 533 when(needCancel(i)) { 534 allocated(i) := false.B 535 } 536 } 537 val needCancelReg = RegNext(needCancel) 538 when (io.brqRedirect.valid) { 539 enqPtrExt := enqPtrExt 540 } 541 when (lastCycleRedirect.valid) { 542 enqPtrExt := enqPtrExt - PopCount(needCancelReg) 543 } 544 545 // assert(!io.rollback.valid) 546 when(io.rollback.valid) { 547 XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.pc, io.rollback.bits.roqIdx.asUInt) 548 } 549 550 // debug info 551 XSDebug("enqPtrExt %d:%d deqPtrExt %d:%d\n", enqPtrExt.flag, enqPtr, deqPtrExt.flag, deqPtr) 552 553 def PrintFlag(flag: Bool, name: String): Unit = { 554 when(flag) { 555 XSDebug(false, true.B, name) 556 }.otherwise { 557 XSDebug(false, true.B, " ") 558 } 559 } 560 561 for (i <- 0 until LoadQueueSize) { 562 if (i % 4 == 0) XSDebug("") 563 XSDebug(false, true.B, "%x [%x] ", uop(i).cf.pc, dataModule.io.rdata(i).paddr) 564 PrintFlag(allocated(i), "a") 565 PrintFlag(allocated(i) && datavalid(i), "v") 566 PrintFlag(allocated(i) && writebacked(i), "w") 567 PrintFlag(allocated(i) && commited(i), "c") 568 PrintFlag(allocated(i) && miss(i), "m") 569 PrintFlag(allocated(i) && listening(i), "l") 570 PrintFlag(allocated(i) && pending(i), "p") 571 XSDebug(false, true.B, " ") 572 if (i % 4 == 3 || i == LoadQueueSize - 1) XSDebug(false, true.B, "\n") 573 } 574 575} 576