xref: /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala (revision 0466583513e4c1ddbbb566b866b8963635acb20f) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils._
23import utility._
24import xiangshan._
25import xiangshan.backend.fu.fpu.FPU
26import xiangshan.backend.rob.RobLsqIO
27import xiangshan.cache._
28import xiangshan.frontend.FtqPtr
29import xiangshan.ExceptionNO._
30import xiangshan.mem.mdp._
31import xiangshan.backend.rob.RobPtr
32
33class LqPtr(implicit p: Parameters) extends CircularQueuePtr[LqPtr](
34  p => p(XSCoreParamsKey).VirtualLoadQueueSize
35){
36}
37
38object LqPtr {
39  def apply(f: Bool, v: UInt)(implicit p: Parameters): LqPtr = {
40    val ptr = Wire(new LqPtr)
41    ptr.flag := f
42    ptr.value := v
43    ptr
44  }
45}
46
47trait HasLoadHelper { this: XSModule =>
48  def rdataHelper(uop: MicroOp, rdata: UInt): UInt = {
49    val fpWen = uop.ctrl.fpWen
50    LookupTree(uop.ctrl.fuOpType, List(
51      LSUOpType.lb   -> SignExt(rdata(7, 0) , XLEN),
52      LSUOpType.lh   -> SignExt(rdata(15, 0), XLEN),
53      /*
54          riscv-spec-20191213: 12.2 NaN Boxing of Narrower Values
55          Any operation that writes a narrower result to an f register must write
56          all 1s to the uppermost FLEN−n bits to yield a legal NaN-boxed value.
57      */
58      LSUOpType.lw   -> Mux(fpWen, FPU.box(rdata, FPU.S), SignExt(rdata(31, 0), XLEN)),
59      LSUOpType.ld   -> Mux(fpWen, FPU.box(rdata, FPU.D), SignExt(rdata(63, 0), XLEN)),
60      LSUOpType.lbu  -> ZeroExt(rdata(7, 0) , XLEN),
61      LSUOpType.lhu  -> ZeroExt(rdata(15, 0), XLEN),
62      LSUOpType.lwu  -> ZeroExt(rdata(31, 0), XLEN),
63    ))
64  }
65}
66
67class LqEnqIO(implicit p: Parameters) extends XSBundle {
68  val canAccept = Output(Bool())
69  val sqCanAccept = Input(Bool())
70  val needAlloc = Vec(exuParameters.LsExuCnt, Input(Bool()))
71  val req = Vec(exuParameters.LsExuCnt, Flipped(ValidIO(new MicroOp)))
72  val resp = Vec(exuParameters.LsExuCnt, Output(new LqPtr))
73}
74
75class LqTriggerIO(implicit p: Parameters) extends XSBundle {
76  val hitLoadAddrTriggerHitVec = Input(Vec(3, Bool()))
77  val lqLoadAddrTriggerHitVec = Output(Vec(3, Bool()))
78}
79
80
81
82class LoadQueue(implicit p: Parameters) extends XSModule
83  with HasDCacheParameters
84  with HasCircularQueuePtrHelper
85  with HasLoadHelper
86  with HasPerfEvents
87{
88  val io = IO(new Bundle() {
89    val redirect = Flipped(Valid(new Redirect))
90    val enq = new LqEnqIO
91    val ldu = new Bundle() {
92        val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2
93        val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2
94        val ldin         = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3
95    }
96    val sta = new Bundle() {
97      val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1
98    }
99    val std = new Bundle() {
100      val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new ExuOutput))) // from store_s0, store data, send to sq from rs
101    }
102    val sq = new Bundle() {
103      val stAddrReadySqPtr = Input(new SqPtr)
104      val stAddrReadyVec   = Input(Vec(StoreQueueSize, Bool()))
105      val stDataReadySqPtr = Input(new SqPtr)
106      val stDataReadyVec   = Input(Vec(StoreQueueSize, Bool()))
107      val stIssuePtr       = Input(new SqPtr)
108      val sqEmpty          = Input(Bool())
109    }
110    val ldout = Vec(LoadPipelineWidth, DecoupledIO(new ExuOutput))
111    val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle))
112    val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle))
113    val refill = Flipped(ValidIO(new Refill))
114    val release = Flipped(Valid(new Release))
115    val rollback = Output(Valid(new Redirect))
116    val rob = Flipped(new RobLsqIO)
117    val uncache = new UncacheWordIO
118    val trigger = Vec(LoadPipelineWidth, new LqTriggerIO)
119    val exceptionAddr = new ExceptionAddrIO
120    val lqFull = Output(Bool())
121    val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W))
122    val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W))
123    val lq_rep_full = Output(Bool())
124    val tlbReplayDelayCycleCtrl = Vec(4, Input(UInt(ReSelectLen.W)))
125    val l2_hint = Input(Valid(new L2ToL1Hint()))
126  })
127
128  val loadQueueRAR = Module(new LoadQueueRAR)  //  read-after-read violation
129  val loadQueueRAW = Module(new LoadQueueRAW)  //  read-after-write violation
130  val loadQueueReplay = Module(new LoadQueueReplay)  //  enqueue if need replay
131  val virtualLoadQueue = Module(new VirtualLoadQueue)  //  control state
132  val exceptionBuffer = Module(new LqExceptionBuffer) // exception buffer
133  val uncacheBuffer = Module(new UncacheBuffer) // uncache buffer
134
135  /**
136   * LoadQueueRAR
137   */
138  loadQueueRAR.io.redirect <> io.redirect
139  loadQueueRAR.io.release  <> io.release
140  loadQueueRAR.io.ldWbPtr  <> virtualLoadQueue.io.ldWbPtr
141  for (w <- 0 until LoadPipelineWidth) {
142    loadQueueRAR.io.query(w).req    <> io.ldu.ldld_nuke_query(w).req // from load_s1
143    loadQueueRAR.io.query(w).resp   <> io.ldu.ldld_nuke_query(w).resp // to load_s2
144    loadQueueRAR.io.query(w).revoke := io.ldu.ldld_nuke_query(w).revoke // from load_s3
145  }
146
147  /**
148   * LoadQueueRAW
149   */
150  loadQueueRAW.io.redirect         <> io.redirect
151  loadQueueRAW.io.storeIn          <> io.sta.storeAddrIn
152  loadQueueRAW.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr
153  loadQueueRAW.io.stIssuePtr       <> io.sq.stIssuePtr
154  for (w <- 0 until LoadPipelineWidth) {
155    loadQueueRAW.io.query(w).req    <> io.ldu.stld_nuke_query(w).req // from load_s1
156    loadQueueRAW.io.query(w).resp   <> io.ldu.stld_nuke_query(w).resp // to load_s2
157    loadQueueRAW.io.query(w).revoke := io.ldu.stld_nuke_query(w).revoke // from load_s3
158  }
159
160  /**
161   * VirtualLoadQueue
162   */
163  virtualLoadQueue.io.redirect    <> io.redirect
164  virtualLoadQueue.io.enq         <> io.enq
165  virtualLoadQueue.io.ldin        <> io.ldu.ldin // from load_s3
166  virtualLoadQueue.io.lqFull      <> io.lqFull
167  virtualLoadQueue.io.lqDeq       <> io.lqDeq
168  virtualLoadQueue.io.lqCancelCnt <> io.lqCancelCnt
169
170  /**
171   * Load queue exception buffer
172   */
173  exceptionBuffer.io.redirect <> io.redirect
174  for ((buff, w) <- exceptionBuffer.io.req.zipWithIndex) {
175    buff.valid := io.ldu.ldin(w).valid // from load_s3
176    buff.bits := io.ldu.ldin(w).bits
177  }
178  io.exceptionAddr <> exceptionBuffer.io.exceptionAddr
179
180  /**
181   * Load uncache buffer
182   */
183  uncacheBuffer.io.redirect   <> io.redirect
184  uncacheBuffer.io.ldout      <> io.ldout
185  uncacheBuffer.io.ld_raw_data  <> io.ld_raw_data
186  uncacheBuffer.io.rob        <> io.rob
187  uncacheBuffer.io.uncache    <> io.uncache
188  uncacheBuffer.io.trigger    <> io.trigger
189  for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) {
190    buff.valid := io.ldu.ldin(w).valid // from load_s3
191    buff.bits := io.ldu.ldin(w).bits // from load_s3
192  }
193
194  // rollback
195  def selectOldest[T <: Redirect](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = {
196    assert(valid.length == bits.length)
197    if (valid.length == 0 || valid.length == 1) {
198      (valid, bits)
199    } else if (valid.length == 2) {
200      val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0)))))
201      for (i <- res.indices) {
202        res(i).valid := valid(i)
203        res(i).bits := bits(i)
204      }
205      val oldest = Mux(valid(0) && valid(1), Mux(isAfter(bits(0).robIdx, bits(1).robIdx), res(1), res(0)), Mux(valid(0) && !valid(1), res(0), res(1)))
206      (Seq(oldest.valid), Seq(oldest.bits))
207    } else {
208      val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2))
209      val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2)))
210      selectOldest(left._1 ++ right._1, left._2 ++ right._2)
211    }
212  }
213
214  val (rollbackSelV, rollbackSelBits) = selectOldest(
215                                          Seq(loadQueueRAW.io.rollback.valid, uncacheBuffer.io.rollback.valid),
216                                          Seq(loadQueueRAW.io.rollback.bits, uncacheBuffer.io.rollback.bits)
217                                        )
218  io.rollback.valid := rollbackSelV.head
219  io.rollback.bits := rollbackSelBits.head
220
221  /* <------- DANGEROUS: Don't change sequence here ! -------> */
222
223  /**
224   * LoadQueueReplay
225   */
226  loadQueueReplay.io.redirect         <> io.redirect
227  loadQueueReplay.io.enq              <> io.ldu.ldin // from load_s3
228  loadQueueReplay.io.storeAddrIn      <> io.sta.storeAddrIn // from store_s1
229  loadQueueReplay.io.storeDataIn      <> io.std.storeDataIn // from store_s0
230  loadQueueReplay.io.replay           <> io.replay
231  loadQueueReplay.io.refill           <> io.refill
232  loadQueueReplay.io.stAddrReadySqPtr <> io.sq.stAddrReadySqPtr
233  loadQueueReplay.io.stAddrReadyVec   <> io.sq.stAddrReadyVec
234  loadQueueReplay.io.stDataReadySqPtr <> io.sq.stDataReadySqPtr
235  loadQueueReplay.io.stDataReadyVec   <> io.sq.stDataReadyVec
236  loadQueueReplay.io.sqEmpty          <> io.sq.sqEmpty
237  loadQueueReplay.io.lqFull           <> io.lq_rep_full
238  loadQueueReplay.io.ldWbPtr          <> virtualLoadQueue.io.ldWbPtr
239  loadQueueReplay.io.rarFull          <> loadQueueRAR.io.lqFull
240  loadQueueReplay.io.rawFull          <> loadQueueRAW.io.lqFull
241  loadQueueReplay.io.l2_hint          <> io.l2_hint
242  loadQueueReplay.io.tlbReplayDelayCycleCtrl <> io.tlbReplayDelayCycleCtrl
243
244  val full_mask = Cat(loadQueueRAR.io.lqFull, loadQueueRAW.io.lqFull, loadQueueReplay.io.lqFull)
245  XSPerfAccumulate("full_mask_000", full_mask === 0.U)
246  XSPerfAccumulate("full_mask_001", full_mask === 1.U)
247  XSPerfAccumulate("full_mask_010", full_mask === 2.U)
248  XSPerfAccumulate("full_mask_011", full_mask === 3.U)
249  XSPerfAccumulate("full_mask_100", full_mask === 4.U)
250  XSPerfAccumulate("full_mask_101", full_mask === 5.U)
251  XSPerfAccumulate("full_mask_110", full_mask === 6.U)
252  XSPerfAccumulate("full_mask_111", full_mask === 7.U)
253  XSPerfAccumulate("rollback", io.rollback.valid)
254
255  // perf cnt
256  val perfEvents = Seq(virtualLoadQueue, loadQueueRAR, loadQueueRAW, loadQueueReplay).flatMap(_.getPerfEvents) ++
257  Seq(
258    ("full_mask_000", full_mask === 0.U),
259    ("full_mask_001", full_mask === 1.U),
260    ("full_mask_010", full_mask === 2.U),
261    ("full_mask_011", full_mask === 3.U),
262    ("full_mask_100", full_mask === 4.U),
263    ("full_mask_101", full_mask === 5.U),
264    ("full_mask_110", full_mask === 6.U),
265    ("full_mask_111", full_mask === 7.U),
266    ("rollback", io.rollback.valid)
267  )
268  generatePerfEvent()
269  // end
270}