xref: /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala (revision b03c55a5df5dc8793cb44b42dd60141566e57e78) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils._
23import utility._
24import xiangshan._
25import xiangshan.backend.fu.FuConfig._
26import xiangshan.backend.fu.fpu.FPU
27import xiangshan.backend.rob.RobLsqIO
28import xiangshan.cache._
29import xiangshan.frontend.FtqPtr
30import xiangshan.ExceptionNO._
31import xiangshan.cache.wpu.ReplayCarry
32import xiangshan.backend.rob.RobPtr
33
34class LqExceptionBuffer(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper {
35  val enqPortNum = LoadPipelineWidth + VecLoadPipelineWidth + 1 // 1 for mmio bus non-data error
36
37  val io = IO(new Bundle() {
38    val redirect      = Flipped(Valid(new Redirect))
39    val req           = Vec(enqPortNum, Flipped(Valid(new LqWriteBundle)))
40    val exceptionAddr = new ExceptionAddrIO
41  })
42
43  val req_valid = RegInit(false.B)
44  val req = Reg(new LqWriteBundle)
45
46  // enqueue
47  // s1:
48  val s1_req = VecInit(io.req.map(_.bits))
49  val s1_valid = VecInit(io.req.map(x => x.valid))
50
51  // s2: delay 1 cycle
52  val s2_req = (0 until enqPortNum).map(i => {
53    RegEnable(s1_req(i), s1_valid(i))})
54  val s2_valid = (0 until enqPortNum).map(i =>
55    RegNext(s1_valid(i)) &&
56    !s2_req(i).uop.robIdx.needFlush(RegNext(io.redirect)) &&
57    !s2_req(i).uop.robIdx.needFlush(io.redirect)
58  )
59  val s2_has_exception = s2_req.map(x => ExceptionNO.selectByFu(x.uop.exceptionVec, LduCfg).asUInt.orR)
60
61  val s2_enqueue = Wire(Vec(enqPortNum, Bool()))
62  for (w <- 0 until enqPortNum) {
63    s2_enqueue(w) := s2_valid(w) && s2_has_exception(w)
64  }
65
66  when (req_valid && req.uop.robIdx.needFlush(io.redirect)) {
67    req_valid := s2_enqueue.asUInt.orR
68  } .elsewhen (s2_enqueue.asUInt.orR) {
69    req_valid := req_valid || true.B
70  }
71
72  def selectOldest[T <: LqWriteBundle](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = {
73    assert(valid.length == bits.length)
74    if (valid.length == 0 || valid.length == 1) {
75      (valid, bits)
76    } else if (valid.length == 2) {
77      val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0)))))
78      for (i <- res.indices) {
79        res(i).valid := valid(i)
80        res(i).bits := bits(i)
81      }
82      val oldest = Mux(valid(0) && valid(1),
83        Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) ||
84          (isNotBefore(bits(0).uop.robIdx, bits(1).uop.robIdx) && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)),
85        Mux(valid(0) && !valid(1), res(0), res(1)))
86      (Seq(oldest.valid), Seq(oldest.bits))
87    } else {
88      val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2))
89      val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2)))
90      selectOldest(left._1 ++ right._1, left._2 ++ right._2)
91    }
92  }
93
94  val reqSel = selectOldest(s2_enqueue, s2_req)
95
96  when (req_valid) {
97    req := Mux(
98      reqSel._1(0) && (isAfter(req.uop.robIdx, reqSel._2(0).uop.robIdx) || (isNotBefore(req.uop.robIdx, reqSel._2(0).uop.robIdx) && req.uop.uopIdx > reqSel._2(0).uop.uopIdx)),
99      reqSel._2(0),
100      req)
101  } .elsewhen (s2_enqueue.asUInt.orR) {
102    req := reqSel._2(0)
103  }
104
105  io.exceptionAddr.vaddr := req.vaddr
106  io.exceptionAddr.vstart := req.uop.vpu.vstart
107  io.exceptionAddr.vl     := req.uop.vpu.vl
108  io.exceptionAddr.gpaddr := req.gpaddr
109  XSPerfAccumulate("exception", !RegNext(req_valid) && req_valid)
110
111  // end
112}