1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants} 9import xiangshan.backend.LSUOpType 10import xiangshan.mem._ 11import xiangshan.backend.roq.RoqLsqIO 12 13class ExceptionAddrIO extends XSBundle { 14 val lsIdx = Input(new LSIdx) 15 val isStore = Input(Bool()) 16 val vaddr = Output(UInt(VAddrBits.W)) 17} 18 19class FwdEntry extends XSBundle { 20 val valid = Bool() 21 val data = UInt(8.W) 22} 23 24// inflight miss block reqs 25class InflightBlockInfo extends XSBundle { 26 val block_addr = UInt(PAddrBits.W) 27 val valid = Bool() 28} 29 30class LsqEnqIO extends XSBundle { 31 val canAccept = Output(Bool()) 32 val needAlloc = Vec(RenameWidth, Input(Bool())) 33 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 34 val resp = Vec(RenameWidth, Output(new LSIdx)) 35} 36 37// Load / Store Queue Wrapper for XiangShan Out of Order LSU 38class LsqWrappper extends XSModule with HasDCacheParameters { 39 val io = IO(new Bundle() { 40 val enq = new LsqEnqIO 41 val brqRedirect = Flipped(ValidIO(new Redirect)) 42 val flush = Input(Bool()) 43 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 44 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 45 val loadDataForwarded = Vec(LoadPipelineWidth, Input(Bool())) 46 val needReplayFromRS = Vec(LoadPipelineWidth, Input(Bool())) 47 val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReq)) 48 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load 49 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 50 val forward = Vec(LoadPipelineWidth, Flipped(new MaskedLoadForwardQueryIO)) 51 val roq = Flipped(new RoqLsqIO) 52 val rollback = Output(Valid(new Redirect)) 53 val dcache = Flipped(ValidIO(new Refill)) 54 val uncache = new DCacheWordIO 55 val exceptionAddr = new ExceptionAddrIO 56 val sqempty = Output(Bool()) 57 }) 58 val difftestIO = IO(new Bundle() { 59 val fromSQ = new Bundle() { 60 val storeCommit = Output(UInt(2.W)) 61 val storeAddr = Output(Vec(2, UInt(64.W))) 62 val storeData = Output(Vec(2, UInt(64.W))) 63 val storeMask = Output(Vec(2, UInt(8.W))) 64 } 65 }) 66 difftestIO <> DontCare 67 68 val loadQueue = Module(new LoadQueue) 69 val storeQueue = Module(new StoreQueue) 70 71 // io.enq logic 72 // LSQ: send out canAccept when both load queue and store queue are ready 73 // Dispatch: send instructions to LSQ only when they are ready 74 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 75 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 76 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 77 for (i <- 0 until RenameWidth) { 78 val isStore = CommitType.lsInstIsStore(io.enq.req(i).bits.ctrl.commitType) 79 80 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i) && !isStore 81 loadQueue.io.enq.req(i).valid := !isStore && io.enq.req(i).valid 82 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 83 84 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i) && isStore 85 storeQueue.io.enq.req(i).valid := isStore && io.enq.req(i).valid 86 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 87 88 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 89 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 90 } 91 92 // load queue wiring 93 loadQueue.io.brqRedirect <> io.brqRedirect 94 loadQueue.io.flush <> io.flush 95 loadQueue.io.loadIn <> io.loadIn 96 loadQueue.io.storeIn <> io.storeIn 97 loadQueue.io.loadDataForwarded <> io.loadDataForwarded 98 loadQueue.io.needReplayFromRS <> io.needReplayFromRS 99 loadQueue.io.ldout <> io.ldout 100 loadQueue.io.roq <> io.roq 101 loadQueue.io.rollback <> io.rollback 102 loadQueue.io.dcache <> io.dcache 103 loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 104 loadQueue.io.exceptionAddr.isStore := DontCare 105 106 // store queue wiring 107 // storeQueue.io <> DontCare 108 storeQueue.io.brqRedirect <> io.brqRedirect 109 storeQueue.io.flush <> io.flush 110 storeQueue.io.storeIn <> io.storeIn 111 storeQueue.io.sbuffer <> io.sbuffer 112 storeQueue.io.mmioStout <> io.mmioStout 113 storeQueue.io.roq <> io.roq 114 storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 115 storeQueue.io.exceptionAddr.isStore := DontCare 116 117 loadQueue.io.load_s1 <> io.forward 118 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 119 120 storeQueue.io.sqempty <> io.sqempty 121 122 if (!env.FPGAPlatform) { 123 difftestIO.fromSQ <> storeQueue.difftestIO 124 } 125 126 io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 127 128 // naive uncache arbiter 129 val s_idle :: s_load :: s_store :: Nil = Enum(3) 130 val pendingstate = RegInit(s_idle) 131 132 switch(pendingstate){ 133 is(s_idle){ 134 when(io.uncache.req.fire()){ 135 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, s_store) 136 } 137 } 138 is(s_load){ 139 when(io.uncache.resp.fire()){ 140 pendingstate := s_idle 141 } 142 } 143 is(s_store){ 144 when(io.uncache.resp.fire()){ 145 pendingstate := s_idle 146 } 147 } 148 } 149 150 loadQueue.io.uncache := DontCare 151 storeQueue.io.uncache := DontCare 152 loadQueue.io.uncache.resp.valid := false.B 153 storeQueue.io.uncache.resp.valid := false.B 154 when(loadQueue.io.uncache.req.valid){ 155 io.uncache.req <> loadQueue.io.uncache.req 156 }.otherwise{ 157 io.uncache.req <> storeQueue.io.uncache.req 158 } 159 when(pendingstate === s_load){ 160 io.uncache.resp <> loadQueue.io.uncache.resp 161 }.otherwise{ 162 io.uncache.resp <> storeQueue.io.uncache.resp 163 } 164 165 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 166 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 167 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 168 169} 170