1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, MemExuOutput} 26import xiangshan.backend._ 27import xiangshan.backend.rob.RobLsqIO 28import xiangshan.backend.fu.FuType 29import xiangshan.mem.Bundles._ 30import xiangshan.cache._ 31import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 32import xiangshan.cache.{CMOReq, CMOResp} 33import xiangshan.cache.mmu.{TlbRequestIO, TlbHintIO} 34 35class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 36 val isStore = Input(Bool()) 37 val vaddr = Output(UInt(XLEN.W)) 38 val vaNeedExt = Output(Bool()) 39 val isHyper = Output(Bool()) 40 val vstart = Output(UInt((log2Up(VLEN) + 1).W)) 41 val vl = Output(UInt((log2Up(VLEN) + 1).W)) 42 val gpaddr = Output(UInt(XLEN.W)) 43 val isForVSnonLeafPTE = Output(Bool()) 44} 45 46class FwdEntry extends Bundle { 47 val validFast = Bool() // validFast is generated the same cycle with query 48 val valid = Bool() // valid is generated 1 cycle after query request 49 val data = UInt(8.W) // data is generated 1 cycle after query request 50} 51 52// inflight miss block reqs 53class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 54 val block_addr = UInt(PAddrBits.W) 55 val valid = Bool() 56} 57 58class LsqEnqIO(implicit p: Parameters) extends MemBlockBundle { 59 val canAccept = Output(Bool()) 60 val needAlloc = Vec(LSQEnqWidth, Input(UInt(2.W))) 61 val req = Vec(LSQEnqWidth, Flipped(ValidIO(new DynInst))) 62 val iqAccept = Input(Vec(LSQEnqWidth, Bool())) 63 val resp = Vec(LSQEnqWidth, Output(new LSIdx)) 64} 65 66// Load / Store Queue Wrapper for XiangShan Out of Order LSU 67class LsqWrapper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 68 val io = IO(new Bundle() { 69 val hartId = Input(UInt(hartIdLen.W)) 70 val brqRedirect = Flipped(ValidIO(new Redirect)) 71 val stvecFeedback = Vec(VecStorePipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO))) 72 val ldvecFeedback = Vec(VecLoadPipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO))) 73 val enq = new LsqEnqIO 74 val ldu = new Bundle() { 75 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 76 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 77 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 78 } 79 val sta = new Bundle() { 80 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // from store_s0, store mask, send to sq from rs 81 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 82 val storeAddrInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) // from store_s2 83 } 84 val std = new Bundle() { 85 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput(isVector = true)))) // from store_s0, store data, send to sq from rs 86 } 87 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 88 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 89 val ncOut = Vec(LoadPipelineWidth, DecoupledIO(new LsPipelineBundle)) 90 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 91 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddrAndPfFlag)) 92 val sbufferVecDifftestInfo = Vec(EnsbufferWidth, Decoupled(new DynInst)) // The vector store difftest needs is 93 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 94 val rob = Flipped(new RobLsqIO) 95 val nuke_rollback = Vec(StorePipelineWidth, Output(Valid(new Redirect))) 96 val nack_rollback = Vec(1, Output(Valid(new Redirect))) // uncahce 97 val release = Flipped(Valid(new Release)) 98 // val refill = Flipped(Valid(new Refill)) 99 val tl_d_channel = Input(new DcacheToLduForwardIO) 100 val maControl = Flipped(new StoreMaBufToSqControlIO) 101 val uncacheOutstanding = Input(Bool()) 102 val uncache = new UncacheWordIO 103 val mmioStout = DecoupledIO(new MemExuOutput) // writeback uncached store 104 // TODO: implement vector store 105 val vecmmioStout = DecoupledIO(new MemExuOutput(isVector = true)) // vec writeback uncached store 106 val sqEmpty = Output(Bool()) 107 val lq_rep_full = Output(Bool()) 108 val sqFull = Output(Bool()) 109 val lqFull = Output(Bool()) 110 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize+1).W)) 111 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 112 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 113 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 114 val lqCanAccept = Output(Bool()) 115 val sqCanAccept = Output(Bool()) 116 val lqDeqPtr = Output(new LqPtr) 117 val sqDeqPtr = Output(new SqPtr) 118 val exceptionAddr = new ExceptionAddrIO 119 val loadMisalignFull = Input(Bool()) 120 val issuePtrExt = Output(new SqPtr) 121 val l2_hint = Input(Valid(new L2ToL1Hint())) 122 val tlb_hint = Flipped(new TlbHintIO) 123 val cmoOpReq = DecoupledIO(new CMOReq) 124 val cmoOpResp = Flipped(DecoupledIO(new CMOResp)) 125 val flushSbuffer = new SbufferFlushBundle 126 val force_write = Output(Bool()) 127 val lqEmpty = Output(Bool()) 128 129 // top-down 130 val debugTopDown = new LoadQueueTopDownIO 131 val noUopsIssued = Input(Bool()) 132 }) 133 134 val loadQueue = Module(new LoadQueue) 135 val storeQueue = Module(new StoreQueue) 136 137 storeQueue.io.hartId := io.hartId 138 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 139 140 if (backendParams.debugEn){ dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) } 141 142 // Todo: imm 143 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(14.U(ReSelectLen.W), 0.U(ReSelectLen.W), 125.U(ReSelectLen.W), 0.U(ReSelectLen.W)))) 144 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 145 146 // io.enq logic 147 // LSQ: send out canAccept when both load queue and store queue are ready 148 // Dispatch: send instructions to LSQ only when they are ready 149 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 150 io.lqCanAccept := loadQueue.io.enq.canAccept 151 io.sqCanAccept := storeQueue.io.enq.canAccept 152 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 153 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 154 io.lqDeqPtr := loadQueue.io.lqDeqPtr 155 io.sqDeqPtr := storeQueue.io.sqDeqPtr 156 for (i <- io.enq.req.indices) { 157 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 158 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 159 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 160 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 161 162 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 163 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 164 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 165 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 166 167 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 168 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 169 } 170 171 // store queue wiring 172 storeQueue.io.brqRedirect <> io.brqRedirect 173 storeQueue.io.vecFeedback <> io.stvecFeedback 174 storeQueue.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 175 storeQueue.io.storeAddrInRe <> io.sta.storeAddrInRe // from store_s2 176 storeQueue.io.storeDataIn <> io.std.storeDataIn // from store_s0 177 storeQueue.io.storeMaskIn <> io.sta.storeMaskIn // from store_s0 178 storeQueue.io.sbuffer <> io.sbuffer 179 storeQueue.io.sbufferVecDifftestInfo <> io.sbufferVecDifftestInfo 180 storeQueue.io.mmioStout <> io.mmioStout 181 storeQueue.io.vecmmioStout <> io.vecmmioStout 182 storeQueue.io.rob <> io.rob 183 storeQueue.io.exceptionAddr.isStore := DontCare 184 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 185 storeQueue.io.sqDeq <> io.sqDeq 186 storeQueue.io.sqEmpty <> io.sqEmpty 187 storeQueue.io.sqFull <> io.sqFull 188 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 189 storeQueue.io.force_write <> io.force_write 190 storeQueue.io.cmoOpReq <> io.cmoOpReq 191 storeQueue.io.cmoOpResp <> io.cmoOpResp 192 storeQueue.io.flushSbuffer <> io.flushSbuffer 193 storeQueue.io.maControl <> io.maControl 194 195 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 196 197 // load queue wiring 198 loadQueue.io.redirect <> io.brqRedirect 199 loadQueue.io.vecFeedback <> io.ldvecFeedback 200 loadQueue.io.ldu <> io.ldu 201 loadQueue.io.ldout <> io.ldout 202 loadQueue.io.ld_raw_data <> io.ld_raw_data 203 loadQueue.io.ncOut <> io.ncOut 204 loadQueue.io.rob <> io.rob 205 loadQueue.io.nuke_rollback <> io.nuke_rollback 206 loadQueue.io.nack_rollback <> io.nack_rollback 207 loadQueue.io.replay <> io.replay 208 // loadQueue.io.refill <> io.refill 209 loadQueue.io.tl_d_channel <> io.tl_d_channel 210 loadQueue.io.release <> io.release 211 loadQueue.io.exceptionAddr.isStore := DontCare 212 loadQueue.io.loadMisalignFull := io.loadMisalignFull 213 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 214 loadQueue.io.sq.stAddrReadySqPtr <> storeQueue.io.stAddrReadySqPtr 215 loadQueue.io.sq.stAddrReadyVec <> storeQueue.io.stAddrReadyVec 216 loadQueue.io.sq.stDataReadySqPtr <> storeQueue.io.stDataReadySqPtr 217 loadQueue.io.sq.stDataReadyVec <> storeQueue.io.stDataReadyVec 218 loadQueue.io.sq.stIssuePtr <> storeQueue.io.stIssuePtr 219 loadQueue.io.sq.sqEmpty <> storeQueue.io.sqEmpty 220 loadQueue.io.sta.storeAddrIn <> io.sta.storeAddrIn // store_s1 221 loadQueue.io.std.storeDataIn <> io.std.storeDataIn // store_s0 222 loadQueue.io.lqFull <> io.lqFull 223 loadQueue.io.lq_rep_full <> io.lq_rep_full 224 loadQueue.io.lqDeq <> io.lqDeq 225 loadQueue.io.l2_hint <> io.l2_hint 226 loadQueue.io.tlb_hint <> io.tlb_hint 227 loadQueue.io.lqEmpty <> io.lqEmpty 228 229 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 230 // s0: commit 231 // s1: exception find 232 // s2: exception triggered 233 // s3: ptr updated & new address 234 // address will be used at the next cycle after exception is triggered 235 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 236 io.exceptionAddr.vaNeedExt := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaNeedExt, loadQueue.io.exceptionAddr.vaNeedExt) 237 io.exceptionAddr.isHyper := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.isHyper, loadQueue.io.exceptionAddr.isHyper) 238 io.exceptionAddr.vstart := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vstart, loadQueue.io.exceptionAddr.vstart) 239 io.exceptionAddr.vl := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vl, loadQueue.io.exceptionAddr.vl) 240 io.exceptionAddr.gpaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.gpaddr, loadQueue.io.exceptionAddr.gpaddr) 241 io.exceptionAddr.isForVSnonLeafPTE:= Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.isForVSnonLeafPTE, loadQueue.io.exceptionAddr.isForVSnonLeafPTE) 242 io.issuePtrExt := storeQueue.io.stAddrReadySqPtr 243 244 // naive uncache arbiter 245 val s_idle :: s_load :: s_store :: Nil = Enum(3) 246 val pendingstate = RegInit(s_idle) 247 248 switch(pendingstate){ 249 is(s_idle){ 250 when(io.uncache.req.fire){ 251 pendingstate := 252 Mux(io.uncacheOutstanding && io.uncache.req.bits.nc, s_idle, 253 Mux(loadQueue.io.uncache.req.valid, s_load, 254 s_store)) 255 } 256 } 257 is(s_load){ 258 when(io.uncache.resp.fire){ 259 pendingstate := s_idle 260 } 261 } 262 is(s_store){ 263 when(io.uncache.resp.fire){ 264 pendingstate := s_idle 265 } 266 } 267 } 268 269 loadQueue.io.uncache := DontCare 270 storeQueue.io.uncache := DontCare 271 loadQueue.io.uncache.req.ready := false.B 272 storeQueue.io.uncache.req.ready := false.B 273 loadQueue.io.uncache.resp.valid := false.B 274 loadQueue.io.uncache.idResp.valid := false.B 275 storeQueue.io.uncache.resp.valid := false.B 276 storeQueue.io.uncache.idResp.valid := false.B 277 when(pendingstate === s_idle){ 278 when(loadQueue.io.uncache.req.valid){ 279 io.uncache.req <> loadQueue.io.uncache.req 280 }.otherwise{ 281 io.uncache.req <> storeQueue.io.uncache.req 282 } 283 }.otherwise{ 284 io.uncache.req.valid := false.B 285 io.uncache.req.bits := DontCare 286 } 287 when (io.uncache.resp.bits.is2lq) { 288 io.uncache.resp <> loadQueue.io.uncache.resp 289 } .otherwise { 290 io.uncache.resp <> storeQueue.io.uncache.resp 291 } 292 when(io.uncache.idResp.bits.is2lq) { 293 loadQueue.io.uncache.idResp <> io.uncache.idResp 294 }.otherwise { 295 storeQueue.io.uncache.idResp <> io.uncache.idResp 296 } 297 298 loadQueue.io.debugTopDown <> io.debugTopDown 299 loadQueue.io.noUopsIssed := io.noUopsIssued 300 301 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 302 assert(!(loadQueue.io.uncache.idResp.valid && storeQueue.io.uncache.idResp.valid)) 303 when (!io.uncacheOutstanding) { 304 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 305 } 306 307 308 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 309 generatePerfEvent() 310} 311 312class LsqEnqCtrl(implicit p: Parameters) extends XSModule 313 with HasVLSUParameters { 314 val io = IO(new Bundle { 315 val redirect = Flipped(ValidIO(new Redirect)) 316 // to dispatch 317 val enq = new LsqEnqIO 318 // from `memBlock.io.lqDeq 319 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 320 // from `memBlock.io.sqDeq` 321 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 322 // from/tp lsq 323 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 324 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 325 val lqFreeCount = Output(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 326 val sqFreeCount = Output(UInt(log2Up(StoreQueueSize + 1).W)) 327 val enqLsq = Flipped(new LsqEnqIO) 328 }) 329 330 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 331 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 332 val lqCounter = RegInit(VirtualLoadQueueSize.U(log2Up(VirtualLoadQueueSize + 1).W)) 333 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 334 val canAccept = RegInit(false.B) 335 336 val blockVec = io.enq.iqAccept.map(!_) :+ true.B 337 val numLsElem = io.enq.req.map(_.bits.numLsElem) 338 val needEnqLoadQueue = VecInit(io.enq.req.map(x => x.valid && (FuType.isLoad(x.bits.fuType) || FuType.isVNonsegLoad(x.bits.fuType)))) 339 val needEnqStoreQueue = VecInit(io.enq.req.map(x => x.valid && (FuType.isStore(x.bits.fuType) || FuType.isVNonsegStore(x.bits.fuType)))) 340 val loadQueueElem = needEnqLoadQueue.zip(numLsElem).map(x => Mux(x._1, x._2, 0.U)) 341 val storeQueueElem = needEnqStoreQueue.zip(numLsElem).map(x => Mux(x._1, x._2, 0.U)) 342 val loadFlowPopCount = 0.U +: loadQueueElem.zipWithIndex.map{ case (l, i) => 343 loadQueueElem.take(i + 1).reduce(_ +& _).asTypeOf(UInt(elemIdxBits.W)) 344 } 345 val storeFlowPopCount = 0.U +: storeQueueElem.zipWithIndex.map { case (s, i) => 346 storeQueueElem.take(i + 1).reduce(_ +& _).asTypeOf(UInt(elemIdxBits.W)) 347 } 348 val lqAllocNumber = PriorityMux(blockVec.zip(loadFlowPopCount)) 349 val sqAllocNumber = PriorityMux(blockVec.zip(storeFlowPopCount)) 350 351 io.lqFreeCount := lqCounter 352 io.sqFreeCount := sqCounter 353 // How to update ptr and counter: 354 // (1) by default, updated according to enq/commit 355 // (2) when redirect and dispatch queue is empty, update according to lsq 356 val t1_redirect = RegNext(io.redirect.valid) 357 val t2_redirect = RegNext(t1_redirect) 358 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 359 val t3_update = RegNext(t2_update) 360 val t3_lqCancelCnt = GatedRegNext(io.lqCancelCnt) 361 val t3_sqCancelCnt = GatedRegNext(io.sqCancelCnt) 362 when (t3_update) { 363 lqPtr := lqPtr - t3_lqCancelCnt 364 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 365 sqPtr := sqPtr - t3_sqCancelCnt 366 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 367 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 368 lqPtr := lqPtr + lqAllocNumber 369 lqCounter := lqCounter + io.lcommit - lqAllocNumber 370 sqPtr := sqPtr + sqAllocNumber 371 sqCounter := sqCounter + io.scommit - sqAllocNumber 372 }.otherwise { 373 lqCounter := lqCounter + io.lcommit 374 sqCounter := sqCounter + io.scommit 375 } 376 377 378 //TODO MaxAllocate and width of lqOffset/sqOffset needs to be discussed 379 val lqMaxAllocate = LSQLdEnqWidth 380 val sqMaxAllocate = LSQStEnqWidth 381 val maxAllocate = lqMaxAllocate max sqMaxAllocate 382 val ldCanAccept = lqCounter >= lqAllocNumber +& lqMaxAllocate.U 383 val sqCanAccept = sqCounter >= sqAllocNumber +& sqMaxAllocate.U 384 // It is possible that t3_update and enq are true at the same clock cycle. 385 // For example, if redirect.valid lasts more than one clock cycle, 386 // after the last redirect, new instructions may enter but previously redirect has not been resolved (updated according to the cancel count from LSQ). 387 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 388 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 389 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(lqPtr.value.getWidth.W))) 390 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(sqPtr.value.getWidth.W))) 391 for ((resp, i) <- io.enq.resp.zipWithIndex) { 392 lqOffset(i) := loadFlowPopCount(i) 393 resp.lqIdx := lqPtr + lqOffset(i) 394 sqOffset(i) := storeFlowPopCount(i) 395 resp.sqIdx := sqPtr + sqOffset(i) 396 } 397 398 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 399 io.enqLsq.iqAccept := RegNext(io.enq.iqAccept) 400 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 401 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 402 toLsq.valid := RegNext(do_enq) 403 toLsq.bits := RegEnable(enq.bits, do_enq) 404 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 405 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 406 } 407 408} 409