1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, MemExuOutput} 26import xiangshan.cache._ 27import xiangshan.cache.{DCacheLineIO, DCacheWordIO, MemoryOpConstants} 28import xiangshan.cache.mmu.TlbRequestIO 29import xiangshan.mem._ 30import xiangshan.backend._ 31import xiangshan.backend.rob.RobLsqIO 32 33class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 34 val isStore = Input(Bool()) 35 val vaddr = Output(UInt(VAddrBits.W)) 36} 37 38class FwdEntry extends Bundle { 39 val validFast = Bool() // validFast is generated the same cycle with query 40 val valid = Bool() // valid is generated 1 cycle after query request 41 val data = UInt(8.W) // data is generated 1 cycle after query request 42} 43 44// inflight miss block reqs 45class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 46 val block_addr = UInt(PAddrBits.W) 47 val valid = Bool() 48} 49 50class LsqEnqIO(implicit p: Parameters) extends MemBlockBundle { 51 val canAccept = Output(Bool()) 52 val needAlloc = Vec(LSQEnqWidth, Input(UInt(2.W))) 53 val req = Vec(LSQEnqWidth, Flipped(ValidIO(new DynInst))) 54 val resp = Vec(LSQEnqWidth, Output(new LSIdx)) 55} 56 57// Load / Store Queue Wrapper for XiangShan Out of Order LSU 58class LsqWrapper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 59 val io = IO(new Bundle() { 60 val hartId = Input(UInt(8.W)) 61 val brqRedirect = Flipped(ValidIO(new Redirect)) 62 val enq = new LsqEnqIO 63 val ldu = new Bundle() { 64 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 65 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 66 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 67 } 68 val sta = new Bundle() { 69 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // from store_s0, store mask, send to sq from rs 70 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 71 val storeAddrInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) // from store_s2 72 val vecStoreAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 73 } 74 val std = new Bundle() { 75 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput))) // from store_s0, store data, send to sq from rs 76 } 77 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 78 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 79 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 80 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddrAndPfFlag)) 81 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 82 val rob = Flipped(new RobLsqIO) 83 val rollback = Output(Valid(new Redirect)) 84 val release = Flipped(Valid(new Release)) 85 val refill = Flipped(Valid(new Refill)) 86 val tl_d_channel = Input(new DcacheToLduForwardIO) 87 val uncacheOutstanding = Input(Bool()) 88 val uncache = new UncacheWordIO 89 val mmioStout = DecoupledIO(new MemExuOutput) // writeback uncached store 90 val sqEmpty = Output(Bool()) 91 val lq_rep_full = Output(Bool()) 92 val sqFull = Output(Bool()) 93 val lqFull = Output(Bool()) 94 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize+1).W)) 95 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 96 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 97 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 98 val lqCanAccept = Output(Bool()) 99 val sqCanAccept = Output(Bool()) 100 val exceptionAddr = new ExceptionAddrIO 101 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 102 val issuePtrExt = Output(new SqPtr) 103 val l2_hint = Input(Valid(new L2ToL1Hint())) 104 val force_write = Output(Bool()) 105 val lqEmpty = Output(Bool()) 106 107 // vector 108 val vecWriteback = Flipped(ValidIO(new MemExuOutput(isVector = true))) 109 val vecStoreRetire = Flipped(ValidIO(new SqPtr)) 110 111 // top-down 112 val debugTopDown = new LoadQueueTopDownIO 113 }) 114 115 val loadQueue = Module(new LoadQueue) 116 val storeQueue = Module(new StoreQueue) 117 118 storeQueue.io.hartId := io.hartId 119 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 120 121 122 dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) 123 // Todo: imm 124 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(14.U(ReSelectLen.W), 0.U(ReSelectLen.W), 125.U(ReSelectLen.W), 0.U(ReSelectLen.W)))) 125 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 126 127 // io.enq logic 128 // LSQ: send out canAccept when both load queue and store queue are ready 129 // Dispatch: send instructions to LSQ only when they are ready 130 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 131 io.lqCanAccept := loadQueue.io.enq.canAccept 132 io.sqCanAccept := storeQueue.io.enq.canAccept 133 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 134 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 135 for (i <- io.enq.req.indices) { 136 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 137 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 138 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 139 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 140 141 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 142 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 143 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 144 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 145 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 146 147 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 148 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 149 } 150 151 // store queue wiring 152 storeQueue.io.brqRedirect <> io.brqRedirect 153 storeQueue.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 154 storeQueue.io.storeAddrInRe <> io.sta.storeAddrInRe // from store_s2 155 storeQueue.io.storeDataIn <> io.std.storeDataIn // from store_s0 156 storeQueue.io.storeMaskIn <> io.sta.storeMaskIn // from store_s0 157 storeQueue.io.sbuffer <> io.sbuffer 158 storeQueue.io.mmioStout <> io.mmioStout 159 storeQueue.io.rob <> io.rob 160 storeQueue.io.exceptionAddr.isStore := DontCare 161 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 162 storeQueue.io.sqDeq <> io.sqDeq 163 storeQueue.io.sqEmpty <> io.sqEmpty 164 storeQueue.io.sqFull <> io.sqFull 165 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 166 storeQueue.io.force_write <> io.force_write 167 storeQueue.io.vecStoreRetire <> io.vecStoreRetire 168 169 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 170 171 // load queue wiring 172 loadQueue.io.redirect <> io.brqRedirect 173 loadQueue.io.ldu <> io.ldu 174 loadQueue.io.ldout <> io.ldout 175 loadQueue.io.ld_raw_data <> io.ld_raw_data 176 loadQueue.io.rob <> io.rob 177 loadQueue.io.rollback <> io.rollback 178 loadQueue.io.replay <> io.replay 179 loadQueue.io.refill <> io.refill 180 loadQueue.io.tl_d_channel <> io.tl_d_channel 181 loadQueue.io.release <> io.release 182 loadQueue.io.trigger <> io.trigger 183 loadQueue.io.exceptionAddr.isStore := DontCare 184 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 185 loadQueue.io.sq.stAddrReadySqPtr <> storeQueue.io.stAddrReadySqPtr 186 loadQueue.io.sq.stAddrReadyVec <> storeQueue.io.stAddrReadyVec 187 loadQueue.io.sq.stDataReadySqPtr <> storeQueue.io.stDataReadySqPtr 188 loadQueue.io.sq.stDataReadyVec <> storeQueue.io.stDataReadyVec 189 loadQueue.io.sq.stIssuePtr <> storeQueue.io.stIssuePtr 190 loadQueue.io.sq.sqEmpty <> storeQueue.io.sqEmpty 191 loadQueue.io.sta.storeAddrIn <> io.sta.storeAddrIn // store_s1 192 loadQueue.io.sta.vecStoreAddrIn <> io.sta.vecStoreAddrIn // store_s1 193 loadQueue.io.std.storeDataIn <> io.std.storeDataIn // store_s0 194 loadQueue.io.lqFull <> io.lqFull 195 loadQueue.io.lq_rep_full <> io.lq_rep_full 196 loadQueue.io.lqDeq <> io.lqDeq 197 loadQueue.io.l2_hint <> io.l2_hint 198 loadQueue.io.lqEmpty <> io.lqEmpty 199 loadQueue.io.vecWriteback <> io.vecWriteback 200 201 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 202 // s0: commit 203 // s1: exception find 204 // s2: exception triggered 205 // s3: ptr updated & new address 206 // address will be used at the next cycle after exception is triggered 207 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 208 io.issuePtrExt := storeQueue.io.stAddrReadySqPtr 209 210 // naive uncache arbiter 211 val s_idle :: s_load :: s_store :: Nil = Enum(3) 212 val pendingstate = RegInit(s_idle) 213 214 switch(pendingstate){ 215 is(s_idle){ 216 when(io.uncache.req.fire && !io.uncacheOutstanding){ 217 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, 218 Mux(io.uncacheOutstanding, s_idle, s_store)) 219 } 220 } 221 is(s_load){ 222 when(io.uncache.resp.fire){ 223 pendingstate := s_idle 224 } 225 } 226 is(s_store){ 227 when(io.uncache.resp.fire){ 228 pendingstate := s_idle 229 } 230 } 231 } 232 233 loadQueue.io.uncache := DontCare 234 storeQueue.io.uncache := DontCare 235 loadQueue.io.uncache.req.ready := false.B 236 storeQueue.io.uncache.req.ready := false.B 237 loadQueue.io.uncache.resp.valid := false.B 238 storeQueue.io.uncache.resp.valid := false.B 239 when(loadQueue.io.uncache.req.valid){ 240 io.uncache.req <> loadQueue.io.uncache.req 241 }.otherwise{ 242 io.uncache.req <> storeQueue.io.uncache.req 243 } 244 when (io.uncacheOutstanding) { 245 io.uncache.resp <> loadQueue.io.uncache.resp 246 } .otherwise { 247 when(pendingstate === s_load){ 248 io.uncache.resp <> loadQueue.io.uncache.resp 249 }.otherwise{ 250 io.uncache.resp <> storeQueue.io.uncache.resp 251 } 252 } 253 254 loadQueue.io.debugTopDown <> io.debugTopDown 255 256 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 257 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 258 when (!io.uncacheOutstanding) { 259 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 260 } 261 262 263 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 264 generatePerfEvent() 265} 266 267class LsqEnqCtrl(implicit p: Parameters) extends XSModule { 268 val io = IO(new Bundle { 269 val redirect = Flipped(ValidIO(new Redirect)) 270 // to dispatch 271 val enq = new LsqEnqIO 272 // from `memBlock.io.lqDeq 273 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 274 // from `memBlock.io.sqDeq` 275 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 276 // from/tp lsq 277 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 278 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 279 val enqLsq = Flipped(new LsqEnqIO) 280 }) 281 282 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 283 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 284 val lqCounter = RegInit(VirtualLoadQueueSize.U(log2Up(VirtualLoadQueueSize + 1).W)) 285 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 286 val canAccept = RegInit(false.B) 287 288 val loadEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(0))) 289 val storeEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(1))) 290 291 // How to update ptr and counter: 292 // (1) by default, updated according to enq/commit 293 // (2) when redirect and dispatch queue is empty, update according to lsq 294 val t1_redirect = RegNext(io.redirect.valid) 295 val t2_redirect = RegNext(t1_redirect) 296 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 297 val t3_update = RegNext(t2_update) 298 val t3_lqCancelCnt = RegNext(io.lqCancelCnt) 299 val t3_sqCancelCnt = RegNext(io.sqCancelCnt) 300 when (t3_update) { 301 lqPtr := lqPtr - t3_lqCancelCnt 302 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 303 sqPtr := sqPtr - t3_sqCancelCnt 304 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 305 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 306 lqPtr := lqPtr + loadEnqNumber 307 lqCounter := lqCounter + io.lcommit - loadEnqNumber 308 sqPtr := sqPtr + storeEnqNumber 309 sqCounter := sqCounter + io.scommit - storeEnqNumber 310 }.otherwise { 311 lqCounter := lqCounter + io.lcommit 312 sqCounter := sqCounter + io.scommit 313 } 314 315 316 val maxAllocate = backendParams.LdExuCnt max backendParams.StaExuCnt 317 val ldCanAccept = lqCounter >= loadEnqNumber +& maxAllocate.U 318 val sqCanAccept = sqCounter >= storeEnqNumber +& maxAllocate.U 319 // It is possible that t3_update and enq are true at the same clock cycle. 320 // For example, if redirect.valid lasts more than one clock cycle, 321 // after the last redirect, new instructions may enter but previously redirect 322 // has not been resolved (updated according to the cancel count from LSQ). 323 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 324 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 325 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 326 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 327 for ((resp, i) <- io.enq.resp.zipWithIndex) { 328 lqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(0))) 329 resp.lqIdx := lqPtr + lqOffset(i) 330 sqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(1))) 331 resp.sqIdx := sqPtr + sqOffset(i) 332 } 333 334 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 335 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 336 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 337 toLsq.valid := RegNext(do_enq) 338 toLsq.bits := RegEnable(enq.bits, do_enq) 339 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 340 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 341 } 342 343}