1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.cache._ 26import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 27import xiangshan.cache.mmu.{TlbRequestIO} 28import xiangshan.mem._ 29import xiangshan.backend.rob.RobLsqIO 30 31class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 32 val isStore = Input(Bool()) 33 val vaddr = Output(UInt(VAddrBits.W)) 34} 35 36class FwdEntry extends Bundle { 37 val validFast = Bool() // validFast is generated the same cycle with query 38 val valid = Bool() // valid is generated 1 cycle after query request 39 val data = UInt(8.W) // data is generated 1 cycle after query request 40} 41 42// inflight miss block reqs 43class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 44 val block_addr = UInt(PAddrBits.W) 45 val valid = Bool() 46} 47 48class LsqEnqIO(implicit p: Parameters) extends XSBundle { 49 val canAccept = Output(Bool()) 50 val needAlloc = Vec(exuParameters.LsExuCnt, Input(UInt(2.W))) 51 val req = Vec(exuParameters.LsExuCnt, Flipped(ValidIO(new MicroOp))) 52 val resp = Vec(exuParameters.LsExuCnt, Output(new LSIdx)) 53} 54 55// Load / Store Queue Wrapper for XiangShan Out of Order LSU 56class LsqWrapper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 57 val io = IO(new Bundle() { 58 val hartId = Input(UInt(8.W)) 59 val brqRedirect = Flipped(ValidIO(new Redirect)) 60 val enq = new LsqEnqIO 61 val ldu = new Bundle() { 62 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 63 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 64 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 65 } 66 val sta = new Bundle() { 67 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // from store_s0, store mask, send to sq from rs 68 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 69 val storeAddrInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) // from store_s2 70 } 71 val std = new Bundle() { 72 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new ExuOutput))) // from store_s0, store data, send to sq from rs 73 } 74 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new ExuOutput)) 75 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 76 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 77 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddr)) 78 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 79 val rob = Flipped(new RobLsqIO) 80 val rollback = Output(Valid(new Redirect)) 81 val release = Flipped(Valid(new Release)) 82 val refill = Flipped(Valid(new Refill)) 83 val tl_d_channel = Input(new DcacheToLduForwardIO) 84 val uncacheOutstanding = Input(Bool()) 85 val uncache = new UncacheWordIO 86 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 87 val sqEmpty = Output(Bool()) 88 val lq_rep_full = Output(Bool()) 89 val sqFull = Output(Bool()) 90 val lqFull = Output(Bool()) 91 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize+1).W)) 92 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 93 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 94 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 95 val lqCanAccept = Output(Bool()) 96 val sqCanAccept = Output(Bool()) 97 val exceptionAddr = new ExceptionAddrIO 98 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 99 val issuePtrExt = Output(new SqPtr) 100 val l2_hint = Input(Valid(new L2ToL1Hint())) 101 val force_write = Output(Bool()) 102 }) 103 104 val loadQueue = Module(new LoadQueue) 105 val storeQueue = Module(new StoreQueue) 106 107 storeQueue.io.hartId := io.hartId 108 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 109 110 111 dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) 112 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(14.U(ReSelectLen.W), 0.U(ReSelectLen.W), 125.U(ReSelectLen.W), 0.U(ReSelectLen.W)))) 113 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 114 115 // io.enq logic 116 // LSQ: send out canAccept when both load queue and store queue are ready 117 // Dispatch: send instructions to LSQ only when they are ready 118 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 119 io.lqCanAccept := loadQueue.io.enq.canAccept 120 io.sqCanAccept := storeQueue.io.enq.canAccept 121 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 122 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 123 for (i <- io.enq.req.indices) { 124 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 125 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 126 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 127 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 128 129 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 130 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 131 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 132 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 133 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 134 135 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 136 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 137 } 138 139 // store queue wiring 140 storeQueue.io.brqRedirect <> io.brqRedirect 141 storeQueue.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 142 storeQueue.io.storeAddrInRe <> io.sta.storeAddrInRe // from store_s2 143 storeQueue.io.storeDataIn <> io.std.storeDataIn // from store_s0 144 storeQueue.io.storeMaskIn <> io.sta.storeMaskIn // from store_s0 145 storeQueue.io.sbuffer <> io.sbuffer 146 storeQueue.io.mmioStout <> io.mmioStout 147 storeQueue.io.rob <> io.rob 148 storeQueue.io.exceptionAddr.isStore := DontCare 149 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 150 storeQueue.io.sqDeq <> io.sqDeq 151 storeQueue.io.sqEmpty <> io.sqEmpty 152 storeQueue.io.sqFull <> io.sqFull 153 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 154 storeQueue.io.force_write <> io.force_write 155 156 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 157 158 // load queue wiring 159 loadQueue.io.redirect <> io.brqRedirect 160 loadQueue.io.ldu <> io.ldu 161 loadQueue.io.ldout <> io.ldout 162 loadQueue.io.ld_raw_data <> io.ld_raw_data 163 loadQueue.io.rob <> io.rob 164 loadQueue.io.rollback <> io.rollback 165 loadQueue.io.replay <> io.replay 166 loadQueue.io.refill <> io.refill 167 loadQueue.io.tl_d_channel <> io.tl_d_channel 168 loadQueue.io.release <> io.release 169 loadQueue.io.trigger <> io.trigger 170 loadQueue.io.exceptionAddr.isStore := DontCare 171 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 172 loadQueue.io.sq.stAddrReadySqPtr <> storeQueue.io.stAddrReadySqPtr 173 loadQueue.io.sq.stAddrReadyVec <> storeQueue.io.stAddrReadyVec 174 loadQueue.io.sq.stDataReadySqPtr <> storeQueue.io.stDataReadySqPtr 175 loadQueue.io.sq.stDataReadyVec <> storeQueue.io.stDataReadyVec 176 loadQueue.io.sq.stIssuePtr <> storeQueue.io.stIssuePtr 177 loadQueue.io.sq.sqEmpty <> storeQueue.io.sqEmpty 178 loadQueue.io.sta.storeAddrIn <> io.sta.storeAddrIn // store_s1 179 loadQueue.io.std.storeDataIn <> io.std.storeDataIn // store_s0 180 loadQueue.io.lqFull <> io.lqFull 181 loadQueue.io.lq_rep_full <> io.lq_rep_full 182 loadQueue.io.lqDeq <> io.lqDeq 183 loadQueue.io.l2_hint <> io.l2_hint 184 185 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 186 // s0: commit 187 // s1: exception find 188 // s2: exception triggered 189 // s3: ptr updated & new address 190 // address will be used at the next cycle after exception is triggered 191 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 192 io.issuePtrExt := storeQueue.io.stAddrReadySqPtr 193 194 // naive uncache arbiter 195 val s_idle :: s_load :: s_store :: Nil = Enum(3) 196 val pendingstate = RegInit(s_idle) 197 198 switch(pendingstate){ 199 is(s_idle){ 200 when(io.uncache.req.fire() && !io.uncacheOutstanding){ 201 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, 202 Mux(io.uncacheOutstanding, s_idle, s_store)) 203 } 204 } 205 is(s_load){ 206 when(io.uncache.resp.fire()){ 207 pendingstate := s_idle 208 } 209 } 210 is(s_store){ 211 when(io.uncache.resp.fire()){ 212 pendingstate := s_idle 213 } 214 } 215 } 216 217 loadQueue.io.uncache := DontCare 218 storeQueue.io.uncache := DontCare 219 loadQueue.io.uncache.resp.valid := false.B 220 storeQueue.io.uncache.resp.valid := false.B 221 when(loadQueue.io.uncache.req.valid){ 222 io.uncache.req <> loadQueue.io.uncache.req 223 }.otherwise{ 224 io.uncache.req <> storeQueue.io.uncache.req 225 } 226 when (io.uncacheOutstanding) { 227 io.uncache.resp <> loadQueue.io.uncache.resp 228 } .otherwise { 229 when(pendingstate === s_load){ 230 io.uncache.resp <> loadQueue.io.uncache.resp 231 }.otherwise{ 232 io.uncache.resp <> storeQueue.io.uncache.resp 233 } 234 } 235 236 237 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 238 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 239 when (!io.uncacheOutstanding) { 240 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 241 } 242 243 244 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 245 generatePerfEvent() 246} 247 248class LsqEnqCtrl(implicit p: Parameters) extends XSModule { 249 val io = IO(new Bundle { 250 val redirect = Flipped(ValidIO(new Redirect)) 251 // to dispatch 252 val enq = new LsqEnqIO 253 // from `memBlock.io.lqDeq 254 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 255 // from `memBlock.io.sqDeq` 256 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 257 // from/tp lsq 258 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 259 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 260 val enqLsq = Flipped(new LsqEnqIO) 261 }) 262 263 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 264 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 265 val lqCounter = RegInit(VirtualLoadQueueSize.U(log2Up(VirtualLoadQueueSize + 1).W)) 266 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 267 val canAccept = RegInit(false.B) 268 269 val loadEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(0))) 270 val storeEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(1))) 271 272 // How to update ptr and counter: 273 // (1) by default, updated according to enq/commit 274 // (2) when redirect and dispatch queue is empty, update according to lsq 275 val t1_redirect = RegNext(io.redirect.valid) 276 val t2_redirect = RegNext(t1_redirect) 277 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 278 val t3_update = RegNext(t2_update) 279 val t3_lqCancelCnt = RegNext(io.lqCancelCnt) 280 val t3_sqCancelCnt = RegNext(io.sqCancelCnt) 281 when (t3_update) { 282 lqPtr := lqPtr - t3_lqCancelCnt 283 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 284 sqPtr := sqPtr - t3_sqCancelCnt 285 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 286 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 287 lqPtr := lqPtr + loadEnqNumber 288 lqCounter := lqCounter + io.lcommit - loadEnqNumber 289 sqPtr := sqPtr + storeEnqNumber 290 sqCounter := sqCounter + io.scommit - storeEnqNumber 291 }.otherwise { 292 lqCounter := lqCounter + io.lcommit 293 sqCounter := sqCounter + io.scommit 294 } 295 296 297 val maxAllocate = Seq(exuParameters.LduCnt, exuParameters.StuCnt).max 298 val ldCanAccept = lqCounter >= loadEnqNumber +& maxAllocate.U 299 val sqCanAccept = sqCounter >= storeEnqNumber +& maxAllocate.U 300 // It is possible that t3_update and enq are true at the same clock cycle. 301 // For example, if redirect.valid lasts more than one clock cycle, 302 // after the last redirect, new instructions may enter but previously redirect 303 // has not been resolved (updated according to the cancel count from LSQ). 304 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 305 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 306 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 307 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 308 for ((resp, i) <- io.enq.resp.zipWithIndex) { 309 lqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(0))) 310 resp.lqIdx := lqPtr + lqOffset(i) 311 sqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(1))) 312 resp.sqIdx := sqPtr + sqOffset(i) 313 } 314 315 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 316 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 317 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 318 toLsq.valid := RegNext(do_enq) 319 toLsq.bits := RegEnable(enq.bits, do_enq) 320 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 321 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 322 } 323 324}