1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, MemExuOutput} 26import xiangshan.cache._ 27import xiangshan.cache.{DCacheLineIO, DCacheWordIO, MemoryOpConstants} 28import xiangshan.cache.mmu.TlbRequestIO 29import xiangshan.mem._ 30import xiangshan.backend._ 31import xiangshan.backend.rob.RobLsqIO 32 33class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 34 val isStore = Input(Bool()) 35 val vaddr = Output(UInt(VAddrBits.W)) 36} 37 38class FwdEntry extends Bundle { 39 val validFast = Bool() // validFast is generated the same cycle with query 40 val valid = Bool() // valid is generated 1 cycle after query request 41 val data = UInt(8.W) // data is generated 1 cycle after query request 42} 43 44// inflight miss block reqs 45class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 46 val block_addr = UInt(PAddrBits.W) 47 val valid = Bool() 48} 49 50class LsqEnqIO(implicit p: Parameters) extends MemBlockBundle { 51 val canAccept = Output(Bool()) 52 val needAlloc = Vec(MemPipelineWidth, Input(UInt(2.W))) 53 val req = Vec(MemPipelineWidth, Flipped(ValidIO(new DynInst))) 54 val resp = Vec(MemPipelineWidth, Output(new LSIdx)) 55} 56 57// Load / Store Queue Wrapper for XiangShan Out of Order LSU 58class LsqWrapper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 59 val io = IO(new Bundle() { 60 val hartId = Input(UInt(8.W)) 61 val brqRedirect = Flipped(ValidIO(new Redirect)) 62 val enq = new LsqEnqIO 63 val ldu = new Bundle() { 64 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 65 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 66 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 67 } 68 val sta = new Bundle() { 69 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // from store_s0, store mask, send to sq from rs 70 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 71 val storeAddrInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) // from store_s2 72 } 73 val std = new Bundle() { 74 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput))) // from store_s0, store data, send to sq from rs 75 } 76 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 77 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 78 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 79 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddrAndPfFlag)) 80 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 81 val rob = Flipped(new RobLsqIO) 82 val rollback = Output(Valid(new Redirect)) 83 val release = Flipped(Valid(new Release)) 84 val refill = Flipped(Valid(new Refill)) 85 val tl_d_channel = Input(new DcacheToLduForwardIO) 86 val uncacheOutstanding = Input(Bool()) 87 val uncache = new UncacheWordIO 88 val mmioStout = DecoupledIO(new MemExuOutput) // writeback uncached store 89 val sqEmpty = Output(Bool()) 90 val lq_rep_full = Output(Bool()) 91 val sqFull = Output(Bool()) 92 val lqFull = Output(Bool()) 93 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize+1).W)) 94 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 95 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 96 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 97 val lqCanAccept = Output(Bool()) 98 val sqCanAccept = Output(Bool()) 99 val exceptionAddr = new ExceptionAddrIO 100 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 101 val issuePtrExt = Output(new SqPtr) 102 val l2_hint = Input(Valid(new L2ToL1Hint())) 103 val force_write = Output(Bool()) 104 val lqEmpty = Output(Bool()) 105 val debugTopDown = new LoadQueueTopDownIO 106 }) 107 108 val loadQueue = Module(new LoadQueue) 109 val storeQueue = Module(new StoreQueue) 110 111 storeQueue.io.hartId := io.hartId 112 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 113 114 115 dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) 116 // Todo: imm 117 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(14.U(ReSelectLen.W), 0.U(ReSelectLen.W), 125.U(ReSelectLen.W), 0.U(ReSelectLen.W)))) 118 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 119 120 // io.enq logic 121 // LSQ: send out canAccept when both load queue and store queue are ready 122 // Dispatch: send instructions to LSQ only when they are ready 123 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 124 io.lqCanAccept := loadQueue.io.enq.canAccept 125 io.sqCanAccept := storeQueue.io.enq.canAccept 126 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 127 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 128 for (i <- io.enq.req.indices) { 129 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 130 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 131 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 132 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 133 134 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 135 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 136 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 137 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 138 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 139 140 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 141 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 142 } 143 144 // store queue wiring 145 storeQueue.io.brqRedirect <> io.brqRedirect 146 storeQueue.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 147 storeQueue.io.storeAddrInRe <> io.sta.storeAddrInRe // from store_s2 148 storeQueue.io.storeDataIn <> io.std.storeDataIn // from store_s0 149 storeQueue.io.storeMaskIn <> io.sta.storeMaskIn // from store_s0 150 storeQueue.io.sbuffer <> io.sbuffer 151 storeQueue.io.mmioStout <> io.mmioStout 152 storeQueue.io.rob <> io.rob 153 storeQueue.io.exceptionAddr.isStore := DontCare 154 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 155 storeQueue.io.sqDeq <> io.sqDeq 156 storeQueue.io.sqEmpty <> io.sqEmpty 157 storeQueue.io.sqFull <> io.sqFull 158 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 159 storeQueue.io.force_write <> io.force_write 160 161 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 162 163 // load queue wiring 164 loadQueue.io.redirect <> io.brqRedirect 165 loadQueue.io.ldu <> io.ldu 166 loadQueue.io.ldout <> io.ldout 167 loadQueue.io.ld_raw_data <> io.ld_raw_data 168 loadQueue.io.rob <> io.rob 169 loadQueue.io.rollback <> io.rollback 170 loadQueue.io.replay <> io.replay 171 loadQueue.io.refill <> io.refill 172 loadQueue.io.tl_d_channel <> io.tl_d_channel 173 loadQueue.io.release <> io.release 174 loadQueue.io.trigger <> io.trigger 175 loadQueue.io.exceptionAddr.isStore := DontCare 176 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 177 loadQueue.io.sq.stAddrReadySqPtr <> storeQueue.io.stAddrReadySqPtr 178 loadQueue.io.sq.stAddrReadyVec <> storeQueue.io.stAddrReadyVec 179 loadQueue.io.sq.stDataReadySqPtr <> storeQueue.io.stDataReadySqPtr 180 loadQueue.io.sq.stDataReadyVec <> storeQueue.io.stDataReadyVec 181 loadQueue.io.sq.stIssuePtr <> storeQueue.io.stIssuePtr 182 loadQueue.io.sq.sqEmpty <> storeQueue.io.sqEmpty 183 loadQueue.io.sta.storeAddrIn <> io.sta.storeAddrIn // store_s1 184 loadQueue.io.std.storeDataIn <> io.std.storeDataIn // store_s0 185 loadQueue.io.lqFull <> io.lqFull 186 loadQueue.io.lq_rep_full <> io.lq_rep_full 187 loadQueue.io.lqDeq <> io.lqDeq 188 loadQueue.io.l2_hint <> io.l2_hint 189 loadQueue.io.lqEmpty <> io.lqEmpty 190 191 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 192 // s0: commit 193 // s1: exception find 194 // s2: exception triggered 195 // s3: ptr updated & new address 196 // address will be used at the next cycle after exception is triggered 197 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 198 io.issuePtrExt := storeQueue.io.stAddrReadySqPtr 199 200 // naive uncache arbiter 201 val s_idle :: s_load :: s_store :: Nil = Enum(3) 202 val pendingstate = RegInit(s_idle) 203 204 switch(pendingstate){ 205 is(s_idle){ 206 when(io.uncache.req.fire && !io.uncacheOutstanding){ 207 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, 208 Mux(io.uncacheOutstanding, s_idle, s_store)) 209 } 210 } 211 is(s_load){ 212 when(io.uncache.resp.fire){ 213 pendingstate := s_idle 214 } 215 } 216 is(s_store){ 217 when(io.uncache.resp.fire){ 218 pendingstate := s_idle 219 } 220 } 221 } 222 223 loadQueue.io.uncache := DontCare 224 storeQueue.io.uncache := DontCare 225 loadQueue.io.uncache.req.ready := false.B 226 storeQueue.io.uncache.req.ready := false.B 227 loadQueue.io.uncache.resp.valid := false.B 228 storeQueue.io.uncache.resp.valid := false.B 229 when(loadQueue.io.uncache.req.valid){ 230 io.uncache.req <> loadQueue.io.uncache.req 231 }.otherwise{ 232 io.uncache.req <> storeQueue.io.uncache.req 233 } 234 when (io.uncacheOutstanding) { 235 io.uncache.resp <> loadQueue.io.uncache.resp 236 } .otherwise { 237 when(pendingstate === s_load){ 238 io.uncache.resp <> loadQueue.io.uncache.resp 239 }.otherwise{ 240 io.uncache.resp <> storeQueue.io.uncache.resp 241 } 242 } 243 244 loadQueue.io.debugTopDown <> io.debugTopDown 245 246 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 247 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 248 when (!io.uncacheOutstanding) { 249 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 250 } 251 252 253 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 254 generatePerfEvent() 255} 256 257class LsqEnqCtrl(implicit p: Parameters) extends XSModule { 258 val io = IO(new Bundle { 259 val redirect = Flipped(ValidIO(new Redirect)) 260 // to dispatch 261 val enq = new LsqEnqIO 262 // from `memBlock.io.lqDeq 263 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 264 // from `memBlock.io.sqDeq` 265 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 266 // from/tp lsq 267 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 268 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 269 val enqLsq = Flipped(new LsqEnqIO) 270 }) 271 272 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 273 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 274 val lqCounter = RegInit(VirtualLoadQueueSize.U(log2Up(VirtualLoadQueueSize + 1).W)) 275 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 276 val canAccept = RegInit(false.B) 277 278 val loadEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(0))) 279 val storeEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(1))) 280 281 // How to update ptr and counter: 282 // (1) by default, updated according to enq/commit 283 // (2) when redirect and dispatch queue is empty, update according to lsq 284 val t1_redirect = RegNext(io.redirect.valid) 285 val t2_redirect = RegNext(t1_redirect) 286 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 287 val t3_update = RegNext(t2_update) 288 val t3_lqCancelCnt = RegNext(io.lqCancelCnt) 289 val t3_sqCancelCnt = RegNext(io.sqCancelCnt) 290 when (t3_update) { 291 lqPtr := lqPtr - t3_lqCancelCnt 292 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 293 sqPtr := sqPtr - t3_sqCancelCnt 294 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 295 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 296 lqPtr := lqPtr + loadEnqNumber 297 lqCounter := lqCounter + io.lcommit - loadEnqNumber 298 sqPtr := sqPtr + storeEnqNumber 299 sqCounter := sqCounter + io.scommit - storeEnqNumber 300 }.otherwise { 301 lqCounter := lqCounter + io.lcommit 302 sqCounter := sqCounter + io.scommit 303 } 304 305 306 val maxAllocate = Seq(backendParams.LduCnt, backendParams.StaCnt).max 307 val ldCanAccept = lqCounter >= loadEnqNumber +& maxAllocate.U 308 val sqCanAccept = sqCounter >= storeEnqNumber +& maxAllocate.U 309 // It is possible that t3_update and enq are true at the same clock cycle. 310 // For example, if redirect.valid lasts more than one clock cycle, 311 // after the last redirect, new instructions may enter but previously redirect 312 // has not been resolved (updated according to the cancel count from LSQ). 313 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 314 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 315 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 316 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 317 for ((resp, i) <- io.enq.resp.zipWithIndex) { 318 lqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(0))) 319 resp.lqIdx := lqPtr + lqOffset(i) 320 sqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(1))) 321 resp.sqIdx := sqPtr + sqOffset(i) 322 } 323 324 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 325 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 326 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 327 toLsq.valid := RegNext(do_enq) 328 toLsq.bits := RegEnable(enq.bits, do_enq) 329 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 330 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 331 } 332 333}