xref: /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala (revision 0bd67ba5d9e2254f494e631babff500195d3dfa3)
1c7658a75SYinan Xupackage xiangshan.mem
2c7658a75SYinan Xu
3c7658a75SYinan Xuimport chisel3._
4c7658a75SYinan Xuimport chisel3.util._
5c7658a75SYinan Xuimport utils._
6c7658a75SYinan Xuimport xiangshan._
7c7658a75SYinan Xuimport xiangshan.cache._
8c7658a75SYinan Xuimport xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants}
9c7658a75SYinan Xuimport xiangshan.backend.LSUOpType
10c7658a75SYinan Xuimport xiangshan.mem._
11c7658a75SYinan Xuimport xiangshan.backend.roq.RoqPtr
12c7658a75SYinan Xu
13c7658a75SYinan Xuclass ExceptionAddrIO extends XSBundle {
14c7658a75SYinan Xu  val lsIdx = Input(new LSIdx)
15c7658a75SYinan Xu  val isStore = Input(Bool())
16c7658a75SYinan Xu  val vaddr = Output(UInt(VAddrBits.W))
17c7658a75SYinan Xu}
18c7658a75SYinan Xu
19c7658a75SYinan Xu
20*0bd67ba5SYinan Xuclass LsqEntry extends XSBundle {
21c7658a75SYinan Xu  val vaddr = UInt(VAddrBits.W) // TODO: need opt
22c7658a75SYinan Xu  val paddr = UInt(PAddrBits.W)
23c7658a75SYinan Xu  val op = UInt(6.W)
24c7658a75SYinan Xu  val mask = UInt(8.W)
25c7658a75SYinan Xu  val data = UInt(XLEN.W)
26c7658a75SYinan Xu  val exception = UInt(16.W) // TODO: opt size
27c7658a75SYinan Xu  val mmio = Bool()
28c7658a75SYinan Xu  val fwdMask = Vec(8, Bool())
29c7658a75SYinan Xu  val fwdData = Vec(8, UInt(8.W))
30c7658a75SYinan Xu}
31c7658a75SYinan Xu
32c7658a75SYinan Xu// inflight miss block reqs
33c7658a75SYinan Xuclass InflightBlockInfo extends XSBundle {
34c7658a75SYinan Xu  val block_addr = UInt(PAddrBits.W)
35c7658a75SYinan Xu  val valid = Bool()
36c7658a75SYinan Xu}
37c7658a75SYinan Xu
38c7658a75SYinan Xu// Load / Store Queue Wrapper for XiangShan Out of Order LSU
39c7658a75SYinan Xuclass LsqWrappper extends XSModule with HasDCacheParameters {
40c7658a75SYinan Xu  val io = IO(new Bundle() {
41c7658a75SYinan Xu    val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
42c7658a75SYinan Xu    val lsIdxs = Output(Vec(RenameWidth, new LSIdx))
43c7658a75SYinan Xu    val brqRedirect = Input(Valid(new Redirect))
44c7658a75SYinan Xu    val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle)))
45c7658a75SYinan Xu    val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle)))
46c7658a75SYinan Xu    val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReq))
47c7658a75SYinan Xu    val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback store
48c7658a75SYinan Xu    val stout = Vec(2, DecoupledIO(new ExuOutput)) // writeback store
49c7658a75SYinan Xu    val forward = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO))
50c7658a75SYinan Xu    val commits = Flipped(Vec(CommitWidth, Valid(new RoqCommit)))
51c7658a75SYinan Xu    val rollback = Output(Valid(new Redirect))
52c7658a75SYinan Xu    val dcache = new DCacheLineIO
53c7658a75SYinan Xu    val uncache = new DCacheWordIO
54c7658a75SYinan Xu    val roqDeqPtr = Input(new RoqPtr)
55c7658a75SYinan Xu    val oldestStore = Output(Valid(new RoqPtr))
56c7658a75SYinan Xu    val exceptionAddr = new ExceptionAddrIO
57c7658a75SYinan Xu  })
58c7658a75SYinan Xu
59c7658a75SYinan Xu  val loadQueue = Module(new LoadQueue)
60c7658a75SYinan Xu  val storeQueue = Module(new StoreQueue)
61c7658a75SYinan Xu
62c7658a75SYinan Xu  // load queue wiring
63c7658a75SYinan Xu  loadQueue.io.dp1Req <> io.dp1Req
64c7658a75SYinan Xu  loadQueue.io.brqRedirect <> io.brqRedirect
65c7658a75SYinan Xu  loadQueue.io.loadIn <> io.loadIn
66c7658a75SYinan Xu  loadQueue.io.storeIn <> io.storeIn
67c7658a75SYinan Xu  loadQueue.io.ldout <> io.ldout
68c7658a75SYinan Xu  loadQueue.io.commits <> io.commits
69c7658a75SYinan Xu  loadQueue.io.rollback <> io.rollback
70c7658a75SYinan Xu  loadQueue.io.dcache <> io.dcache
71c7658a75SYinan Xu  loadQueue.io.roqDeqPtr <> io.roqDeqPtr
72c7658a75SYinan Xu  loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx
73c7658a75SYinan Xu  loadQueue.io.exceptionAddr.isStore := DontCare
74c7658a75SYinan Xu
75c7658a75SYinan Xu  // store queue wiring
76c7658a75SYinan Xu  // storeQueue.io <> DontCare
77c7658a75SYinan Xu  storeQueue.io.dp1Req <> io.dp1Req
78c7658a75SYinan Xu  storeQueue.io.brqRedirect <> io.brqRedirect
79c7658a75SYinan Xu  storeQueue.io.storeIn <> io.storeIn
80c7658a75SYinan Xu  storeQueue.io.sbuffer <> io.sbuffer
81c7658a75SYinan Xu  storeQueue.io.stout <> io.stout
82c7658a75SYinan Xu  storeQueue.io.commits <> io.commits
83c7658a75SYinan Xu  storeQueue.io.roqDeqPtr <> io.roqDeqPtr
84c7658a75SYinan Xu  storeQueue.io.oldestStore <> io.oldestStore
85c7658a75SYinan Xu  storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx
86c7658a75SYinan Xu  storeQueue.io.exceptionAddr.isStore := DontCare
87c7658a75SYinan Xu
88c7658a75SYinan Xu  loadQueue.io.forward <> io.forward
89c7658a75SYinan Xu  storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE
90c7658a75SYinan Xu
91c7658a75SYinan Xu  io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr)
92c7658a75SYinan Xu
93c7658a75SYinan Xu  // naive uncache arbiter
94c7658a75SYinan Xu  val s_idle :: s_load :: s_store :: Nil = Enum(3)
95c7658a75SYinan Xu  val uncacheState = RegInit(s_idle)
96c7658a75SYinan Xu
97c7658a75SYinan Xu  switch(uncacheState){
98c7658a75SYinan Xu    is(s_idle){
99c7658a75SYinan Xu      when(io.uncache.req.fire()){
100c7658a75SYinan Xu        uncacheState := Mux(loadQueue.io.uncache.req.valid, s_load, s_store)
101c7658a75SYinan Xu      }
102c7658a75SYinan Xu    }
103c7658a75SYinan Xu    is(s_load){
104c7658a75SYinan Xu      when(io.uncache.resp.fire()){
105c7658a75SYinan Xu        uncacheState := s_idle
106c7658a75SYinan Xu      }
107c7658a75SYinan Xu    }
108c7658a75SYinan Xu    is(s_store){
109c7658a75SYinan Xu      when(io.uncache.resp.fire()){
110c7658a75SYinan Xu        uncacheState := s_idle
111c7658a75SYinan Xu      }
112c7658a75SYinan Xu    }
113c7658a75SYinan Xu  }
114c7658a75SYinan Xu
115c7658a75SYinan Xu  loadQueue.io.uncache := DontCare
116c7658a75SYinan Xu  storeQueue.io.uncache := DontCare
117c7658a75SYinan Xu  loadQueue.io.uncache.resp.valid := false.B
118c7658a75SYinan Xu  storeQueue.io.uncache.resp.valid := false.B
119c7658a75SYinan Xu  when(loadQueue.io.uncache.req.valid){
120c7658a75SYinan Xu    io.uncache.req <> loadQueue.io.uncache.req
121c7658a75SYinan Xu  }.otherwise{
122c7658a75SYinan Xu    io.uncache.req <> storeQueue.io.uncache.req
123c7658a75SYinan Xu  }
124c7658a75SYinan Xu  when(uncacheState === s_load){
125c7658a75SYinan Xu    io.uncache.resp <> loadQueue.io.uncache.resp
126c7658a75SYinan Xu  }.otherwise{
127c7658a75SYinan Xu    io.uncache.resp <> storeQueue.io.uncache.resp
128c7658a75SYinan Xu  }
129c7658a75SYinan Xu
130c7658a75SYinan Xu  assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid))
131c7658a75SYinan Xu  assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid))
132c7658a75SYinan Xu  assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && uncacheState === s_idle))
133c7658a75SYinan Xu
134c7658a75SYinan Xu  // fix valid, allocate lq / sq index
135c7658a75SYinan Xu  (0 until RenameWidth).map(i => {
136c7658a75SYinan Xu    val isStore = CommitType.lsInstIsStore(io.dp1Req(i).bits.ctrl.commitType)
137c7658a75SYinan Xu    val prevCanIn = if (i == 0) true.B else Cat((0 until i).map(i => io.dp1Req(i).ready)).andR
138c7658a75SYinan Xu    loadQueue.io.dp1Req(i).valid := !isStore && io.dp1Req(i).valid && prevCanIn
139c7658a75SYinan Xu    storeQueue.io.dp1Req(i).valid := isStore && io.dp1Req(i).valid && prevCanIn
140c7658a75SYinan Xu    loadQueue.io.lqIdxs(i) <> io.lsIdxs(i).lqIdx
141c7658a75SYinan Xu    storeQueue.io.sqIdxs(i) <> io.lsIdxs(i).sqIdx
142c7658a75SYinan Xu    io.dp1Req(i).ready := storeQueue.io.dp1Req(i).ready && loadQueue.io.dp1Req(i).ready
143c7658a75SYinan Xu  })
144c7658a75SYinan Xu}
145