1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import utility._ 24import utils._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput} 27import xiangshan.backend.rob.RobPtr 28import xiangshan.cache._ 29import xiangshan.backend.fu.FenceToSbuffer 30import xiangshan.cache.wpu.ReplayCarry 31import xiangshan.mem.prefetch.PrefetchReqBundle 32 33object genWmask { 34 def apply(addr: UInt, sizeEncode: UInt): UInt = { 35 (LookupTree(sizeEncode, List( 36 "b00".U -> 0x1.U, //0001 << addr(2:0) 37 "b01".U -> 0x3.U, //0011 38 "b10".U -> 0xf.U, //1111 39 "b11".U -> 0xff.U //11111111 40 )) << addr(2, 0)).asUInt 41 } 42} 43 44object genVWmask { 45 def apply(addr: UInt, sizeEncode: UInt): UInt = { 46 (LookupTree(sizeEncode, List( 47 "b00".U -> 0x1.U, //0001 << addr(2:0) 48 "b01".U -> 0x3.U, //0011 49 "b10".U -> 0xf.U, //1111 50 "b11".U -> 0xff.U //11111111 51 )) << addr(3, 0)).asUInt 52 } 53} 54 55object genWdata { 56 def apply(data: UInt, sizeEncode: UInt): UInt = { 57 LookupTree(sizeEncode, List( 58 "b00".U -> Fill(16, data(7, 0)), 59 "b01".U -> Fill(8, data(15, 0)), 60 "b10".U -> Fill(4, data(31, 0)), 61 "b11".U -> Fill(2, data(63,0)) 62 )) 63 } 64} 65 66object shiftDataToLow { 67 def apply(addr: UInt,data : UInt): UInt = { 68 Mux(addr(3), (data >> 64).asUInt,data) 69 } 70} 71object shiftMaskToLow { 72 def apply(addr: UInt,mask: UInt): UInt = { 73 Mux(addr(3),(mask >> 8).asUInt,mask) 74 } 75} 76 77class LsPipelineBundle(implicit p: Parameters) extends XSBundle 78 with HasDCacheParameters 79 with HasVLSUParameters { 80 val uop = new DynInst 81 val vaddr = UInt(VAddrBits.W) 82 val paddr = UInt(PAddrBits.W) 83 // val func = UInt(6.W) 84 val mask = UInt((VLEN/8).W) 85 val data = UInt((VLEN+1).W) 86 val wlineflag = Bool() // store write the whole cache line 87 88 val miss = Bool() 89 val tlbMiss = Bool() 90 val ptwBack = Bool() 91 val mmio = Bool() 92 val atomic = Bool() 93 val rsIdx = UInt(log2Up(MemIQSizeMax).W) 94 95 val forwardMask = Vec(VLEN/8, Bool()) 96 val forwardData = Vec(VLEN/8, UInt(8.W)) 97 98 // prefetch 99 val isPrefetch = Bool() 100 val isHWPrefetch = Bool() 101 def isSWPrefetch = isPrefetch && !isHWPrefetch 102 103 // vector 104 val isvec = Bool() 105 val is128bit = Bool() 106 val uop_unit_stride_fof = Bool() 107 // val rob_idx_valid = Vec(2,Bool()) 108 // val inner_idx = Vec(2,UInt(3.W)) 109 // val rob_idx = Vec(2,new RobPtr) 110 val reg_offset = UInt(vOffsetBits.W) 111 // val offset = Vec(2,UInt(4.W)) 112 val exp = Bool() 113 val is_first_ele = Bool() 114 val flowPtr = new VlflowPtr() // VLFlowQueue ptr 115 val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 116 117 // For debug usage 118 val isFirstIssue = Bool() 119 val hasROBEntry = Bool() 120 121 // For load replay 122 val isLoadReplay = Bool() 123 val isFastPath = Bool() 124 val isFastReplay = Bool() 125 val replayCarry = new ReplayCarry(nWays) 126 127 // For dcache miss load 128 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 129 val handledByMSHR = Bool() 130 val replacementUpdated = Bool() 131 val missDbUpdated = Bool() 132 133 val forward_tlDchannel = Bool() 134 val dcacheRequireReplay = Bool() 135 val delayedLoadError = Bool() 136 val lateKill = Bool() 137 val feedbacked = Bool() 138 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 139 // loadQueueReplay index. 140 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 141 142 // issue dequeue port index 143 val deqPortIdx = UInt(log2Ceil(LoadPipelineWidth).W) 144} 145 146class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 147 val meta_prefetch = UInt(L1PfSourceBits.W) 148 val meta_access = Bool() 149 150 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false) = { 151 if (latch) vaddr := RegNext(input.vaddr) else vaddr := input.vaddr 152 if (latch) paddr := RegNext(input.paddr) else paddr := input.paddr 153 if (latch) mask := RegNext(input.mask) else mask := input.mask 154 if (latch) data := RegNext(input.data) else data := input.data 155 if (latch) uop := RegNext(input.uop) else uop := input.uop 156 if (latch) wlineflag := RegNext(input.wlineflag) else wlineflag := input.wlineflag 157 if (latch) miss := RegNext(input.miss) else miss := input.miss 158 if (latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss 159 if (latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack 160 if (latch) mmio := RegNext(input.mmio) else mmio := input.mmio 161 if (latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx 162 if (latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask 163 if (latch) forwardData := RegNext(input.forwardData) else forwardData := input.forwardData 164 if (latch) isPrefetch := RegNext(input.isPrefetch) else isPrefetch := input.isPrefetch 165 if (latch) isHWPrefetch := RegNext(input.isHWPrefetch) else isHWPrefetch := input.isHWPrefetch 166 if (latch) isFirstIssue := RegNext(input.isFirstIssue) else isFirstIssue := input.isFirstIssue 167 if (latch) hasROBEntry := RegNext(input.hasROBEntry) else hasROBEntry := input.hasROBEntry 168 if (latch) dcacheRequireReplay := RegNext(input.dcacheRequireReplay) else dcacheRequireReplay := input.dcacheRequireReplay 169 if (latch) schedIndex := RegNext(input.schedIndex) else schedIndex := input.schedIndex 170 if (latch) isvec := RegNext(input.isvec) else isvec := input.isvec 171 if (latch) is128bit := RegNext(input.is128bit) else is128bit := input.is128bit 172 if (latch) exp := RegNext(input.exp) else exp := input.exp 173 if (latch) is_first_ele := RegNext(input.is_first_ele) else is_first_ele := input.is_first_ele 174 if (latch) uop_unit_stride_fof := RegNext(input.uop_unit_stride_fof) else uop_unit_stride_fof := input.uop_unit_stride_fof 175 if (latch) reg_offset := RegNext(input.reg_offset) else reg_offset := input.reg_offset 176 if (latch) flowPtr := RegNext(input.flowPtr) else flowPtr := input.flowPtr 177 if (latch) sflowPtr := RegNext(input.sflowPtr) else sflowPtr := input.sflowPtr 178 179 meta_prefetch := DontCare 180 meta_access := DontCare 181 forward_tlDchannel := DontCare 182 mshrid := DontCare 183 replayCarry := DontCare 184 atomic := DontCare 185 isLoadReplay := DontCare 186 isFastPath := DontCare 187 isFastReplay := DontCare 188 handledByMSHR := DontCare 189 replacementUpdated := DontCare 190 missDbUpdated := DontCare 191 delayedLoadError := DontCare 192 lateKill := DontCare 193 feedbacked := DontCare 194 deqPortIdx := DontCare 195 ldCancel := DontCare 196 } 197 198 def asPrefetchReqBundle(): PrefetchReqBundle = { 199 val res = Wire(new PrefetchReqBundle) 200 res.vaddr := this.vaddr 201 res.paddr := this.paddr 202 res.pc := this.uop.pc 203 204 res 205 } 206} 207 208class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 209 210class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 211 // load inst replay informations 212 val rep_info = new LoadToLsqReplayIO 213 // queue entry data, except flag bits, will be updated if writeQueue is true, 214 // valid bit in LqWriteBundle will be ignored 215 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 216 217 218 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false) = { 219 if(latch) vaddr := RegNext(input.vaddr) else vaddr := input.vaddr 220 if(latch) paddr := RegNext(input.paddr) else paddr := input.paddr 221 if(latch) mask := RegNext(input.mask) else mask := input.mask 222 if(latch) data := RegNext(input.data) else data := input.data 223 if(latch) uop := RegNext(input.uop) else uop := input.uop 224 if(latch) wlineflag := RegNext(input.wlineflag) else wlineflag := input.wlineflag 225 if(latch) miss := RegNext(input.miss) else miss := input.miss 226 if(latch) tlbMiss := RegNext(input.tlbMiss) else tlbMiss := input.tlbMiss 227 if(latch) ptwBack := RegNext(input.ptwBack) else ptwBack := input.ptwBack 228 if(latch) mmio := RegNext(input.mmio) else mmio := input.mmio 229 if(latch) atomic := RegNext(input.atomic) else atomic := input.atomic 230 if(latch) rsIdx := RegNext(input.rsIdx) else rsIdx := input.rsIdx 231 if(latch) forwardMask := RegNext(input.forwardMask) else forwardMask := input.forwardMask 232 if(latch) forwardData := RegNext(input.forwardData) else forwardData := input.forwardData 233 if(latch) isPrefetch := RegNext(input.isPrefetch) else isPrefetch := input.isPrefetch 234 if(latch) isHWPrefetch := RegNext(input.isHWPrefetch) else isHWPrefetch := input.isHWPrefetch 235 if(latch) isFirstIssue := RegNext(input.isFirstIssue) else isFirstIssue := input.isFirstIssue 236 if(latch) hasROBEntry := RegNext(input.hasROBEntry) else hasROBEntry := input.hasROBEntry 237 if(latch) isLoadReplay := RegNext(input.isLoadReplay) else isLoadReplay := input.isLoadReplay 238 if(latch) isFastPath := RegNext(input.isFastPath) else isFastPath := input.isFastPath 239 if(latch) isFastReplay := RegNext(input.isFastReplay) else isFastReplay := input.isFastReplay 240 if(latch) mshrid := RegNext(input.mshrid) else mshrid := input.mshrid 241 if(latch) forward_tlDchannel := RegNext(input.forward_tlDchannel) else forward_tlDchannel := input.forward_tlDchannel 242 if(latch) replayCarry := RegNext(input.replayCarry) else replayCarry := input.replayCarry 243 if(latch) dcacheRequireReplay := RegNext(input.dcacheRequireReplay) else dcacheRequireReplay := input.dcacheRequireReplay 244 if(latch) schedIndex := RegNext(input.schedIndex) else schedIndex := input.schedIndex 245 if(latch) handledByMSHR := RegNext(input.handledByMSHR) else handledByMSHR := input.handledByMSHR 246 if(latch) replacementUpdated := RegNext(input.replacementUpdated) else replacementUpdated := input.replacementUpdated 247 if(latch) missDbUpdated := RegNext(input.missDbUpdated) else missDbUpdated := input.missDbUpdated 248 if(latch) delayedLoadError := RegNext(input.delayedLoadError) else delayedLoadError := input.delayedLoadError 249 if(latch) lateKill := RegNext(input.lateKill) else lateKill := input.lateKill 250 if(latch) feedbacked := RegNext(input.feedbacked) else feedbacked := input.feedbacked 251 if(latch) isvec := RegNext(input.isvec) else isvec := input.isvec 252 if(latch) is128bit := RegNext(input.is128bit) else is128bit := input.is128bit 253 if(latch) exp := RegNext(input.exp) else exp := input.exp 254 if(latch) uop_unit_stride_fof := RegNext(input.uop_unit_stride_fof) else uop_unit_stride_fof := input.uop_unit_stride_fof 255 if(latch) reg_offset := RegNext(input.reg_offset) else reg_offset := input.reg_offset 256 257 rep_info := DontCare 258 data_wen_dup := DontCare 259 } 260} 261 262class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 263 val vaddr = Output(UInt(VAddrBits.W)) 264 val paddr = Output(UInt(PAddrBits.W)) 265 val mask = Output(UInt((VLEN/8).W)) 266 val uop = Output(new DynInst) // for replay 267 val pc = Output(UInt(VAddrBits.W)) //for debug 268 val valid = Output(Bool()) 269 270 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 271 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 272 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 273 274 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 275 val sqIdx = Output(new SqPtr) 276 277 // dataInvalid suggests store to load forward found forward should happen, 278 // but data is not available for now. If dataInvalid, load inst should 279 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 280 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 281 282 // matchInvalid suggests in store to load forward logic, paddr cam result does 283 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 284 // should be raised to flush SQ and committed sbuffer. 285 val matchInvalid = Input(Bool()) // resp to load_s2 286 287 // addrInvalid suggests store to load forward found forward should happen, 288 // but address (SSID) is not available for now. If addrInvalid, load inst should 289 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 290 val addrInvalid = Input(Bool()) 291} 292 293// LoadForwardQueryIO used in load pipeline 294// 295// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 296// PipeIO use predecoded sqIdxMask for better forward timing 297class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 298 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 299 // sqIdxMask is calcuated in earlier stage for better timing 300 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 301 302 // dataInvalid: addr match, but data is not valid for now 303 val dataInvalidFast = Input(Bool()) // resp to load_s1 304 // val dataInvalid = Input(Bool()) // resp to load_s2 305 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 306 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 307} 308 309// Query load queue for ld-ld violation 310// 311// Req should be send in load_s1 312// Resp will be generated 1 cycle later 313// 314// Note that query req may be !ready, as dcache is releasing a block 315// If it happens, a replay from rs is needed. 316class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 317 val uop = new DynInst 318 // mask: load's data mask. 319 val mask = UInt((VLEN/8).W) 320 321 // paddr: load's paddr. 322 val paddr = UInt(PAddrBits.W) 323 // dataInvalid: load data is invalid. 324 val data_valid = Bool() 325} 326 327class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 328 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 329 val rep_frm_fetch = Bool() 330} 331 332class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 333 val req = Decoupled(new LoadNukeQueryReq) 334 val resp = Flipped(Valid(new LoadNukeQueryResp)) 335 val revoke = Output(Bool()) 336} 337 338class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 339 // robIdx: Requestor's (a store instruction) rob index for match logic. 340 val robIdx = new RobPtr 341 342 // paddr: requestor's (a store instruction) physical address for match logic. 343 val paddr = UInt(PAddrBits.W) 344 345 // mask: requestor's (a store instruction) data width mask for match logic. 346 val mask = UInt((VLEN/8).W) 347} 348 349// Store byte valid mask write bundle 350// 351// Store byte valid mask write to SQ takes 2 cycles 352class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 353 val sqIdx = new SqPtr 354 val mask = UInt((VLEN/8).W) 355} 356 357class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 358 // old dcache: optimize data sram read fanout 359 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 360 // val bank_oh = UInt(DCacheBanks.W) 361 362 // new dcache 363 val respDcacheData = UInt(VLEN.W) 364 val forwardMask = Vec(VLEN/8, Bool()) 365 val forwardData = Vec(VLEN/8, UInt(8.W)) 366 val uop = new DynInst // for data selection, only fwen and fuOpType are used 367 val addrOffset = UInt(4.W) // for data selection 368 369 // forward tilelink D channel 370 val forward_D = Bool() 371 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 372 373 // forward mshr data 374 val forward_mshr = Bool() 375 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 376 377 val forward_result_valid = Bool() 378 379 def dcacheData(): UInt = { 380 // old dcache 381 // val dcache_data = Mux1H(bank_oh, bankedDcacheData) 382 // new dcache 383 val dcache_data = respDcacheData 384 val use_D = forward_D && forward_result_valid 385 val use_mshr = forward_mshr && forward_result_valid 386 Mux(use_D, forwardData_D.asUInt, Mux(use_mshr, forwardData_mshr.asUInt, dcache_data)) 387 } 388 389 def mergedData(): UInt = { 390 val rdataVec = VecInit((0 until VLEN / 8).map(j => 391 Mux(forwardMask(j), forwardData(j), dcacheData()(8*(j+1)-1, 8*j)) 392 )) 393 rdataVec.asUInt 394 } 395} 396 397// Load writeback data from load queue (refill) 398class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 399 val lqData = UInt(64.W) // load queue has merged data 400 val uop = new DynInst // for data selection, only fwen and fuOpType are used 401 val addrOffset = UInt(3.W) // for data selection 402 403 def mergedData(): UInt = { 404 lqData 405 } 406} 407 408// Bundle for load / store wait waking up 409class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 410 val robIdx = Vec(backendParams.StaCnt, ValidIO(new RobPtr)) 411 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 412} 413 414object AddPipelineReg { 415 class PipelineRegModule[T <: Data](gen: T) extends Module { 416 val io = IO(new Bundle() { 417 val in = Flipped(DecoupledIO(gen.cloneType)) 418 val out = DecoupledIO(gen.cloneType) 419 val isFlush = Input(Bool()) 420 }) 421 422 val valid = RegInit(false.B) 423 valid.suggestName("pipeline_reg_valid") 424 when (io.out.fire) { valid := false.B } 425 when (io.in.fire) { valid := true.B } 426 when (io.isFlush) { valid := false.B } 427 428 io.in.ready := !valid || io.out.ready 429 io.out.bits := RegEnable(io.in.bits, io.in.fire) 430 io.out.valid := valid //&& !isFlush 431 } 432 433 def apply[T <: Data] 434 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 435 moduleName: Option[String] = None 436 ){ 437 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 438 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 439 pipelineReg.io.in <> left 440 right <> pipelineReg.io.out 441 pipelineReg.io.isFlush := isFlush 442 } 443} 444