1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, MemExuInput} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.cache._ 30import xiangshan.backend.fu.FenceToSbuffer 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import math._ 34 35object genWmask { 36 def apply(addr: UInt, sizeEncode: UInt): UInt = { 37 (LookupTree(sizeEncode, List( 38 "b00".U -> 0x1.U, //0001 << addr(2:0) 39 "b01".U -> 0x3.U, //0011 40 "b10".U -> 0xf.U, //1111 41 "b11".U -> 0xff.U //11111111 42 )) << addr(2, 0)).asUInt 43 } 44} 45 46object genVWmask { 47 def apply(addr: UInt, sizeEncode: UInt): UInt = { 48 (LookupTree(sizeEncode, List( 49 "b00".U -> 0x1.U, //0001 << addr(2:0) 50 "b01".U -> 0x3.U, //0011 51 "b10".U -> 0xf.U, //1111 52 "b11".U -> 0xff.U //11111111 53 )) << addr(3, 0)).asUInt 54 } 55} 56 57object genWdata { 58 def apply(data: UInt, sizeEncode: UInt): UInt = { 59 LookupTree(sizeEncode, List( 60 "b00".U -> Fill(16, data(7, 0)), 61 "b01".U -> Fill(8, data(15, 0)), 62 "b10".U -> Fill(4, data(31, 0)), 63 "b11".U -> Fill(2, data(63,0)) 64 )) 65 } 66} 67 68object shiftDataToLow { 69 def apply(addr: UInt,data : UInt): UInt = { 70 Mux(addr(3), (data >> 64).asUInt,data) 71 } 72} 73object shiftMaskToLow { 74 def apply(addr: UInt,mask: UInt): UInt = { 75 Mux(addr(3),(mask >> 8).asUInt,mask) 76 } 77} 78 79class LsPipelineBundle(implicit p: Parameters) extends XSBundle 80 with HasDCacheParameters 81 with HasVLSUParameters { 82 val uop = new DynInst 83 val vaddr = UInt(VAddrBits.W) 84 // For exception vaddr generate 85 val fullva = UInt(XLEN.W) 86 val vaNeedExt = Bool() 87 val isHyper = Bool() 88 val paddr = UInt(PAddrBits.W) 89 val gpaddr = UInt(XLEN.W) 90 val isForVSnonLeafPTE = Bool() 91 // val func = UInt(6.W) 92 val mask = UInt((VLEN/8).W) 93 val data = UInt((VLEN+1).W) 94 val wlineflag = Bool() // store write the whole cache line 95 96 val miss = Bool() 97 val tlbMiss = Bool() 98 val ptwBack = Bool() 99 val af = Bool() 100 val nc = Bool() 101 val mmio = Bool() 102 val atomic = Bool() 103 104 val forwardMask = Vec(VLEN/8, Bool()) 105 val forwardData = Vec(VLEN/8, UInt(8.W)) 106 107 // prefetch 108 val isPrefetch = Bool() 109 val isHWPrefetch = Bool() 110 def isSWPrefetch = isPrefetch && !isHWPrefetch 111 112 // misalignBuffer 113 val isFrmMisAlignBuf = Bool() 114 115 // vector 116 val isvec = Bool() 117 val isLastElem = Bool() 118 val is128bit = Bool() 119 val uop_unit_stride_fof = Bool() 120 val usSecondInv = Bool() 121 val elemIdx = UInt(elemIdxBits.W) 122 val alignedType = UInt(alignTypeBits.W) 123 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 124 // val rob_idx_valid = Vec(2,Bool()) 125 // val inner_idx = Vec(2,UInt(3.W)) 126 // val rob_idx = Vec(2,new RobPtr) 127 val reg_offset = UInt(vOffsetBits.W) 128 val elemIdxInsideVd = UInt(elemIdxBits.W) 129 // val offset = Vec(2,UInt(4.W)) 130 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 131 val is_first_ele = Bool() 132 val vecBaseVaddr = UInt(VAddrBits.W) 133 val vecVaddrOffset = UInt(VAddrBits.W) 134 val vecTriggerMask = UInt((VLEN/8).W) 135 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 136 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 137 138 // For debug usage 139 val isFirstIssue = Bool() 140 val hasROBEntry = Bool() 141 142 // For load replay 143 val isLoadReplay = Bool() 144 val isFastPath = Bool() 145 val isFastReplay = Bool() 146 val replayCarry = new ReplayCarry(nWays) 147 148 // For dcache miss load 149 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 150 val handledByMSHR = Bool() 151 val replacementUpdated = Bool() 152 val missDbUpdated = Bool() 153 154 val forward_tlDchannel = Bool() 155 val dcacheRequireReplay = Bool() 156 val delayedLoadError = Bool() 157 val lateKill = Bool() 158 val feedbacked = Bool() 159 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 160 // loadQueueReplay index. 161 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 162 // hardware prefetch and fast replay no need to query tlb 163 val tlbNoQuery = Bool() 164} 165 166class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 167 val meta_prefetch = UInt(L1PfSourceBits.W) 168 val meta_access = Bool() 169 170 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 171 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 172 if (latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 173 if (latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 174 if (latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 175 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 176 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 177 if (latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 178 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 179 if (latch) data := RegEnable(input.data, enable) else data := input.data 180 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 181 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 182 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 183 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 184 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 185 if (latch) af := RegEnable(input.af, enable) else af := input.af 186 if (latch) nc := RegEnable(input.nc, enable) else nc := input.nc 187 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 188 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 189 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 190 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 191 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 192 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 193 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 194 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 195 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 196 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 197 if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery 198 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 199 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 200 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 201 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 202 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 203 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 204 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 205 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 206 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 207 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 208 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 209 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 210 if (latch) vecBaseVaddr := RegEnable(input.vecBaseVaddr, enable) else vecBaseVaddr := input.vecBaseVaddr 211 if (latch) vecVaddrOffset := RegEnable(input.vecVaddrOffset, enable) else vecVaddrOffset := input.vecVaddrOffset 212 if (latch) vecTriggerMask := RegEnable(input.vecTriggerMask, enable) else vecTriggerMask := input.vecTriggerMask 213 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 214 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 215 216 meta_prefetch := DontCare 217 meta_access := DontCare 218 forward_tlDchannel := DontCare 219 mshrid := DontCare 220 replayCarry := DontCare 221 atomic := DontCare 222 isLoadReplay := DontCare 223 isFastPath := DontCare 224 isFastReplay := DontCare 225 handledByMSHR := DontCare 226 replacementUpdated := DontCare 227 missDbUpdated := DontCare 228 delayedLoadError := DontCare 229 lateKill := DontCare 230 feedbacked := DontCare 231 ldCancel := DontCare 232 } 233 234 def asPrefetchReqBundle(): PrefetchReqBundle = { 235 val res = Wire(new PrefetchReqBundle) 236 res.vaddr := this.vaddr 237 res.paddr := this.paddr 238 res.pc := this.uop.pc 239 res.miss := this.miss 240 res.pfHitStream := isFromStream(this.meta_prefetch) 241 242 res 243 } 244} 245 246class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 247 248class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 249 // load inst replay informations 250 val rep_info = new LoadToLsqReplayIO 251 // queue entry data, except flag bits, will be updated if writeQueue is true, 252 // valid bit in LqWriteBundle will be ignored 253 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 254 255 256 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 257 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 258 if(latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 259 if(latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 260 if(latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 261 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 262 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 263 if(latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 264 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 265 if(latch) data := RegEnable(input.data, enable) else data := input.data 266 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 267 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 268 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 269 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 270 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 271 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 272 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 273 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 274 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 275 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 276 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 277 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 278 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 279 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 280 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 281 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 282 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 283 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 284 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 285 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 286 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 287 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 288 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 289 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 290 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 291 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 292 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 293 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 294 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 295 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 296 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 297 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 298 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 299 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 300 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 301 302 rep_info := DontCare 303 data_wen_dup := DontCare 304 } 305} 306 307class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 308 val need_rep = Bool() 309} 310 311class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 312 val vaddr = Output(UInt(VAddrBits.W)) 313 val paddr = Output(UInt(PAddrBits.W)) 314 val mask = Output(UInt((VLEN/8).W)) 315 val uop = Output(new DynInst) // for replay 316 val pc = Output(UInt(VAddrBits.W)) //for debug 317 val valid = Output(Bool()) 318 319 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 320 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 321 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 322 323 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 324 val sqIdx = Output(new SqPtr) 325 326 // dataInvalid suggests store to load forward found forward should happen, 327 // but data is not available for now. If dataInvalid, load inst should 328 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 329 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 330 331 // matchInvalid suggests in store to load forward logic, paddr cam result does 332 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 333 // should be raised to flush SQ and committed sbuffer. 334 val matchInvalid = Input(Bool()) // resp to load_s2 335 336 // addrInvalid suggests store to load forward found forward should happen, 337 // but address (SSID) is not available for now. If addrInvalid, load inst should 338 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 339 val addrInvalid = Input(Bool()) 340} 341 342// LoadForwardQueryIO used in load pipeline 343// 344// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 345// PipeIO use predecoded sqIdxMask for better forward timing 346class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 347 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 348 // sqIdxMask is calcuated in earlier stage for better timing 349 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 350 351 // dataInvalid: addr match, but data is not valid for now 352 val dataInvalidFast = Input(Bool()) // resp to load_s1 353 // val dataInvalid = Input(Bool()) // resp to load_s2 354 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 355 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 356} 357 358// Query load queue for ld-ld violation 359// 360// Req should be send in load_s1 361// Resp will be generated 1 cycle later 362// 363// Note that query req may be !ready, as dcache is releasing a block 364// If it happens, a replay from rs is needed. 365class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 366 val uop = new DynInst 367 // mask: load's data mask. 368 val mask = UInt((VLEN/8).W) 369 370 // paddr: load's paddr. 371 val paddr = UInt(PAddrBits.W) 372 // dataInvalid: load data is invalid. 373 val data_valid = Bool() 374 // nc: is NC access 375 val is_nc = Bool() 376} 377 378class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 379 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 380 val rep_frm_fetch = Bool() 381} 382 383class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 384 val req = Decoupled(new LoadNukeQueryReq) 385 val resp = Flipped(Valid(new LoadNukeQueryResp)) 386 val revoke = Output(Bool()) 387} 388 389class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 390 // robIdx: Requestor's (a store instruction) rob index for match logic. 391 val robIdx = new RobPtr 392 393 // paddr: requestor's (a store instruction) physical address for match logic. 394 val paddr = UInt(PAddrBits.W) 395 396 // mask: requestor's (a store instruction) data width mask for match logic. 397 val mask = UInt((VLEN/8).W) 398 399 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 400 val matchLine = Bool() 401} 402 403class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 404 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 405 val control = Output(new XSBundle { 406 // control sq to write-into sb 407 val writeSb = Bool() 408 val wdata = UInt(VLEN.W) 409 val wmask = UInt((VLEN / 8).W) 410 val paddr = UInt(PAddrBits.W) 411 val vaddr = UInt(VAddrBits.W) 412 val last = Bool() 413 val hasException = Bool() 414 // remove this entry in sq 415 val removeSq = Bool() 416 }) 417 // from storeQueue to storeMisalignBuffer, provide detail info of this store 418 val storeInfo = Input(new XSBundle { 419 val data = UInt(VLEN.W) 420 // is the data of the unaligned store ready at sq? 421 val dataReady = Bool() 422 // complete a data transfer from sq to sb 423 val completeSbTrans = Bool() 424 }) 425} 426 427// Store byte valid mask write bundle 428// 429// Store byte valid mask write to SQ takes 2 cycles 430class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 431 val sqIdx = new SqPtr 432 val mask = UInt((VLEN/8).W) 433} 434 435class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 436 // old dcache: optimize data sram read fanout 437 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 438 // val bank_oh = UInt(DCacheBanks.W) 439 440 // new dcache 441 val respDcacheData = UInt(VLEN.W) 442 val forwardMask = Vec(VLEN/8, Bool()) 443 val forwardData = Vec(VLEN/8, UInt(8.W)) 444 val uop = new DynInst // for data selection, only fwen and fuOpType are used 445 val addrOffset = UInt(4.W) // for data selection 446 447 // forward tilelink D channel 448 val forward_D = Bool() 449 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 450 451 // forward mshr data 452 val forward_mshr = Bool() 453 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 454 455 val forward_result_valid = Bool() 456 457 def mergeTLData(): UInt = { 458 // merge TL D or MSHR data at load s2 459 val dcache_data = respDcacheData 460 val use_D = forward_D && forward_result_valid 461 val use_mshr = forward_mshr && forward_result_valid 462 Mux( 463 use_D || use_mshr, 464 Mux( 465 use_D, 466 forwardData_D.asUInt, 467 forwardData_mshr.asUInt 468 ), 469 dcache_data 470 ) 471 } 472 473 def mergeLsqFwdData(dcacheData: UInt): UInt = { 474 // merge dcache and lsq forward data at load s3 475 val rdataVec = VecInit((0 until VLEN / 8).map(j => 476 Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j)) 477 )) 478 rdataVec.asUInt 479 } 480} 481 482// Load writeback data from load queue (refill) 483class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 484 val lqData = UInt(64.W) // load queue has merged data 485 val uop = new DynInst // for data selection, only fwen and fuOpType are used 486 val addrOffset = UInt(3.W) // for data selection 487 488 def mergedData(): UInt = { 489 lqData 490 } 491} 492 493// Bundle for load / store wait waking up 494class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 495 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 496 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 497} 498 499object AddPipelineReg { 500 class PipelineRegModule[T <: Data](gen: T) extends Module { 501 val io = IO(new Bundle() { 502 val in = Flipped(DecoupledIO(gen.cloneType)) 503 val out = DecoupledIO(gen.cloneType) 504 val isFlush = Input(Bool()) 505 }) 506 507 val valid = RegInit(false.B) 508 valid.suggestName("pipeline_reg_valid") 509 when (io.out.fire) { valid := false.B } 510 when (io.in.fire) { valid := true.B } 511 when (io.isFlush) { valid := false.B } 512 513 io.in.ready := !valid || io.out.ready 514 io.out.bits := RegEnable(io.in.bits, io.in.fire) 515 io.out.valid := valid //&& !isFlush 516 } 517 518 def apply[T <: Data] 519 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 520 moduleName: Option[String] = None 521 ): Unit = { 522 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 523 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 524 pipelineReg.io.in <> left 525 right <> pipelineReg.io.out 526 pipelineReg.io.isFlush := isFlush 527 } 528}