xref: /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala (revision b52348ae0426bffb9826f33c51928739b9d7f47e)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19
20import chipsalliance.rocketchip.config.Parameters
21import chisel3._
22import chisel3.util._
23import xiangshan._
24import utils._
25import utility._
26import xiangshan.backend.rob.RobPtr
27import xiangshan.cache._
28import xiangshan.backend.fu.FenceToSbuffer
29import xiangshan.cache.dcache.ReplayCarry
30
31object genWmask {
32  def apply(addr: UInt, sizeEncode: UInt): UInt = {
33    (LookupTree(sizeEncode, List(
34      "b00".U -> 0x1.U, //0001 << addr(2:0)
35      "b01".U -> 0x3.U, //0011
36      "b10".U -> 0xf.U, //1111
37      "b11".U -> 0xff.U //11111111
38    )) << addr(2, 0)).asUInt()
39  }
40}
41
42object genWdata {
43  def apply(data: UInt, sizeEncode: UInt): UInt = {
44    LookupTree(sizeEncode, List(
45      "b00".U -> Fill(8, data(7, 0)),
46      "b01".U -> Fill(4, data(15, 0)),
47      "b10".U -> Fill(2, data(31, 0)),
48      "b11".U -> data
49    ))
50  }
51}
52
53class LsPipelineBundle(implicit p: Parameters) extends XSBundleWithMicroOp with HasDCacheParameters{
54  val vaddr = UInt(VAddrBits.W)
55  val paddr = UInt(PAddrBits.W)
56  // val func = UInt(6.W)
57  val mask = UInt(8.W)
58  val data = UInt((XLEN+1).W)
59  val wlineflag = Bool() // store write the whole cache line
60
61  val miss = Bool()
62  val tlbMiss = Bool()
63  val ptwBack = Bool()
64  val mmio = Bool()
65  val atomic = Bool()
66  val rsIdx = UInt(log2Up(IssQueSize).W)
67
68  val forwardMask = Vec(8, Bool())
69  val forwardData = Vec(8, UInt(8.W))
70
71  // prefetch
72  val isPrefetch = Bool()
73  val isHWPrefetch = Bool()
74
75  // For debug usage
76  val isFirstIssue = Bool()
77
78  // For load replay
79  val isLoadReplay = Bool()
80  val replayCarry = new ReplayCarry
81
82  // For dcache miss load
83  val mshrid = UInt(log2Up(cfg.nMissEntries).W)
84
85  val forward_tlDchannel = Bool()
86}
87
88class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle {
89  // queue entry data, except flag bits, will be updated if writeQueue is true,
90  // valid bit in LqWriteBundle will be ignored
91  val lq_data_wen_dup = Vec(6, Bool()) // dirty reg dup
92
93  def fromLsPipelineBundle(input: LsPipelineBundle) = {
94    vaddr := input.vaddr
95    paddr := input.paddr
96    mask := input.mask
97    data := input.data
98    uop := input.uop
99    wlineflag := input.wlineflag
100    miss := input.miss
101    tlbMiss := input.tlbMiss
102    ptwBack := input.ptwBack
103    mmio := input.mmio
104    atomic := input.atomic
105    rsIdx := input.rsIdx
106    forwardMask := input.forwardMask
107    forwardData := input.forwardData
108    isPrefetch := input.isPrefetch
109    isHWPrefetch := input.isHWPrefetch
110    isFirstIssue := input.isFirstIssue
111    isLoadReplay := input.isLoadReplay
112    mshrid := input.mshrid
113    forward_tlDchannel := input.forward_tlDchannel
114    replayCarry := input.replayCarry
115
116    lq_data_wen_dup := DontCare
117  }
118}
119
120class LoadForwardQueryIO(implicit p: Parameters) extends XSBundleWithMicroOp {
121  val vaddr = Output(UInt(VAddrBits.W))
122  val paddr = Output(UInt(PAddrBits.W))
123  val mask = Output(UInt(8.W))
124  override val uop = Output(new MicroOp) // for replay
125  val pc = Output(UInt(VAddrBits.W)) //for debug
126  val valid = Output(Bool())
127
128  val forwardMaskFast = Input(Vec(8, Bool())) // resp to load_s1
129  val forwardMask = Input(Vec(8, Bool())) // resp to load_s2
130  val forwardData = Input(Vec(8, UInt(8.W))) // resp to load_s2
131
132  // val lqIdx = Output(UInt(LoadQueueIdxWidth.W))
133  val sqIdx = Output(new SqPtr)
134
135  // dataInvalid suggests store to load forward found forward should happen,
136  // but data is not available for now. If dataInvalid, load inst should
137  // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid
138  val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now
139
140  // matchInvalid suggests in store to load forward logic, paddr cam result does
141  // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception
142  // should be raised to flush SQ and committed sbuffer.
143  val matchInvalid = Input(Bool()) // resp to load_s2
144}
145
146// LoadForwardQueryIO used in load pipeline
147//
148// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO:
149// PipeIO use predecoded sqIdxMask for better forward timing
150class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO {
151  // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons
152  // sqIdxMask is calcuated in earlier stage for better timing
153  val sqIdxMask = Output(UInt(StoreQueueSize.W))
154
155  // dataInvalid: addr match, but data is not valid for now
156  val dataInvalidFast = Input(Bool()) // resp to load_s1
157  // val dataInvalid = Input(Bool()) // resp to load_s2
158  val dataInvalidSqIdx = Input(UInt(log2Up(StoreQueueSize).W)) // resp to load_s2, sqIdx value
159}
160
161// Query load queue for ld-ld violation
162//
163// Req should be send in load_s1
164// Resp will be generated 1 cycle later
165//
166// Note that query req may be !ready, as dcache is releasing a block
167// If it happens, a replay from rs is needed.
168
169class LoadViolationQueryReq(implicit p: Parameters) extends XSBundleWithMicroOp { // provide lqIdx
170  val paddr = UInt(PAddrBits.W)
171}
172
173class LoadViolationQueryResp(implicit p: Parameters) extends XSBundle {
174  val have_violation = Bool()
175}
176
177class LoadViolationQueryIO(implicit p: Parameters) extends XSBundle {
178  val req = Decoupled(new LoadViolationQueryReq)
179  val resp = Flipped(Valid(new LoadViolationQueryResp))
180}
181
182class LoadReExecuteQueryIO(implicit p: Parameters) extends XSBundle {
183  //  robIdx: Requestor's (a store instruction) rob index for match logic.
184  val robIdx = new RobPtr
185
186  //  paddr: requestor's (a store instruction) physical address for match logic.
187  val paddr = UInt(PAddrBits.W)
188
189  //  mask: requestor's (a store instruction) data width mask for match logic.
190  val mask = UInt(8.W)
191}
192
193// Store byte valid mask write bundle
194//
195// Store byte valid mask write to SQ takes 2 cycles
196class StoreMaskBundle(implicit p: Parameters) extends XSBundle {
197  val sqIdx = new SqPtr
198  val mask = UInt(8.W)
199}
200
201class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle {
202  // old dcache: optimize data sram read fanout
203  // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W))
204  // val bank_oh = UInt(DCacheBanks.W)
205
206  // new dcache
207  val respDcacheData = UInt(XLEN.W)
208  val forwardMask = Vec(8, Bool())
209  val forwardData = Vec(8, UInt(8.W))
210  val uop = new MicroOp // for data selection, only fwen and fuOpType are used
211  val addrOffset = UInt(3.W) // for data selection
212
213  // forward tilelink D channel
214  val forward_D = Input(Bool())
215  val forwardData_D = Input(Vec(8, UInt(8.W)))
216
217  // forward mshr data
218  val forward_mshr = Input(Bool())
219  val forwardData_mshr = Input(Vec(8, UInt(8.W)))
220
221  val forward_result_valid = Input(Bool())
222
223  def dcacheData(): UInt = {
224    // old dcache
225    // val dcache_data = Mux1H(bank_oh, bankedDcacheData)
226    // new dcache
227    val dcache_data = respDcacheData
228    val use_D = forward_D && forward_result_valid
229    val use_mshr = forward_mshr && forward_result_valid
230    Mux(use_D, forwardData_D.asUInt, Mux(use_mshr, forwardData_mshr.asUInt, dcache_data))
231  }
232
233  def mergedData(): UInt = {
234    val rdataVec = VecInit((0 until XLEN / 8).map(j =>
235      Mux(forwardMask(j), forwardData(j), dcacheData()(8*(j+1)-1, 8*j))
236    ))
237    rdataVec.asUInt
238  }
239}
240
241// Load writeback data from load queue (refill)
242class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle {
243  val lqData = UInt(64.W) // load queue has merged data
244  val uop = new MicroOp // for data selection, only fwen and fuOpType are used
245  val addrOffset = UInt(3.W) // for data selection
246
247  def mergedData(): UInt = {
248    lqData
249  }
250}
251
252// Bundle for load / store wait waking up
253class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle {
254  val staIssue = Vec(exuParameters.StuCnt, ValidIO(new ExuInput))
255  val stdIssue = Vec(exuParameters.StuCnt, ValidIO(new ExuInput))
256}
257
258object AddPipelineReg {
259  class PipelineRegModule[T <: Data](gen: T) extends Module {
260    val io = IO(new Bundle() {
261      val in = Flipped(DecoupledIO(gen.cloneType))
262      val out = DecoupledIO(gen.cloneType)
263      val isFlush = Input(Bool())
264    })
265
266    val valid = RegInit(false.B)
267    valid.suggestName("pipeline_reg_valid")
268    when (io.out.fire()) { valid := false.B }
269    when (io.in.fire()) { valid := true.B }
270    when (io.isFlush) { valid := false.B }
271
272    io.in.ready := !valid || io.out.ready
273    io.out.bits := RegEnable(io.in.bits, io.in.fire())
274    io.out.valid := valid //&& !isFlush
275  }
276
277  def apply[T <: Data]
278  (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool,
279   moduleName: Option[String] = None
280  ){
281    val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType))
282    if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get)
283    pipelineReg.io.in <> left
284    right <> pipelineReg.io.out
285    pipelineReg.io.isFlush := isFlush
286  }
287}
288